mirror of
https://github.com/golang/go.git
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cmd: update golang.org/x/arch for riscv64 disassembler
Update to a newer version of golang.org/x/arch, in order to bring in changes to the riscv64 disassembler: go get golang.org/x/arch@master go mod vendor go mod tidy Change-Id: I6e3ece09e72e36d50bae8341832d5b8f7e330e72 Reviewed-on: https://go-review.googlesource.com/c/go/+/778961 Reviewed-by: Keith Randall <khr@golang.org> Auto-Submit: Joel Sing <joel@sing.id.au> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
This commit is contained in:
Joel Sing
Gopher Robot
parent
c3f7d75877
commit
fd7a0e680d
7 changed files with 200 additions and 31 deletions
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@ -4,7 +4,7 @@ go 1.27
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require (
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github.com/google/pprof v0.0.0-20260115054156-294ebfa9ad83
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golang.org/x/arch v0.23.1-0.20260109160903-657d90bd6695
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golang.org/x/arch v0.27.1-0.20260513003155-2ebc08890589
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golang.org/x/build v0.0.0-20260122183339-3ba88df37c64
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golang.org/x/mod v0.36.1-0.20260513122029-343ee60345a1
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golang.org/x/sync v0.20.0
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@ -6,8 +6,8 @@ github.com/ianlancetaylor/demangle v0.0.0-20250417193237-f615e6bd150b h1:ogbOPx8
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github.com/ianlancetaylor/demangle v0.0.0-20250417193237-f615e6bd150b/go.mod h1:gx7rwoVhcfuVKG5uya9Hs3Sxj7EIvldVofAWIUtGouw=
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github.com/yuin/goldmark v1.6.0 h1:boZcn2GTjpsynOsC0iJHnBWa4Bi0qzfJjthwauItG68=
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github.com/yuin/goldmark v1.6.0/go.mod h1:6yULJ656Px+3vBD8DxQVa3kxgyrAnzto9xy5taEt/CY=
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golang.org/x/arch v0.23.1-0.20260109160903-657d90bd6695 h1:q45HsUyFzBjBk4mHGgUewJf6KKOkNiWB8wMx0X6elyA=
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golang.org/x/arch v0.23.1-0.20260109160903-657d90bd6695/go.mod h1:dNHoOeKiyja7GTvF9NJS1l3Z2yntpQNzgrjh1cU103A=
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golang.org/x/arch v0.27.1-0.20260513003155-2ebc08890589 h1:vhLfA6kUzRvCYV5uFBJbdMndztX1STqGC8GmQJsuldY=
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golang.org/x/arch v0.27.1-0.20260513003155-2ebc08890589/go.mod h1:0X+GdSIP+kL5wPmpK7sdkEVTt2XoYP0cSjQSbZBwOi8=
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golang.org/x/build v0.0.0-20260122183339-3ba88df37c64 h1:BNhBATNmH/VtzGolB+ksQPPvn6ZyffiR8TmKenqNo+A=
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golang.org/x/build v0.0.0-20260122183339-3ba88df37c64/go.mod h1:3QmSbNil8ZWqC94m80Glej1v8b92gYzPIQPTtSa0c+4=
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golang.org/x/mod v0.36.1-0.20260513122029-343ee60345a1 h1:C0TwvxhsI0bHc1TbK4QEa5PCMrHiST7y/lpX4MVW3KM=
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21
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go
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vendored
21
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/plan9x.go
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vendored
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@ -52,31 +52,18 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text
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// Move addressing mode into opcode suffix.
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suffix := ""
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switch inst.Op {
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case LDR, LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH, STUR, STURB, STURH, LD1, ST1:
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switch mem := inst.Args[1].(type) {
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for i := range inst.Args {
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switch mem := inst.Args[i].(type) {
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case MemImmediate:
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switch mem.Mode {
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case AddrOffset:
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// no suffix
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case AddrPreIndex:
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suffix = ".W"
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suffix += ".W"
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case AddrPostIndex, AddrPostReg:
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suffix = ".P"
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suffix += ".P"
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}
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}
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case STP, LDP:
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switch mem := inst.Args[2].(type) {
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case MemImmediate:
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switch mem.Mode {
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case AddrOffset:
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// no suffix
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case AddrPreIndex:
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suffix = ".W"
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case AddrPostIndex:
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suffix = ".P"
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}
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}
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}
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44
src/cmd/vendor/golang.org/x/arch/riscv64/riscv64asm/gnu.go
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44
src/cmd/vendor/golang.org/x/arch/riscv64/riscv64asm/gnu.go
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@ -29,8 +29,9 @@ func GNUSyntax(inst Inst) string {
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}
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op := strings.ToLower(inst.Op.String())
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gnuSyntaxSwitch:
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switch inst.Op {
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case ADDI, ADDIW, ANDI, ORI, SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW, XORI:
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case ADDI, ADDIW, ANDI, SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW, XORI:
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if inst.Op == ADDI {
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if inst.Args[1].(Reg) == X0 && inst.Args[0].(Reg) != X0 {
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op = "li"
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@ -65,6 +66,25 @@ func GNUSyntax(inst Inst) string {
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args = args[:len(args)-1]
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}
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case ORI:
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if inst.Args[0].(Reg) == X0 {
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simm := inst.Args[2].(Simm)
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switch simm.Imm & 0b11111 {
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case 0:
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op = "prefetch.i"
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case 1:
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op = "prefetch.r"
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case 3:
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op = "prefetch.w"
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default:
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break gnuSyntaxSwitch
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}
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// compared to ORI, the lowest 5 bits of simm.Imm in PREFETCH should be zeros
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simm.Imm = simm.Imm &^ 0b11111
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args[0] = RegOffset{inst.Args[1].(Reg), simm}.String()
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args = args[:len(args)-2]
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}
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case ADD:
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if inst.Args[1].(Reg) == X0 {
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op = "mv"
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@ -221,11 +241,25 @@ func GNUSyntax(inst Inst) string {
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args = args[:len(args)-1]
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}
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// When both pred and succ equals to iorw, the GNU objdump will omit them.
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case FENCE:
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if inst.Args[0].(MemOrder).String() == "iorw" &&
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inst.Args[1].(MemOrder).String() == "iorw" {
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args = nil
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fm := inst.Enc >> 28
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pred := inst.Args[0].(MemOrder).String()
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succ := inst.Args[1].(MemOrder).String()
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if fm == 0b1000 {
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if pred == "rw" && succ == "rw" {
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return "fence.tso"
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}
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return op
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}
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// PAUSE is encoded as a FENCE instruction with pred=W, succ=0.
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if pred == "w" && succ == "" {
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return "pause"
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}
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if fm != 0 || pred == "" || succ == "" || (pred == "iorw" && succ == "iorw") {
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// We've either got a full fence or a reserved encoding which should be
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// treated as a full fence. When both pred and succ equals to iorw, GNU
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// objdump will omit them.
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return op
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}
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case FSGNJX_D:
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41
src/cmd/vendor/golang.org/x/arch/riscv64/riscv64asm/plan9x.go
generated
vendored
41
src/cmd/vendor/golang.org/x/arch/riscv64/riscv64asm/plan9x.go
generated
vendored
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@ -44,6 +44,7 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text
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op := inst.Op.String()
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goSyntaxSwitch:
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switch inst.Op {
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case AMOADD_D, AMOADD_D_AQ, AMOADD_D_RL, AMOADD_D_AQRL, AMOADD_W, AMOADD_W_AQ,
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@ -74,6 +75,25 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text
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args = args[:len(args)-1]
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}
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case ORI:
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if inst.Args[0].(Reg) == X0 {
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simm := inst.Args[2].(Simm)
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switch simm.Imm & 0b11111 {
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case 0:
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op = "PREFETCHI"
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case 1:
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op = "PREFETCHR"
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case 3:
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op = "PREFETCHW"
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default:
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break goSyntaxSwitch
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}
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// compared to ORI, the lowest 5 bits of simm.Imm in PREFETCH should be zeros
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simm.Imm = simm.Imm &^ 0b11111
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args[0] = plan9Arg(&inst, pc, symname, RegOffset{inst.Args[1].(Reg), simm})
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args = args[:len(args)-2]
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}
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case ANDI:
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if inst.Args[2].(Simm).Imm == 255 {
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op = "MOVBU"
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@ -179,9 +199,26 @@ func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text
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}
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}
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// Fence instruction in plan9 doesn't have any operands.
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case FENCE:
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args = nil
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fm := inst.Enc >> 28
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pred := inst.Args[0].(MemOrder).String()
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succ := inst.Args[1].(MemOrder).String()
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if fm == 0b1000 {
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if pred == "rw" && succ == "rw" {
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return "FENCE.TSO"
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}
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return op
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}
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// PAUSE is encoded as a FENCE instruction with pred=W, succ=0.
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if pred == "w" && succ == "" {
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return "PAUSE"
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}
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if fm != 0 || pred == "" || succ == "" || (pred == "iorw" && succ == "iorw") {
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// We've either got a full fence or a reserved encoding which should be
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// treated as a full fence.
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return op
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}
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args[0], args[1] = args[1], args[0]
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case FMADD_D, FMADD_H, FMADD_Q, FMADD_S, FMSUB_D, FMSUB_H,
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FMSUB_Q, FMSUB_S, FNMADD_D, FNMADD_H, FNMADD_Q, FNMADD_S,
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115
src/cmd/vendor/golang.org/x/arch/riscv64/riscv64asm/tables.go
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115
src/cmd/vendor/golang.org/x/arch/riscv64/riscv64asm/tables.go
generated
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@ -1,5 +1,4 @@
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// Code generated by riscv64spec riscv-opcodes
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// DO NOT EDIT
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// Code generated by 'go run ../riscv64spec riscv-opcodes'; DO NOT EDIT.
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// Copyright 2024 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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@ -104,6 +103,13 @@ const (
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BNE
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BSET
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BSETI
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CBO_CLEAN
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CBO_FLUSH
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CBO_INVAL
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CBO_ZERO
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CLMUL
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CLMULH
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CLMULR
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CLZ
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CLZW
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CPOP
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@ -375,6 +381,27 @@ const (
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VAADDU_VX
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VAADD_VV
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VAADD_VX
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VAESDF_VS
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VAESDF_VV
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VAESDM_VS
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VAESDM_VV
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VAESEF_VS
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VAESEF_VV
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VAESEM_VS
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VAESEM_VV
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VAESKF1_VI
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VAESKF2_VI
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VAESZ_VS
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VGHSH_VV
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VGMUL_VV
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VSHA2CH_VV
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VSHA2CL_VV
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VSHA2MS_VV
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VSM3C_VI
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VSM3ME_VV
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VSM4K_VI
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VSM4R_VS
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VSM4R_VV
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VADC_VIM
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VADC_VVM
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VADC_VXM
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@ -1100,6 +1127,13 @@ var opstr = [...]string{
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BNE: "BNE",
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BSET: "BSET",
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BSETI: "BSETI",
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CBO_CLEAN: "CBO.CLEAN",
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CBO_FLUSH: "CBO.FLUSH",
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CBO_INVAL: "CBO.INVAL",
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CBO_ZERO: "CBO.ZERO",
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CLMUL: "CLMUL",
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CLMULH: "CLMULH",
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CLMULR: "CLMULR",
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CLZ: "CLZ",
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CLZW: "CLZW",
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CPOP: "CPOP",
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@ -1371,6 +1405,27 @@ var opstr = [...]string{
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VAADDU_VX: "VAADDU.VX",
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VAADD_VV: "VAADD.VV",
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VAADD_VX: "VAADD.VX",
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VAESDF_VS: "VAESDF.VS",
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VAESDF_VV: "VAESDF.VV",
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VAESDM_VS: "VAESDM.VS",
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VAESDM_VV: "VAESDM.VV",
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VAESEF_VS: "VAESEF.VS",
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VAESEF_VV: "VAESEF.VV",
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VAESEM_VS: "VAESEM.VS",
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VAESEM_VV: "VAESEM.VV",
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VAESKF1_VI: "VAESKF1.VI",
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VAESKF2_VI: "VAESKF2.VI",
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VAESZ_VS: "VAESZ.VS",
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VGHSH_VV: "VGHSH.VV",
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VGMUL_VV: "VGMUL.VV",
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VSHA2CH_VV: "VSHA2CH.VV",
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VSHA2CL_VV: "VSHA2CL.VV",
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VSHA2MS_VV: "VSHA2MS.VV",
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VSM3C_VI: "VSM3C.VI",
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VSM3ME_VV: "VSM3ME.VV",
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VSM4K_VI: "VSM4K.VI",
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VSM4R_VS: "VSM4R.VS",
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VSM4R_VV: "VSM4R.VV",
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VADC_VIM: "VADC.VIM",
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VADC_VVM: "VADC.VVM",
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VADC_VXM: "VADC.VXM",
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@ -2191,6 +2246,20 @@ var instFormats = [...]instFormat{
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{mask: 0xfe00707f, value: 0x28001033, op: BSET, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
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// BSETI rd, rs1, shamt6
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{mask: 0xfc00707f, value: 0x28001013, op: BSETI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}},
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// CBO.CLEAN rs1_ptr
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{mask: 0xfff07fff, value: 0x0010200f, op: CBO_CLEAN, args: argTypeList{arg_rs1_ptr}},
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// CBO.FLUSH rs1_ptr
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{mask: 0xfff07fff, value: 0x0020200f, op: CBO_FLUSH, args: argTypeList{arg_rs1_ptr}},
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// CBO.INVAL rs1_ptr
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{mask: 0xfff07fff, value: 0x0000200f, op: CBO_INVAL, args: argTypeList{arg_rs1_ptr}},
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// CBO.ZERO rs1_ptr
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{mask: 0xfff07fff, value: 0x0040200f, op: CBO_ZERO, args: argTypeList{arg_rs1_ptr}},
|
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// CLMUL rd, rs1, rs2
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{mask: 0xfe00707f, value: 0x0a001033, op: CLMUL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
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// CLMULH rd, rs1, rs2
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{mask: 0xfe00707f, value: 0x0a003033, op: CLMULH, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
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// CLMULR rd, rs1, rs2
|
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{mask: 0xfe00707f, value: 0x0a002033, op: CLMULR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}},
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||||
// CLZ rd, rs1
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{mask: 0xfff0707f, value: 0x60001013, op: CLZ, args: argTypeList{arg_rd, arg_rs1}},
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||||
// CLZW rd, rs1
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||||
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@ -2733,6 +2802,48 @@ var instFormats = [...]instFormat{
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|||
{mask: 0xfc00707f, value: 0x24002057, op: VAADD_VV, args: argTypeList{arg_vm, arg_vs2, arg_vs1, arg_vd}},
|
||||
// VAADD.VX vm, vs2, rs1, vd
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{mask: 0xfc00707f, value: 0x24006057, op: VAADD_VX, args: argTypeList{arg_vm, arg_vs2, arg_rs1, arg_vd}},
|
||||
// VAESDF.VS vs2, vd
|
||||
{mask: 0xfe0ff07f, value: 0xa600a077, op: VAESDF_VS, args: argTypeList{arg_vs2, arg_vd}},
|
||||
// VAESDF.VV vs2, vd
|
||||
{mask: 0xfe0ff07f, value: 0xa200a077, op: VAESDF_VV, args: argTypeList{arg_vs2, arg_vd}},
|
||||
// VAESDM.VS vs2, vd
|
||||
{mask: 0xfe0ff07f, value: 0xa6002077, op: VAESDM_VS, args: argTypeList{arg_vs2, arg_vd}},
|
||||
// VAESDM.VV vs2, vd
|
||||
{mask: 0xfe0ff07f, value: 0xa2002077, op: VAESDM_VV, args: argTypeList{arg_vs2, arg_vd}},
|
||||
// VAESEF.VS vs2, vd
|
||||
{mask: 0xfe0ff07f, value: 0xa601a077, op: VAESEF_VS, args: argTypeList{arg_vs2, arg_vd}},
|
||||
// VAESEF.VV vs2, vd
|
||||
{mask: 0xfe0ff07f, value: 0xa201a077, op: VAESEF_VV, args: argTypeList{arg_vs2, arg_vd}},
|
||||
// VAESEM.VS vs2, vd
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||||
{mask: 0xfe0ff07f, value: 0xa6012077, op: VAESEM_VS, args: argTypeList{arg_vs2, arg_vd}},
|
||||
// VAESEM.VV vs2, vd
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||||
{mask: 0xfe0ff07f, value: 0xa2012077, op: VAESEM_VV, args: argTypeList{arg_vs2, arg_vd}},
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||||
// VAESKF1.VI vs2, zimm, vd
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||||
{mask: 0xfe00707f, value: 0x8a002077, op: VAESKF1_VI, args: argTypeList{arg_vs2, arg_zimm, arg_vd}},
|
||||
// VAESKF2.VI vs2, zimm, vd
|
||||
{mask: 0xfe00707f, value: 0xaa002077, op: VAESKF2_VI, args: argTypeList{arg_vs2, arg_zimm, arg_vd}},
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||||
// VAESZ.VS vs2, vd
|
||||
{mask: 0xfe0ff07f, value: 0xa603a077, op: VAESZ_VS, args: argTypeList{arg_vs2, arg_vd}},
|
||||
// VGHSH.VV vs2, vs1, vd
|
||||
{mask: 0xfe00707f, value: 0xb2002077, op: VGHSH_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
|
||||
// VGMUL.VV vs2, vd
|
||||
{mask: 0xfe0ff07f, value: 0xa208a077, op: VGMUL_VV, args: argTypeList{arg_vs2, arg_vd}},
|
||||
// VSHA2CH.VV vs2, vs1, vd
|
||||
{mask: 0xfe00707f, value: 0xba002077, op: VSHA2CH_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
|
||||
// VSHA2CL.VV vs2, vs1, vd
|
||||
{mask: 0xfe00707f, value: 0xbe002077, op: VSHA2CL_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
|
||||
// VSHA2MS.VV vs2, vs1, vd
|
||||
{mask: 0xfe00707f, value: 0xb6002077, op: VSHA2MS_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
|
||||
// VSM3C.VI vs2, zimm, vd
|
||||
{mask: 0xfe00707f, value: 0xae002077, op: VSM3C_VI, args: argTypeList{arg_vs2, arg_zimm, arg_vd}},
|
||||
// VSM3ME.VV vs2, vs1, vd
|
||||
{mask: 0xfe00707f, value: 0x82002077, op: VSM3ME_VV, args: argTypeList{arg_vs2, arg_vs1, arg_vd}},
|
||||
// VSM4K.VI vs2, zimm, vd
|
||||
{mask: 0xfe00707f, value: 0x86002077, op: VSM4K_VI, args: argTypeList{arg_vs2, arg_zimm, arg_vd}},
|
||||
// VSM4R.VS vs2, vd
|
||||
{mask: 0xfe0ff07f, value: 0xa6082077, op: VSM4R_VS, args: argTypeList{arg_vs2, arg_vd}},
|
||||
// VSM4R.VV vs2, vd
|
||||
{mask: 0xfe0ff07f, value: 0xa2082077, op: VSM4R_VV, args: argTypeList{arg_vs2, arg_vd}},
|
||||
// VADC.VIM vs2, simm5, vd
|
||||
{mask: 0xfe00707f, value: 0x40003057, op: VADC_VIM, args: argTypeList{arg_vs2, arg_simm5, arg_vd}},
|
||||
// VADC.VVM vs2, vs1, vd
|
||||
|
|
|
|||
4
src/cmd/vendor/modules.txt
vendored
4
src/cmd/vendor/modules.txt
vendored
|
|
@ -16,8 +16,8 @@ github.com/google/pprof/third_party/svgpan
|
|||
# github.com/ianlancetaylor/demangle v0.0.0-20250417193237-f615e6bd150b
|
||||
## explicit; go 1.13
|
||||
github.com/ianlancetaylor/demangle
|
||||
# golang.org/x/arch v0.23.1-0.20260109160903-657d90bd6695
|
||||
## explicit; go 1.24.0
|
||||
# golang.org/x/arch v0.27.1-0.20260513003155-2ebc08890589
|
||||
## explicit; go 1.25.0
|
||||
golang.org/x/arch/arm/armasm
|
||||
golang.org/x/arch/arm64/arm64asm
|
||||
golang.org/x/arch/loong64/loong64asm
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue