Fixes#74076
Change-Id: Icc67b3d4e342f329584433bd1250c56ae8f5a73d
Reviewed-on: https://go-review.googlesource.com/c/go/+/690635
Reviewed-by: Alan Donovan <adonovan@google.com>
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before:
MOVV $n + $offset, Roff
PRELDX (Rbase)(Roff), $hint
after:
PRELDX offset(Rbase), $n, $hint
This instruction is supported in CL 671875, but is not actually used
Change-Id: I943d488ea6dc77781cd796ef480a89fede666bab
Reviewed-on: https://go-review.googlesource.com/c/go/+/673155
Reviewed-by: Meidan Li <limeidan@loongson.cn>
Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
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In order to make it easier to write in assembly and to be consistent
with the usage of general instructions, a new assembly format is
added for the instructions VANDV and VANDB.
It also works for instructions XVAND{V,B}, [X]V{OR,XOR,NOR,ANDN,ORN}V
and [X]V{OR,XOR,NOR}B.
Change-Id: Ia75d607ac918950e58840ec627aaf0be45d837fe
Reviewed-on: https://go-review.googlesource.com/c/go/+/671316
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On loong64, BFPT and BFPF are mapped to the platform assembly as follows:
Go asm syntax:
BFPT FCCx, offs21
BFPF FCCx, offs21
Equivalent platform assembler syntax:
bcnez cj, offs21
bceqz cj, offs21
If the condition register is not specified, it defaults to FCC0.
Change-Id: I2cc3df62a9c55d4b5eb124789358983c6737319c
Reviewed-on: https://go-review.googlesource.com/c/go/+/667456
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Junyang Shao <shaojunyang@google.com>
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This CL refers to the implementation of ARM64 and adds support for the following
types of SIMD instructions:
1. Move general-purpose register to a vector element, e.g.:
VMOVQ Rj, <Vd>.<T>[index]
<T> can have the following values:
B, H, W, V
2. Move vector element to general-purpose register, e.g.:
VMOVQ <Vj>.<T>[index], Rd
<T> can have the following values:
B, BU, H, HU, W, WU, VU
3. Duplicate general-purpose register to vector, e.g.:
VMOVQ Rj, <Vd>.<T>
<T> can have the following values:
B16, H8, W4, V2, B32, H16, W8, V4
4. Move vector, e.g.:
XVMOVQ Xj, <Xd>.<T>
<T> can have the following values:
B16, H8, W4, V2, Q1
5. Move vector element to scalar, e.g.:
XVMOVQ Xj, <Xd>.<T>[index]
XVMOVQ Xj.<T>[index], Xd
<T> can have the following values:
W, V
6. Move vector element to vector register, e.g.:
VMOVQ <Vn>.<T>[index], Vn.<T>
<T> can have the following values:
B, H, W, V
This CL only adds syntax and doesn't break any assembly that already exists.
Change-Id: I7656efac6def54da6c5ae182f39c2a21bfdf92bb
Reviewed-on: https://go-review.googlesource.com/c/go/+/616258
Reviewed-by: David Chase <drchase@google.com>
Reviewed-by: Meidan Li <limeidan@loongson.cn>
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Reviewed-by: Cherry Mui <cherryyz@google.com>
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8-bit and 16-bit sign extensions and 32-bit zero extensions were realized
with left and right shifts before this change. We now support assembling
EXTWB, EXTWH and BSTRPICKV, so all three can be done with a single insn
respectively.
This patch is a copy of CL 479496.
Co-authored-by: WANG Xuerui <git@xen0n.name>
Change-Id: Iee5741dd9ebb25746f51008f3f6c86704339d615
Reviewed-on: https://go-review.googlesource.com/c/go/+/626195
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
Reviewed-by: David Chase <drchase@google.com>
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The old API was to do
r := obj.AddRel(sym)
r.Type = this
r.Off = that
etc
The new API is:
sym.AddRel(ctxt, obj.Reloc{Type: this: Off: that, etc})
This new API is more idiomatic and avoids ever having relocations
that are only partially constructed. Most importantly, it sets up
for sym.AddRel being able to check relocation validity in the future.
(Passing ctxt is for use in validity checking.)
Passes golang.org/x/tools/cmd/toolstash/buildall.
Change-Id: I042ea76e61bb3bf6402f98ca11291a13f4799972
Reviewed-on: https://go-review.googlesource.com/c/go/+/625616
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Add support for assembling the FMA instructions present in the LoongArch
base ISA v1.00. This requires adding a new instruction format and making
use of a third source operand, which is put in RestArgs[0].
The single-precision instructions have the `.s` prefix in their official
mnemonics, and similar Go asm instructions all have `S` prefix for the
other architectures having FMA support, but in this change they instead
have `F` prefix in Go asm because loong64 currently follows the mips
backends in the naming convention. This could be changed later because
FMA is fully expressible in pure Go, making it unlikely to have to hand-
write such assembly in the wild.
Example mapping between actual encoding and Go asm syntax:
fmadd.s fd, fj, fk, fa -> FMADDF fa, fk, fj, fd
(prog.From = fa, prog.Reg = fk, prog.RestArgs[0] = fj and prog.To = fd)
fmadd.s fd, fd, fk, fa -> FMADDF fa, fk, fd
(prog.From = fa, prog.Reg = fk and prog.To = fd)
This patch is a copy of CL 477716.
Co-authored-by: WANG Xuerui <git@xen0n.name>
Change-Id: I9b4e4c601d6c5a854ee238f085849666e4faf090
Reviewed-on: https://go-review.googlesource.com/c/go/+/623877
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
Reviewed-by: Cherry Mui <cherryyz@google.com>
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This patch is a copy of CL 478595.
Co-authored-by: WANG Xuerui <git@xen0n.name>
Change-Id: Ifb6e8183c83a5dfe5dec84e173a74d5de62692a0
Reviewed-on: https://go-review.googlesource.com/c/go/+/623875
Reviewed-by: Carlos Amedee <carlos@golang.org>
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Reviewed-by: Michael Pratt <mpratt@google.com>
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All remaining unary bitop instructions in the LoongArch v1.00 base ISA
are added with this change.
While at it, add the missing W suffix to the current CLO/CLZ names. They
are not used anywhere as far as we know, so no breakage is expected.
Also, stop reusing SLL's instruction format for simplicity, in favor of
a new but trivial instruction format case.
This patch is a copy of CL 477717.
Co-authored-by: WANG Xuerui <git@xen0n.name>
Change-Id: Idbcaca25dda1ed313674ef8b26da722e8d7151c0
Reviewed-on: https://go-review.googlesource.com/c/go/+/623876
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with slices there's no need to implement sort.Interface
Change-Id: I59167e78881cb1df89a71e33d738d6aeca7adb71
GitHub-Last-Rev: 507ba84453
GitHub-Pull-Request: golang/go#68724
Reviewed-on: https://go-review.googlesource.com/c/go/+/602895
Reviewed-by: Ian Lance Taylor <iant@golang.org>
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Go asm syntax example:
MOVV R4, FCSR0
MOVV FCSR1, R5
MOVV F4, FCC0
MOVV FCC1, F5
Equivalent platform assembler syntax:
movgr2fcsr fcsr0, r4
movfcsr2gr r5, fcsr1
movfr2cf fcc0, f4
movcf2fr f5, fcc1
Ref: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html
This change also merges the case of floating point move instructions
and add checks for the range of special registers.
Change-Id: Ib08fbce83e7a31dc0ab4857bf9ba959855241d1c
Reviewed-on: https://go-review.googlesource.com/c/go/+/580279
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There is no need to check whether the symbol is empty, since we have already
checked it before. In addition, it is enough to use C_ADDR to represent memory
access, C_LEXT and C_SEXT are not needed.
Change-Id: I7158d6b549482b35cd9ac5fba781648fb3f21922
Reviewed-on: https://go-review.googlesource.com/c/go/+/565615
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Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn>
If p.To.Sym is nil, that means we can get the target offset from
p.To.Target().pc - c.pc，only when p.To.Sym is not nil, we need relocation
to get the true address of target symbol.
Change-Id: Ied52f675c6aa6e8fb8d972b7699f5cadd1ecb268
Reviewed-on: https://go-review.googlesource.com/c/go/+/565627
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Reviewed-by: Meidan Li <limeidan@loongson.cn>
When the kind of the operand is TYPE_BRANCH, we cannot determine
whether it is a long branch or a short branch, so we merge these
two classes into one.
Change-Id: I7d7fa8f62ff02791ec3de4e3e3f7610bc9cb1743
Reviewed-on: https://go-review.googlesource.com/c/go/+/565626
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The instructions belonging to case 32 have the same structure as the
instructions in case 2.
The instructions in case 33 are actually two-register operation
instructions. We move their definitions from function oprrr to oprr and
merge their implementation into case 9.
Change-Id: Id04aaa497e78d8198a58f8d406876d16b3f393a7
Reviewed-on: https://go-review.googlesource.com/c/go/+/565616
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The plan9 instructions ASLLV and -ASLLV are translated into the same assembly
instructions, so -ASLLV can be removed and replaced with ASLLV in the
corresponding position.
ASRLV and -ASRLV have the same reason as the above two instructions.
Change-Id: I4bd79ca7bb070f7a924a0205ef2f19cf2b9ae2c9
Reviewed-on: https://go-review.googlesource.com/c/go/+/565623
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