// autogenerated: do not edit! // generated from gen/*Ops.go package ssa import ( "cmd/internal/obj" "cmd/internal/obj/arm" "cmd/internal/obj/ppc64" "cmd/internal/obj/x86" ) const ( BlockInvalid BlockKind = iota BlockAMD64EQ BlockAMD64NE BlockAMD64LT BlockAMD64LE BlockAMD64GT BlockAMD64GE BlockAMD64ULT BlockAMD64ULE BlockAMD64UGT BlockAMD64UGE BlockAMD64EQF BlockAMD64NEF BlockAMD64ORD BlockAMD64NAN BlockARMEQ BlockARMNE BlockARMLT BlockARMLE BlockARMGT BlockARMGE BlockARMULT BlockARMULE BlockARMUGT BlockARMUGE BlockPlain BlockIf BlockCall BlockDefer BlockCheck BlockRet BlockRetJmp BlockExit BlockFirst BlockPPC64EQ BlockPPC64NE BlockPPC64LT BlockPPC64LE BlockPPC64GT BlockPPC64GE BlockPPC64ULT BlockPPC64ULE BlockPPC64UGT BlockPPC64UGE ) var blockString = [...]string{ BlockInvalid: "BlockInvalid", BlockAMD64EQ: "EQ", BlockAMD64NE: "NE", BlockAMD64LT: "LT", BlockAMD64LE: "LE", BlockAMD64GT: "GT", BlockAMD64GE: "GE", BlockAMD64ULT: "ULT", BlockAMD64ULE: "ULE", BlockAMD64UGT: "UGT", BlockAMD64UGE: "UGE", BlockAMD64EQF: "EQF", BlockAMD64NEF: "NEF", BlockAMD64ORD: "ORD", BlockAMD64NAN: "NAN", BlockARMEQ: "EQ", BlockARMNE: "NE", BlockARMLT: "LT", BlockARMLE: "LE", BlockARMGT: "GT", BlockARMGE: "GE", BlockARMULT: "ULT", BlockARMULE: "ULE", BlockARMUGT: "UGT", BlockARMUGE: "UGE", BlockPlain: "Plain", BlockIf: "If", BlockCall: "Call", BlockDefer: "Defer", BlockCheck: "Check", BlockRet: "Ret", BlockRetJmp: "RetJmp", BlockExit: "Exit", BlockFirst: "First", BlockPPC64EQ: "EQ", BlockPPC64NE: "NE", BlockPPC64LT: "LT", BlockPPC64LE: "LE", BlockPPC64GT: "GT", BlockPPC64GE: "GE", BlockPPC64ULT: "ULT", BlockPPC64ULE: "ULE", BlockPPC64UGT: "UGT", BlockPPC64UGE: "UGE", } func (k BlockKind) String() string { return blockString[k] } const ( OpInvalid Op = iota OpAMD64ADDSS OpAMD64ADDSD OpAMD64SUBSS OpAMD64SUBSD OpAMD64MULSS OpAMD64MULSD OpAMD64DIVSS OpAMD64DIVSD OpAMD64MOVSSload OpAMD64MOVSDload OpAMD64MOVSSconst OpAMD64MOVSDconst OpAMD64MOVSSloadidx1 OpAMD64MOVSSloadidx4 OpAMD64MOVSDloadidx1 OpAMD64MOVSDloadidx8 OpAMD64MOVSSstore OpAMD64MOVSDstore OpAMD64MOVSSstoreidx1 OpAMD64MOVSSstoreidx4 OpAMD64MOVSDstoreidx1 OpAMD64MOVSDstoreidx8 OpAMD64ADDQ OpAMD64ADDL OpAMD64ADDQconst OpAMD64ADDLconst OpAMD64SUBQ OpAMD64SUBL OpAMD64SUBQconst OpAMD64SUBLconst OpAMD64MULQ OpAMD64MULL OpAMD64MULQconst OpAMD64MULLconst OpAMD64HMULQ OpAMD64HMULL OpAMD64HMULW OpAMD64HMULB OpAMD64HMULQU OpAMD64HMULLU OpAMD64HMULWU OpAMD64HMULBU OpAMD64AVGQU OpAMD64DIVQ OpAMD64DIVL OpAMD64DIVW OpAMD64DIVQU OpAMD64DIVLU OpAMD64DIVWU OpAMD64MODQ OpAMD64MODL OpAMD64MODW OpAMD64MODQU OpAMD64MODLU OpAMD64MODWU OpAMD64ANDQ OpAMD64ANDL OpAMD64ANDQconst OpAMD64ANDLconst OpAMD64ORQ OpAMD64ORL OpAMD64ORQconst OpAMD64ORLconst OpAMD64XORQ OpAMD64XORL OpAMD64XORQconst OpAMD64XORLconst OpAMD64CMPQ OpAMD64CMPL OpAMD64CMPW OpAMD64CMPB OpAMD64CMPQconst OpAMD64CMPLconst OpAMD64CMPWconst OpAMD64CMPBconst OpAMD64UCOMISS OpAMD64UCOMISD OpAMD64TESTQ OpAMD64TESTL OpAMD64TESTW OpAMD64TESTB OpAMD64TESTQconst OpAMD64TESTLconst OpAMD64TESTWconst OpAMD64TESTBconst OpAMD64SHLQ OpAMD64SHLL OpAMD64SHLQconst OpAMD64SHLLconst OpAMD64SHRQ OpAMD64SHRL OpAMD64SHRW OpAMD64SHRB OpAMD64SHRQconst OpAMD64SHRLconst OpAMD64SHRWconst OpAMD64SHRBconst OpAMD64SARQ OpAMD64SARL OpAMD64SARW OpAMD64SARB OpAMD64SARQconst OpAMD64SARLconst OpAMD64SARWconst OpAMD64SARBconst OpAMD64ROLQconst OpAMD64ROLLconst OpAMD64ROLWconst OpAMD64ROLBconst OpAMD64NEGQ OpAMD64NEGL OpAMD64NOTQ OpAMD64NOTL OpAMD64BSFQ OpAMD64BSFL OpAMD64BSFW OpAMD64BSRQ OpAMD64BSRL OpAMD64BSRW OpAMD64CMOVQEQconst OpAMD64CMOVLEQconst OpAMD64CMOVWEQconst OpAMD64CMOVQNEconst OpAMD64CMOVLNEconst OpAMD64CMOVWNEconst OpAMD64BSWAPQ OpAMD64BSWAPL OpAMD64SQRTSD OpAMD64SBBQcarrymask OpAMD64SBBLcarrymask OpAMD64SETEQ OpAMD64SETNE OpAMD64SETL OpAMD64SETLE OpAMD64SETG OpAMD64SETGE OpAMD64SETB OpAMD64SETBE OpAMD64SETA OpAMD64SETAE OpAMD64SETEQF OpAMD64SETNEF OpAMD64SETORD OpAMD64SETNAN OpAMD64SETGF OpAMD64SETGEF OpAMD64MOVBQSX OpAMD64MOVBQZX OpAMD64MOVWQSX OpAMD64MOVWQZX OpAMD64MOVLQSX OpAMD64MOVLQZX OpAMD64MOVLconst OpAMD64MOVQconst OpAMD64CVTTSD2SL OpAMD64CVTTSD2SQ OpAMD64CVTTSS2SL OpAMD64CVTTSS2SQ OpAMD64CVTSL2SS OpAMD64CVTSL2SD OpAMD64CVTSQ2SS OpAMD64CVTSQ2SD OpAMD64CVTSD2SS OpAMD64CVTSS2SD OpAMD64PXOR OpAMD64LEAQ OpAMD64LEAQ1 OpAMD64LEAQ2 OpAMD64LEAQ4 OpAMD64LEAQ8 OpAMD64MOVBload OpAMD64MOVBQSXload OpAMD64MOVWload OpAMD64MOVWQSXload OpAMD64MOVLload OpAMD64MOVLQSXload OpAMD64MOVQload OpAMD64MOVBstore OpAMD64MOVWstore OpAMD64MOVLstore OpAMD64MOVQstore OpAMD64MOVOload OpAMD64MOVOstore OpAMD64MOVBloadidx1 OpAMD64MOVWloadidx1 OpAMD64MOVWloadidx2 OpAMD64MOVLloadidx1 OpAMD64MOVLloadidx4 OpAMD64MOVQloadidx1 OpAMD64MOVQloadidx8 OpAMD64MOVBstoreidx1 OpAMD64MOVWstoreidx1 OpAMD64MOVWstoreidx2 OpAMD64MOVLstoreidx1 OpAMD64MOVLstoreidx4 OpAMD64MOVQstoreidx1 OpAMD64MOVQstoreidx8 OpAMD64MOVBstoreconst OpAMD64MOVWstoreconst OpAMD64MOVLstoreconst OpAMD64MOVQstoreconst OpAMD64MOVBstoreconstidx1 OpAMD64MOVWstoreconstidx1 OpAMD64MOVWstoreconstidx2 OpAMD64MOVLstoreconstidx1 OpAMD64MOVLstoreconstidx4 OpAMD64MOVQstoreconstidx1 OpAMD64MOVQstoreconstidx8 OpAMD64DUFFZERO OpAMD64MOVOconst OpAMD64REPSTOSQ OpAMD64CALLstatic OpAMD64CALLclosure OpAMD64CALLdefer OpAMD64CALLgo OpAMD64CALLinter OpAMD64DUFFCOPY OpAMD64REPMOVSQ OpAMD64InvertFlags OpAMD64LoweredGetG OpAMD64LoweredGetClosurePtr OpAMD64LoweredNilCheck OpAMD64MOVQconvert OpAMD64FlagEQ OpAMD64FlagLT_ULT OpAMD64FlagLT_UGT OpAMD64FlagGT_UGT OpAMD64FlagGT_ULT OpARMADD OpARMADDconst OpARMSUB OpARMSUBconst OpARMRSB OpARMRSBconst OpARMMUL OpARMHMUL OpARMHMULU OpARMDIV OpARMDIVU OpARMMOD OpARMMODU OpARMADDS OpARMADC OpARMSUBS OpARMSBC OpARMMULLU OpARMMULA OpARMADDF OpARMADDD OpARMSUBF OpARMSUBD OpARMMULF OpARMMULD OpARMDIVF OpARMDIVD OpARMAND OpARMANDconst OpARMOR OpARMORconst OpARMXOR OpARMXORconst OpARMBIC OpARMBICconst OpARMMVN OpARMSQRTD OpARMSLL OpARMSLLconst OpARMSRL OpARMSRLconst OpARMSRA OpARMSRAconst OpARMSRRconst OpARMCMP OpARMCMPconst OpARMCMN OpARMCMNconst OpARMTST OpARMTSTconst OpARMTEQ OpARMTEQconst OpARMCMPF OpARMCMPD OpARMMOVWconst OpARMMOVFconst OpARMMOVDconst OpARMMOVWaddr OpARMMOVBload OpARMMOVBUload OpARMMOVHload OpARMMOVHUload OpARMMOVWload OpARMMOVFload OpARMMOVDload OpARMMOVBstore OpARMMOVHstore OpARMMOVWstore OpARMMOVFstore OpARMMOVDstore OpARMMOVBreg OpARMMOVBUreg OpARMMOVHreg OpARMMOVHUreg OpARMMOVWF OpARMMOVWD OpARMMOVWUF OpARMMOVWUD OpARMMOVFW OpARMMOVDW OpARMMOVFWU OpARMMOVDWU OpARMMOVFD OpARMMOVDF OpARMCALLstatic OpARMCALLclosure OpARMCALLdefer OpARMCALLgo OpARMCALLinter OpARMLoweredNilCheck OpARMEqual OpARMNotEqual OpARMLessThan OpARMLessEqual OpARMGreaterThan OpARMGreaterEqual OpARMLessThanU OpARMLessEqualU OpARMGreaterThanU OpARMGreaterEqualU OpARMCarry OpARMLoweredSelect0 OpARMLoweredSelect1 OpARMLoweredZeromask OpARMDUFFZERO OpARMDUFFCOPY OpARMLoweredZero OpARMLoweredMove OpARMLoweredGetClosurePtr OpARMMOVWconvert OpAdd8 OpAdd16 OpAdd32 OpAdd64 OpAddPtr OpAdd32F OpAdd64F OpSub8 OpSub16 OpSub32 OpSub64 OpSubPtr OpSub32F OpSub64F OpMul8 OpMul16 OpMul32 OpMul64 OpMul32F OpMul64F OpDiv32F OpDiv64F OpHmul8 OpHmul8u OpHmul16 OpHmul16u OpHmul32 OpHmul32u OpHmul64 OpHmul64u OpAvg64u OpDiv8 OpDiv8u OpDiv16 OpDiv16u OpDiv32 OpDiv32u OpDiv64 OpDiv64u OpMod8 OpMod8u OpMod16 OpMod16u OpMod32 OpMod32u OpMod64 OpMod64u OpAnd8 OpAnd16 OpAnd32 OpAnd64 OpOr8 OpOr16 OpOr32 OpOr64 OpXor8 OpXor16 OpXor32 OpXor64 OpLsh8x8 OpLsh8x16 OpLsh8x32 OpLsh8x64 OpLsh16x8 OpLsh16x16 OpLsh16x32 OpLsh16x64 OpLsh32x8 OpLsh32x16 OpLsh32x32 OpLsh32x64 OpLsh64x8 OpLsh64x16 OpLsh64x32 OpLsh64x64 OpRsh8x8 OpRsh8x16 OpRsh8x32 OpRsh8x64 OpRsh16x8 OpRsh16x16 OpRsh16x32 OpRsh16x64 OpRsh32x8 OpRsh32x16 OpRsh32x32 OpRsh32x64 OpRsh64x8 OpRsh64x16 OpRsh64x32 OpRsh64x64 OpRsh8Ux8 OpRsh8Ux16 OpRsh8Ux32 OpRsh8Ux64 OpRsh16Ux8 OpRsh16Ux16 OpRsh16Ux32 OpRsh16Ux64 OpRsh32Ux8 OpRsh32Ux16 OpRsh32Ux32 OpRsh32Ux64 OpRsh64Ux8 OpRsh64Ux16 OpRsh64Ux32 OpRsh64Ux64 OpLrot8 OpLrot16 OpLrot32 OpLrot64 OpEq8 OpEq16 OpEq32 OpEq64 OpEqPtr OpEqInter OpEqSlice OpEq32F OpEq64F OpNeq8 OpNeq16 OpNeq32 OpNeq64 OpNeqPtr OpNeqInter OpNeqSlice OpNeq32F OpNeq64F OpLess8 OpLess8U OpLess16 OpLess16U OpLess32 OpLess32U OpLess64 OpLess64U OpLess32F OpLess64F OpLeq8 OpLeq8U OpLeq16 OpLeq16U OpLeq32 OpLeq32U OpLeq64 OpLeq64U OpLeq32F OpLeq64F OpGreater8 OpGreater8U OpGreater16 OpGreater16U OpGreater32 OpGreater32U OpGreater64 OpGreater64U OpGreater32F OpGreater64F OpGeq8 OpGeq8U OpGeq16 OpGeq16U OpGeq32 OpGeq32U OpGeq64 OpGeq64U OpGeq32F OpGeq64F OpAndB OpOrB OpEqB OpNeqB OpNot OpNeg8 OpNeg16 OpNeg32 OpNeg64 OpNeg32F OpNeg64F OpCom8 OpCom16 OpCom32 OpCom64 OpCtz16 OpCtz32 OpCtz64 OpClz16 OpClz32 OpClz64 OpBswap32 OpBswap64 OpSqrt OpPhi OpCopy OpConvert OpConstBool OpConstString OpConstNil OpConst8 OpConst16 OpConst32 OpConst64 OpConst32F OpConst64F OpConstInterface OpConstSlice OpInitMem OpArg OpAddr OpSP OpSB OpFunc OpLoad OpStore OpMove OpZero OpClosureCall OpStaticCall OpDeferCall OpGoCall OpInterCall OpSignExt8to16 OpSignExt8to32 OpSignExt8to64 OpSignExt16to32 OpSignExt16to64 OpSignExt32to64 OpZeroExt8to16 OpZeroExt8to32 OpZeroExt8to64 OpZeroExt16to32 OpZeroExt16to64 OpZeroExt32to64 OpTrunc16to8 OpTrunc32to8 OpTrunc32to16 OpTrunc64to8 OpTrunc64to16 OpTrunc64to32 OpCvt32to32F OpCvt32to64F OpCvt64to32F OpCvt64to64F OpCvt32Fto32 OpCvt32Fto64 OpCvt64Fto32 OpCvt64Fto64 OpCvt32Fto64F OpCvt64Fto32F OpIsNonNil OpIsInBounds OpIsSliceInBounds OpNilCheck OpGetG OpGetClosurePtr OpArrayIndex OpPtrIndex OpOffPtr OpSliceMake OpSlicePtr OpSliceLen OpSliceCap OpComplexMake OpComplexReal OpComplexImag OpStringMake OpStringPtr OpStringLen OpIMake OpITab OpIData OpStructMake0 OpStructMake1 OpStructMake2 OpStructMake3 OpStructMake4 OpStructSelect OpStoreReg OpLoadReg OpFwdRef OpUnknown OpVarDef OpVarKill OpVarLive OpKeepAlive OpInt64Make OpInt64Hi OpInt64Lo OpAdd32carry OpAdd32withcarry OpSub32carry OpSub32withcarry OpMul32uhilo OpSignmask OpZeromask OpCvt32Uto32F OpCvt32Uto64F OpCvt32Fto32U OpCvt64Fto32U OpSelect0 OpSelect1 OpPPC64ADD OpPPC64ADDconst OpPPC64FADD OpPPC64FADDS OpPPC64SUB OpPPC64FSUB OpPPC64FSUBS OpPPC64MULLD OpPPC64MULLW OpPPC64FMUL OpPPC64FMULS OpPPC64FDIV OpPPC64FDIVS OpPPC64AND OpPPC64ANDconst OpPPC64OR OpPPC64ORconst OpPPC64XOR OpPPC64XORconst OpPPC64NEG OpPPC64MOVBreg OpPPC64MOVBZreg OpPPC64MOVHreg OpPPC64MOVHZreg OpPPC64MOVWreg OpPPC64MOVWZreg OpPPC64MOVBload OpPPC64MOVBZload OpPPC64MOVHload OpPPC64MOVHZload OpPPC64MOVWload OpPPC64MOVWZload OpPPC64MOVDload OpPPC64FMOVDload OpPPC64FMOVSload OpPPC64MOVBstore OpPPC64MOVHstore OpPPC64MOVWstore OpPPC64MOVDstore OpPPC64FMOVDstore OpPPC64FMOVSstore OpPPC64MOVBstoreconst OpPPC64MOVHstoreconst OpPPC64MOVWstoreconst OpPPC64MOVDstoreconst OpPPC64MOVDconst OpPPC64MOVWconst OpPPC64MOVHconst OpPPC64MOVBconst OpPPC64FMOVDconst OpPPC64FMOVSconst OpPPC64FCMPU OpPPC64CMP OpPPC64CMPU OpPPC64CMPW OpPPC64CMPWU OpPPC64CMPconst OpPPC64CALLstatic OpPPC64Equal OpPPC64NotEqual OpPPC64LessThan OpPPC64LessEqual OpPPC64GreaterThan OpPPC64GreaterEqual ) var opcodeTable = [...]opInfo{ {name: "OpInvalid"}, { name: "ADDSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "ADDSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "SUBSS", argLen: 2, resultInArg0: true, asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, clobbers: 2147483648, // X15 outputs: []regMask{ 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "SUBSD", argLen: 2, resultInArg0: true, asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, clobbers: 2147483648, // X15 outputs: []regMask{ 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MULSS", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MULSD", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "DIVSS", argLen: 2, resultInArg0: true, asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, clobbers: 2147483648, // X15 outputs: []regMask{ 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "DIVSD", argLen: 2, resultInArg0: true, asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, clobbers: 2147483648, // X15 outputs: []regMask{ 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { name: "MOVSSload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSDload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: x86.AMOVSS, reg: regInfo{ outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: x86.AMOVSD, reg: regInfo{ outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSSloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSSloadidx4", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSDloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSDloadidx8", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVSSstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVSDstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVSSstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVSSstoreidx4", auxType: auxSymOff, argLen: 4, asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVSDstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVSDstoreidx8", auxType: auxSymOff, argLen: 4, asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "ADDQ", argLen: 2, commutative: true, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ADDL", argLen: 2, commutative: true, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ADDQconst", auxType: auxInt64, argLen: 1, asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ADDLconst", auxType: auxInt32, argLen: 1, asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SUBQ", argLen: 2, resultInArg0: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SUBL", argLen: 2, resultInArg0: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SUBQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SUBLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MULQ", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MULL", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MULQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MULLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "HMULQ", argLen: 2, asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "HMULL", argLen: 2, asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "HMULW", argLen: 2, asm: x86.AIMULW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "HMULB", argLen: 2, asm: x86.AIMULB, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "HMULQU", argLen: 2, asm: x86.AMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "HMULLU", argLen: 2, asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "HMULWU", argLen: 2, asm: x86.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "HMULBU", argLen: 2, asm: x86.AMULB, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "AVGQU", argLen: 2, commutative: true, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "DIVQ", argLen: 2, asm: x86.AIDIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934596, // DX FLAGS outputs: []regMask{ 1, // AX }, }, }, { name: "DIVL", argLen: 2, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934596, // DX FLAGS outputs: []regMask{ 1, // AX }, }, }, { name: "DIVW", argLen: 2, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934596, // DX FLAGS outputs: []regMask{ 1, // AX }, }, }, { name: "DIVQU", argLen: 2, asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934596, // DX FLAGS outputs: []regMask{ 1, // AX }, }, }, { name: "DIVLU", argLen: 2, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934596, // DX FLAGS outputs: []regMask{ 1, // AX }, }, }, { name: "DIVWU", argLen: 2, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934596, // DX FLAGS outputs: []regMask{ 1, // AX }, }, }, { name: "MODQ", argLen: 2, asm: x86.AIDIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "MODL", argLen: 2, asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "MODW", argLen: 2, asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "MODQU", argLen: 2, asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "MODLU", argLen: 2, asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "MODWU", argLen: 2, asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // AX {1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 4, // DX }, }, }, { name: "ANDQ", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ANDL", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ANDQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ANDLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ORQ", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ORL", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ORQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "XORQ", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "XORL", argLen: 2, commutative: true, resultInArg0: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "XORQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "XORLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMPQ", argLen: 2, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "CMPL", argLen: 2, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "CMPW", argLen: 2, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "CMPB", argLen: 2, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "CMPQconst", auxType: auxInt64, argLen: 1, asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "CMPLconst", auxType: auxInt32, argLen: 1, asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "CMPWconst", auxType: auxInt16, argLen: 1, asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "CMPBconst", auxType: auxInt8, argLen: 1, asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "UCOMISS", argLen: 2, asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "UCOMISD", argLen: 2, asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "TESTQ", argLen: 2, asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "TESTL", argLen: 2, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "TESTW", argLen: 2, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "TESTB", argLen: 2, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "TESTQconst", auxType: auxInt64, argLen: 1, asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "TESTLconst", auxType: auxInt32, argLen: 1, asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "TESTWconst", auxType: auxInt16, argLen: 1, asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "TESTBconst", auxType: auxInt8, argLen: 1, asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 8589934592, // FLAGS }, }, }, { name: "SHLQ", argLen: 2, resultInArg0: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHLL", argLen: 2, resultInArg0: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHLQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRQ", argLen: 2, resultInArg0: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRL", argLen: 2, resultInArg0: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRW", argLen: 2, resultInArg0: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRB", argLen: 2, resultInArg0: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SHRBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARQ", argLen: 2, resultInArg0: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARL", argLen: 2, resultInArg0: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARW", argLen: 2, resultInArg0: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARB", argLen: 2, resultInArg0: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // CX {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SARBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ROLQconst", auxType: auxInt64, argLen: 1, resultInArg0: true, asm: x86.AROLQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ROLLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ROLWconst", auxType: auxInt16, argLen: 1, resultInArg0: true, asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "ROLBconst", auxType: auxInt8, argLen: 1, resultInArg0: true, asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "NEGQ", argLen: 1, resultInArg0: true, asm: x86.ANEGQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "NEGL", argLen: 1, resultInArg0: true, asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "NOTQ", argLen: 1, resultInArg0: true, asm: x86.ANOTQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "NOTL", argLen: 1, resultInArg0: true, asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSFQ", argLen: 1, asm: x86.ABSFQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSFL", argLen: 1, asm: x86.ABSFL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSFW", argLen: 1, asm: x86.ABSFW, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSRQ", argLen: 1, asm: x86.ABSRQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSRL", argLen: 1, asm: x86.ABSRL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSRW", argLen: 1, asm: x86.ABSRW, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMOVQEQconst", auxType: auxInt64, argLen: 2, resultInArg0: true, asm: x86.ACMOVQEQ, reg: regInfo{ inputs: []inputInfo{ {1, 8589934592}, // FLAGS {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMOVLEQconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: x86.ACMOVLEQ, reg: regInfo{ inputs: []inputInfo{ {1, 8589934592}, // FLAGS {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMOVWEQconst", auxType: auxInt16, argLen: 2, resultInArg0: true, asm: x86.ACMOVLEQ, reg: regInfo{ inputs: []inputInfo{ {1, 8589934592}, // FLAGS {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMOVQNEconst", auxType: auxInt64, argLen: 2, resultInArg0: true, asm: x86.ACMOVQNE, reg: regInfo{ inputs: []inputInfo{ {1, 8589934592}, // FLAGS {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMOVLNEconst", auxType: auxInt32, argLen: 2, resultInArg0: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {1, 8589934592}, // FLAGS {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CMOVWNEconst", auxType: auxInt16, argLen: 2, resultInArg0: true, asm: x86.ACMOVLNE, reg: regInfo{ inputs: []inputInfo{ {1, 8589934592}, // FLAGS {0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSWAPQ", argLen: 1, resultInArg0: true, asm: x86.ABSWAPQ, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "BSWAPL", argLen: 1, resultInArg0: true, asm: x86.ABSWAPL, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SQRTSD", argLen: 1, asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "SBBQcarrymask", argLen: 1, asm: x86.ASBBQ, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SBBLcarrymask", argLen: 1, asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETEQ", argLen: 1, asm: x86.ASETEQ, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETNE", argLen: 1, asm: x86.ASETNE, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETL", argLen: 1, asm: x86.ASETLT, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETLE", argLen: 1, asm: x86.ASETLE, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETG", argLen: 1, asm: x86.ASETGT, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETGE", argLen: 1, asm: x86.ASETGE, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETB", argLen: 1, asm: x86.ASETCS, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETBE", argLen: 1, asm: x86.ASETLS, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETA", argLen: 1, asm: x86.ASETHI, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETAE", argLen: 1, asm: x86.ASETCC, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETEQF", argLen: 1, asm: x86.ASETEQ, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETNEF", argLen: 1, asm: x86.ASETNE, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, clobbers: 8589934593, // AX FLAGS outputs: []regMask{ 65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETORD", argLen: 1, asm: x86.ASETPC, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETNAN", argLen: 1, asm: x86.ASETPS, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETGF", argLen: 1, asm: x86.ASETHI, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "SETGEF", argLen: 1, asm: x86.ASETCC, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // FLAGS }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVBQSX", argLen: 1, asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVBQZX", argLen: 1, asm: x86.AMOVBQZX, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVWQSX", argLen: 1, asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVWQZX", argLen: 1, asm: x86.AMOVWQZX, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLQSX", argLen: 1, asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLQZX", argLen: 1, asm: x86.AMOVLQZX, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: x86.AMOVL, reg: regInfo{ outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVQconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: x86.AMOVQ, reg: regInfo{ outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CVTTSD2SL", argLen: 1, asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CVTTSD2SQ", argLen: 1, asm: x86.ACVTTSD2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CVTTSS2SL", argLen: 1, asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CVTTSS2SQ", argLen: 1, asm: x86.ACVTTSS2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "CVTSL2SS", argLen: 1, asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "CVTSL2SD", argLen: 1, asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "CVTSQ2SS", argLen: 1, asm: x86.ACVTSQ2SS, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "CVTSQ2SD", argLen: 1, asm: x86.ACVTSQ2SD, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "CVTSD2SS", argLen: 1, asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "CVTSS2SD", argLen: 1, asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "PXOR", argLen: 2, commutative: true, resultInArg0: true, asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "LEAQ", auxType: auxSymOff, argLen: 1, rematerializeable: true, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LEAQ1", auxType: auxSymOff, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LEAQ2", auxType: auxSymOff, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LEAQ4", auxType: auxSymOff, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LEAQ8", auxType: auxSymOff, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVBQSXload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVWQSXload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLQSXload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVQload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVLstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVQstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVOload", auxType: auxSymOff, argLen: 2, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "MOVOstore", auxType: auxSymOff, argLen: 3, asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVBloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVWloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVWloadidx2", auxType: auxSymOff, argLen: 3, asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVLloadidx4", auxType: auxSymOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVQloadidx1", auxType: auxSymOff, argLen: 3, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVQloadidx8", auxType: auxSymOff, argLen: 3, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "MOVBstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVWstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVWstoreidx2", auxType: auxSymOff, argLen: 4, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVLstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVLstoreidx4", auxType: auxSymOff, argLen: 4, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVQstoreidx1", auxType: auxSymOff, argLen: 4, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVQstoreidx8", auxType: auxSymOff, argLen: 4, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVLstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVQstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVBstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVWstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVWstoreconstidx2", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVLstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVLstoreconstidx4", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVQstoreconstidx1", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "MOVQstoreconstidx8", auxType: auxSymValAndOff, argLen: 3, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 3, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 65536}, // X0 }, clobbers: 8589934720, // DI FLAGS }, }, { name: "MOVOconst", auxType: auxInt128, argLen: 0, rematerializeable: true, reg: regInfo{ outputs: []regMask{ 4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 }, }, }, { name: "REPSTOSQ", argLen: 4, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 2}, // CX {2, 1}, // AX }, clobbers: 130, // CX DI }, }, { name: "CALLstatic", auxType: auxSymOff, argLen: 1, reg: regInfo{ clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS }, }, { name: "CALLclosure", auxType: auxInt64, argLen: 3, reg: regInfo{ inputs: []inputInfo{ {1, 4}, // DX {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS }, }, { name: "CALLdefer", auxType: auxInt64, argLen: 1, reg: regInfo{ clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS }, }, { name: "CALLgo", auxType: auxInt64, argLen: 1, reg: regInfo{ clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS }, }, { name: "CALLinter", auxType: auxInt64, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI }, clobbers: 8590000320, // SI DI X0 FLAGS }, }, { name: "REPMOVSQ", argLen: 4, reg: regInfo{ inputs: []inputInfo{ {0, 128}, // DI {1, 64}, // SI {2, 2}, // CX }, clobbers: 194, // CX SI DI }, }, { name: "InvertFlags", argLen: 1, reg: regInfo{}, }, { name: "LoweredGetG", argLen: 1, reg: regInfo{ outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []regMask{ 4, // DX }, }, }, { name: "LoweredNilCheck", argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, clobbers: 8589934592, // FLAGS }, }, { name: "MOVQconvert", argLen: 2, asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, outputs: []regMask{ 65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 }, }, }, { name: "FlagEQ", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_ULT", argLen: 0, reg: regInfo{}, }, { name: "FlagLT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_UGT", argLen: 0, reg: regInfo{}, }, { name: "FlagGT_ULT", argLen: 0, reg: regInfo{}, }, { name: "ADD", argLen: 2, commutative: true, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDconst", auxType: auxInt32, argLen: 1, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 14335}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUB", argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBconst", auxType: auxInt32, argLen: 1, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSB", argLen: 2, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "RSBconst", auxType: auxInt32, argLen: 1, asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MUL", argLen: 2, commutative: true, asm: arm.AMUL, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "HMUL", argLen: 2, commutative: true, asm: arm.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "HMULU", argLen: 2, commutative: true, asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "DIV", argLen: 2, asm: arm.ADIV, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, clobbers: 4294967296, // FLAGS outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "DIVU", argLen: 2, asm: arm.ADIVU, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, clobbers: 4294967296, // FLAGS outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOD", argLen: 2, asm: arm.AMOD, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, clobbers: 4294967296, // FLAGS outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MODU", argLen: 2, asm: arm.AMODU, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, clobbers: 4294967296, // FLAGS outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDS", argLen: 2, commutative: true, asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, clobbers: 4294967296, // FLAGS outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADC", argLen: 3, commutative: true, asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ {2, 4294967296}, // FLAGS {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SUBS", argLen: 2, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, clobbers: 4294967296, // FLAGS outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SBC", argLen: 3, asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ {2, 4294967296}, // FLAGS {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MULLU", argLen: 2, commutative: true, asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, clobbers: 1, // R0 outputs: []regMask{ 5118, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MULA", argLen: 3, asm: arm.AMULA, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ADDF", argLen: 2, commutative: true, asm: arm.AADDF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "ADDD", argLen: 2, commutative: true, asm: arm.AADDD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SUBF", argLen: 2, asm: arm.ASUBF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SUBD", argLen: 2, asm: arm.ASUBD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULF", argLen: 2, commutative: true, asm: arm.AMULF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MULD", argLen: 2, commutative: true, asm: arm.AMULD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "DIVF", argLen: 2, asm: arm.ADIVF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "DIVD", argLen: 2, asm: arm.ADIVD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ANDconst", auxType: auxInt32, argLen: 1, asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "ORconst", auxType: auxInt32, argLen: 1, asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "XORconst", auxType: auxInt32, argLen: 1, asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "BIC", argLen: 2, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "BICconst", auxType: auxInt32, argLen: 1, asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MVN", argLen: 1, asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SQRTD", argLen: 1, asm: arm.ASQRTD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SLL", argLen: 2, asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, clobbers: 4294967296, // FLAGS outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SLLconst", auxType: auxInt32, argLen: 1, asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SRL", argLen: 2, asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, clobbers: 4294967296, // FLAGS outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SRLconst", auxType: auxInt32, argLen: 1, asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SRA", argLen: 2, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, clobbers: 4294967296, // FLAGS outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SRAconst", auxType: auxInt32, argLen: 1, asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "SRRconst", auxType: auxInt32, argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "CMP", argLen: 2, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 4294967296, // FLAGS }, }, }, { name: "CMPconst", auxType: auxInt32, argLen: 1, asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 4294967296, // FLAGS }, }, }, { name: "CMN", argLen: 2, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 4294967296, // FLAGS }, }, }, { name: "CMNconst", auxType: auxInt32, argLen: 1, asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 4294967296, // FLAGS }, }, }, { name: "TST", argLen: 2, commutative: true, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 4294967296, // FLAGS }, }, }, { name: "TSTconst", auxType: auxInt32, argLen: 1, asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 4294967296, // FLAGS }, }, }, { name: "TEQ", argLen: 2, commutative: true, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 4294967296, // FLAGS }, }, }, { name: "TEQconst", auxType: auxInt32, argLen: 1, asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 4294967296, // FLAGS }, }, }, { name: "CMPF", argLen: 2, asm: arm.ACMPF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 4294967296, // FLAGS }, }, }, { name: "CMPD", argLen: 2, asm: arm.ACMPD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 4294967296, // FLAGS }, }, }, { name: "MOVWconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: arm.AMOVW, reg: regInfo{ outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVFconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm.AMOVF, reg: regInfo{ outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: arm.AMOVD, reg: regInfo{ outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWaddr", auxType: auxSymOff, argLen: 1, rematerializeable: true, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 8589942784}, // SP SB }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVBload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVBUload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVHload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVHUload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVWload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVFload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDload", auxType: auxSymOff, argLen: 2, asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB }, }, }, { name: "MOVFstore", auxType: auxSymOff, argLen: 3, asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVBreg", argLen: 1, asm: arm.AMOVBS, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVBUreg", argLen: 1, asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVHreg", argLen: 1, asm: arm.AMOVHS, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVHUreg", argLen: 1, asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVWF", argLen: 1, asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWD", argLen: 1, asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWUF", argLen: 1, asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVWUD", argLen: 1, asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVFW", argLen: 1, asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVDW", argLen: 1, asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVFWU", argLen: 1, asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVDWU", argLen: 1, asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "MOVFD", argLen: 1, asm: arm.AMOVFD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "MOVDF", argLen: 1, asm: arm.AMOVDF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []regMask{ 4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "CALLstatic", auxType: auxSymOff, argLen: 1, reg: regInfo{ clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS }, }, { name: "CALLclosure", auxType: auxInt64, argLen: 3, reg: regInfo{ inputs: []inputInfo{ {1, 128}, // R7 {0, 13311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP }, clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS }, }, { name: "CALLdefer", auxType: auxInt64, argLen: 1, reg: regInfo{ clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS }, }, { name: "CALLgo", auxType: auxInt64, argLen: 1, reg: regInfo{ clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS }, }, { name: "CALLinter", auxType: auxInt64, argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS }, }, { name: "LoweredNilCheck", argLen: 2, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, }, }, { name: "Equal", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 4294967296}, // FLAGS }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 4294967296}, // FLAGS }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 4294967296}, // FLAGS }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 4294967296}, // FLAGS }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 4294967296}, // FLAGS }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 4294967296}, // FLAGS }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "LessThanU", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 4294967296}, // FLAGS }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "LessEqualU", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 4294967296}, // FLAGS }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "GreaterThanU", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 4294967296}, // FLAGS }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "GreaterEqualU", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 4294967296}, // FLAGS }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "Carry", argLen: 1, reg: regInfo{ outputs: []regMask{ 4294967296, // FLAGS }, }, }, { name: "LoweredSelect0", argLen: 1, reg: regInfo{ outputs: []regMask{ 1, // R0 }, }, }, { name: "LoweredSelect1", argLen: 1, resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ {0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "LoweredZeromask", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "DUFFZERO", auxType: auxInt64, argLen: 3, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 1}, // R0 }, clobbers: 2, // R1 }, }, { name: "DUFFCOPY", auxType: auxInt64, argLen: 3, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 }, clobbers: 7, // R0 R1 R2 }, }, { name: "LoweredZero", argLen: 4, reg: regInfo{ inputs: []inputInfo{ {0, 2}, // R1 {1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, clobbers: 4294967298, // R1 FLAGS }, }, { name: "LoweredMove", argLen: 4, reg: regInfo{ inputs: []inputInfo{ {0, 4}, // R2 {1, 2}, // R1 {2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, clobbers: 4294967302, // R1 R2 FLAGS }, }, { name: "LoweredGetClosurePtr", argLen: 0, reg: regInfo{ outputs: []regMask{ 128, // R7 }, }, }, { name: "MOVWconvert", argLen: 2, asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 }, outputs: []regMask{ 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 }, }, }, { name: "Add8", argLen: 2, commutative: true, generic: true, }, { name: "Add16", argLen: 2, commutative: true, generic: true, }, { name: "Add32", argLen: 2, commutative: true, generic: true, }, { name: "Add64", argLen: 2, commutative: true, generic: true, }, { name: "AddPtr", argLen: 2, generic: true, }, { name: "Add32F", argLen: 2, generic: true, }, { name: "Add64F", argLen: 2, generic: true, }, { name: "Sub8", argLen: 2, generic: true, }, { name: "Sub16", argLen: 2, generic: true, }, { name: "Sub32", argLen: 2, generic: true, }, { name: "Sub64", argLen: 2, generic: true, }, { name: "SubPtr", argLen: 2, generic: true, }, { name: "Sub32F", argLen: 2, generic: true, }, { name: "Sub64F", argLen: 2, generic: true, }, { name: "Mul8", argLen: 2, commutative: true, generic: true, }, { name: "Mul16", argLen: 2, commutative: true, generic: true, }, { name: "Mul32", argLen: 2, commutative: true, generic: true, }, { name: "Mul64", argLen: 2, commutative: true, generic: true, }, { name: "Mul32F", argLen: 2, generic: true, }, { name: "Mul64F", argLen: 2, generic: true, }, { name: "Div32F", argLen: 2, generic: true, }, { name: "Div64F", argLen: 2, generic: true, }, { name: "Hmul8", argLen: 2, generic: true, }, { name: "Hmul8u", argLen: 2, generic: true, }, { name: "Hmul16", argLen: 2, generic: true, }, { name: "Hmul16u", argLen: 2, generic: true, }, { name: "Hmul32", argLen: 2, generic: true, }, { name: "Hmul32u", argLen: 2, generic: true, }, { name: "Hmul64", argLen: 2, generic: true, }, { name: "Hmul64u", argLen: 2, generic: true, }, { name: "Avg64u", argLen: 2, generic: true, }, { name: "Div8", argLen: 2, generic: true, }, { name: "Div8u", argLen: 2, generic: true, }, { name: "Div16", argLen: 2, generic: true, }, { name: "Div16u", argLen: 2, generic: true, }, { name: "Div32", argLen: 2, generic: true, }, { name: "Div32u", argLen: 2, generic: true, }, { name: "Div64", argLen: 2, generic: true, }, { name: "Div64u", argLen: 2, generic: true, }, { name: "Mod8", argLen: 2, generic: true, }, { name: "Mod8u", argLen: 2, generic: true, }, { name: "Mod16", argLen: 2, generic: true, }, { name: "Mod16u", argLen: 2, generic: true, }, { name: "Mod32", argLen: 2, generic: true, }, { name: "Mod32u", argLen: 2, generic: true, }, { name: "Mod64", argLen: 2, generic: true, }, { name: "Mod64u", argLen: 2, generic: true, }, { name: "And8", argLen: 2, commutative: true, generic: true, }, { name: "And16", argLen: 2, commutative: true, generic: true, }, { name: "And32", argLen: 2, commutative: true, generic: true, }, { name: "And64", argLen: 2, commutative: true, generic: true, }, { name: "Or8", argLen: 2, commutative: true, generic: true, }, { name: "Or16", argLen: 2, commutative: true, generic: true, }, { name: "Or32", argLen: 2, commutative: true, generic: true, }, { name: "Or64", argLen: 2, commutative: true, generic: true, }, { name: "Xor8", argLen: 2, commutative: true, generic: true, }, { name: "Xor16", argLen: 2, commutative: true, generic: true, }, { name: "Xor32", argLen: 2, commutative: true, generic: true, }, { name: "Xor64", argLen: 2, commutative: true, generic: true, }, { name: "Lsh8x8", argLen: 2, generic: true, }, { name: "Lsh8x16", argLen: 2, generic: true, }, { name: "Lsh8x32", argLen: 2, generic: true, }, { name: "Lsh8x64", argLen: 2, generic: true, }, { name: "Lsh16x8", argLen: 2, generic: true, }, { name: "Lsh16x16", argLen: 2, generic: true, }, { name: "Lsh16x32", argLen: 2, generic: true, }, { name: "Lsh16x64", argLen: 2, generic: true, }, { name: "Lsh32x8", argLen: 2, generic: true, }, { name: "Lsh32x16", argLen: 2, generic: true, }, { name: "Lsh32x32", argLen: 2, generic: true, }, { name: "Lsh32x64", argLen: 2, generic: true, }, { name: "Lsh64x8", argLen: 2, generic: true, }, { name: "Lsh64x16", argLen: 2, generic: true, }, { name: "Lsh64x32", argLen: 2, generic: true, }, { name: "Lsh64x64", argLen: 2, generic: true, }, { name: "Rsh8x8", argLen: 2, generic: true, }, { name: "Rsh8x16", argLen: 2, generic: true, }, { name: "Rsh8x32", argLen: 2, generic: true, }, { name: "Rsh8x64", argLen: 2, generic: true, }, { name: "Rsh16x8", argLen: 2, generic: true, }, { name: "Rsh16x16", argLen: 2, generic: true, }, { name: "Rsh16x32", argLen: 2, generic: true, }, { name: "Rsh16x64", argLen: 2, generic: true, }, { name: "Rsh32x8", argLen: 2, generic: true, }, { name: "Rsh32x16", argLen: 2, generic: true, }, { name: "Rsh32x32", argLen: 2, generic: true, }, { name: "Rsh32x64", argLen: 2, generic: true, }, { name: "Rsh64x8", argLen: 2, generic: true, }, { name: "Rsh64x16", argLen: 2, generic: true, }, { name: "Rsh64x32", argLen: 2, generic: true, }, { name: "Rsh64x64", argLen: 2, generic: true, }, { name: "Rsh8Ux8", argLen: 2, generic: true, }, { name: "Rsh8Ux16", argLen: 2, generic: true, }, { name: "Rsh8Ux32", argLen: 2, generic: true, }, { name: "Rsh8Ux64", argLen: 2, generic: true, }, { name: "Rsh16Ux8", argLen: 2, generic: true, }, { name: "Rsh16Ux16", argLen: 2, generic: true, }, { name: "Rsh16Ux32", argLen: 2, generic: true, }, { name: "Rsh16Ux64", argLen: 2, generic: true, }, { name: "Rsh32Ux8", argLen: 2, generic: true, }, { name: "Rsh32Ux16", argLen: 2, generic: true, }, { name: "Rsh32Ux32", argLen: 2, generic: true, }, { name: "Rsh32Ux64", argLen: 2, generic: true, }, { name: "Rsh64Ux8", argLen: 2, generic: true, }, { name: "Rsh64Ux16", argLen: 2, generic: true, }, { name: "Rsh64Ux32", argLen: 2, generic: true, }, { name: "Rsh64Ux64", argLen: 2, generic: true, }, { name: "Lrot8", auxType: auxInt64, argLen: 1, generic: true, }, { name: "Lrot16", auxType: auxInt64, argLen: 1, generic: true, }, { name: "Lrot32", auxType: auxInt64, argLen: 1, generic: true, }, { name: "Lrot64", auxType: auxInt64, argLen: 1, generic: true, }, { name: "Eq8", argLen: 2, commutative: true, generic: true, }, { name: "Eq16", argLen: 2, commutative: true, generic: true, }, { name: "Eq32", argLen: 2, commutative: true, generic: true, }, { name: "Eq64", argLen: 2, commutative: true, generic: true, }, { name: "EqPtr", argLen: 2, commutative: true, generic: true, }, { name: "EqInter", argLen: 2, generic: true, }, { name: "EqSlice", argLen: 2, generic: true, }, { name: "Eq32F", argLen: 2, generic: true, }, { name: "Eq64F", argLen: 2, generic: true, }, { name: "Neq8", argLen: 2, commutative: true, generic: true, }, { name: "Neq16", argLen: 2, commutative: true, generic: true, }, { name: "Neq32", argLen: 2, commutative: true, generic: true, }, { name: "Neq64", argLen: 2, commutative: true, generic: true, }, { name: "NeqPtr", argLen: 2, commutative: true, generic: true, }, { name: "NeqInter", argLen: 2, generic: true, }, { name: "NeqSlice", argLen: 2, generic: true, }, { name: "Neq32F", argLen: 2, generic: true, }, { name: "Neq64F", argLen: 2, generic: true, }, { name: "Less8", argLen: 2, generic: true, }, { name: "Less8U", argLen: 2, generic: true, }, { name: "Less16", argLen: 2, generic: true, }, { name: "Less16U", argLen: 2, generic: true, }, { name: "Less32", argLen: 2, generic: true, }, { name: "Less32U", argLen: 2, generic: true, }, { name: "Less64", argLen: 2, generic: true, }, { name: "Less64U", argLen: 2, generic: true, }, { name: "Less32F", argLen: 2, generic: true, }, { name: "Less64F", argLen: 2, generic: true, }, { name: "Leq8", argLen: 2, generic: true, }, { name: "Leq8U", argLen: 2, generic: true, }, { name: "Leq16", argLen: 2, generic: true, }, { name: "Leq16U", argLen: 2, generic: true, }, { name: "Leq32", argLen: 2, generic: true, }, { name: "Leq32U", argLen: 2, generic: true, }, { name: "Leq64", argLen: 2, generic: true, }, { name: "Leq64U", argLen: 2, generic: true, }, { name: "Leq32F", argLen: 2, generic: true, }, { name: "Leq64F", argLen: 2, generic: true, }, { name: "Greater8", argLen: 2, generic: true, }, { name: "Greater8U", argLen: 2, generic: true, }, { name: "Greater16", argLen: 2, generic: true, }, { name: "Greater16U", argLen: 2, generic: true, }, { name: "Greater32", argLen: 2, generic: true, }, { name: "Greater32U", argLen: 2, generic: true, }, { name: "Greater64", argLen: 2, generic: true, }, { name: "Greater64U", argLen: 2, generic: true, }, { name: "Greater32F", argLen: 2, generic: true, }, { name: "Greater64F", argLen: 2, generic: true, }, { name: "Geq8", argLen: 2, generic: true, }, { name: "Geq8U", argLen: 2, generic: true, }, { name: "Geq16", argLen: 2, generic: true, }, { name: "Geq16U", argLen: 2, generic: true, }, { name: "Geq32", argLen: 2, generic: true, }, { name: "Geq32U", argLen: 2, generic: true, }, { name: "Geq64", argLen: 2, generic: true, }, { name: "Geq64U", argLen: 2, generic: true, }, { name: "Geq32F", argLen: 2, generic: true, }, { name: "Geq64F", argLen: 2, generic: true, }, { name: "AndB", argLen: 2, generic: true, }, { name: "OrB", argLen: 2, generic: true, }, { name: "EqB", argLen: 2, generic: true, }, { name: "NeqB", argLen: 2, generic: true, }, { name: "Not", argLen: 1, generic: true, }, { name: "Neg8", argLen: 1, generic: true, }, { name: "Neg16", argLen: 1, generic: true, }, { name: "Neg32", argLen: 1, generic: true, }, { name: "Neg64", argLen: 1, generic: true, }, { name: "Neg32F", argLen: 1, generic: true, }, { name: "Neg64F", argLen: 1, generic: true, }, { name: "Com8", argLen: 1, generic: true, }, { name: "Com16", argLen: 1, generic: true, }, { name: "Com32", argLen: 1, generic: true, }, { name: "Com64", argLen: 1, generic: true, }, { name: "Ctz16", argLen: 1, generic: true, }, { name: "Ctz32", argLen: 1, generic: true, }, { name: "Ctz64", argLen: 1, generic: true, }, { name: "Clz16", argLen: 1, generic: true, }, { name: "Clz32", argLen: 1, generic: true, }, { name: "Clz64", argLen: 1, generic: true, }, { name: "Bswap32", argLen: 1, generic: true, }, { name: "Bswap64", argLen: 1, generic: true, }, { name: "Sqrt", argLen: 1, generic: true, }, { name: "Phi", argLen: -1, generic: true, }, { name: "Copy", argLen: 1, generic: true, }, { name: "Convert", argLen: 2, generic: true, }, { name: "ConstBool", auxType: auxBool, argLen: 0, generic: true, }, { name: "ConstString", auxType: auxString, argLen: 0, generic: true, }, { name: "ConstNil", argLen: 0, generic: true, }, { name: "Const8", auxType: auxInt8, argLen: 0, generic: true, }, { name: "Const16", auxType: auxInt16, argLen: 0, generic: true, }, { name: "Const32", auxType: auxInt32, argLen: 0, generic: true, }, { name: "Const64", auxType: auxInt64, argLen: 0, generic: true, }, { name: "Const32F", auxType: auxFloat32, argLen: 0, generic: true, }, { name: "Const64F", auxType: auxFloat64, argLen: 0, generic: true, }, { name: "ConstInterface", argLen: 0, generic: true, }, { name: "ConstSlice", argLen: 0, generic: true, }, { name: "InitMem", argLen: 0, generic: true, }, { name: "Arg", auxType: auxSymOff, argLen: 0, generic: true, }, { name: "Addr", auxType: auxSym, argLen: 1, generic: true, }, { name: "SP", argLen: 0, generic: true, }, { name: "SB", argLen: 0, generic: true, }, { name: "Func", auxType: auxSym, argLen: 0, generic: true, }, { name: "Load", argLen: 2, generic: true, }, { name: "Store", auxType: auxInt64, argLen: 3, generic: true, }, { name: "Move", auxType: auxInt64, argLen: 3, generic: true, }, { name: "Zero", auxType: auxInt64, argLen: 2, generic: true, }, { name: "ClosureCall", auxType: auxInt64, argLen: 3, generic: true, }, { name: "StaticCall", auxType: auxSymOff, argLen: 1, generic: true, }, { name: "DeferCall", auxType: auxInt64, argLen: 1, generic: true, }, { name: "GoCall", auxType: auxInt64, argLen: 1, generic: true, }, { name: "InterCall", auxType: auxInt64, argLen: 2, generic: true, }, { name: "SignExt8to16", argLen: 1, generic: true, }, { name: "SignExt8to32", argLen: 1, generic: true, }, { name: "SignExt8to64", argLen: 1, generic: true, }, { name: "SignExt16to32", argLen: 1, generic: true, }, { name: "SignExt16to64", argLen: 1, generic: true, }, { name: "SignExt32to64", argLen: 1, generic: true, }, { name: "ZeroExt8to16", argLen: 1, generic: true, }, { name: "ZeroExt8to32", argLen: 1, generic: true, }, { name: "ZeroExt8to64", argLen: 1, generic: true, }, { name: "ZeroExt16to32", argLen: 1, generic: true, }, { name: "ZeroExt16to64", argLen: 1, generic: true, }, { name: "ZeroExt32to64", argLen: 1, generic: true, }, { name: "Trunc16to8", argLen: 1, generic: true, }, { name: "Trunc32to8", argLen: 1, generic: true, }, { name: "Trunc32to16", argLen: 1, generic: true, }, { name: "Trunc64to8", argLen: 1, generic: true, }, { name: "Trunc64to16", argLen: 1, generic: true, }, { name: "Trunc64to32", argLen: 1, generic: true, }, { name: "Cvt32to32F", argLen: 1, generic: true, }, { name: "Cvt32to64F", argLen: 1, generic: true, }, { name: "Cvt64to32F", argLen: 1, generic: true, }, { name: "Cvt64to64F", argLen: 1, generic: true, }, { name: "Cvt32Fto32", argLen: 1, generic: true, }, { name: "Cvt32Fto64", argLen: 1, generic: true, }, { name: "Cvt64Fto32", argLen: 1, generic: true, }, { name: "Cvt64Fto64", argLen: 1, generic: true, }, { name: "Cvt32Fto64F", argLen: 1, generic: true, }, { name: "Cvt64Fto32F", argLen: 1, generic: true, }, { name: "IsNonNil", argLen: 1, generic: true, }, { name: "IsInBounds", argLen: 2, generic: true, }, { name: "IsSliceInBounds", argLen: 2, generic: true, }, { name: "NilCheck", argLen: 2, generic: true, }, { name: "GetG", argLen: 1, generic: true, }, { name: "GetClosurePtr", argLen: 0, generic: true, }, { name: "ArrayIndex", auxType: auxInt64, argLen: 1, generic: true, }, { name: "PtrIndex", argLen: 2, generic: true, }, { name: "OffPtr", auxType: auxInt64, argLen: 1, generic: true, }, { name: "SliceMake", argLen: 3, generic: true, }, { name: "SlicePtr", argLen: 1, generic: true, }, { name: "SliceLen", argLen: 1, generic: true, }, { name: "SliceCap", argLen: 1, generic: true, }, { name: "ComplexMake", argLen: 2, generic: true, }, { name: "ComplexReal", argLen: 1, generic: true, }, { name: "ComplexImag", argLen: 1, generic: true, }, { name: "StringMake", argLen: 2, generic: true, }, { name: "StringPtr", argLen: 1, generic: true, }, { name: "StringLen", argLen: 1, generic: true, }, { name: "IMake", argLen: 2, generic: true, }, { name: "ITab", argLen: 1, generic: true, }, { name: "IData", argLen: 1, generic: true, }, { name: "StructMake0", argLen: 0, generic: true, }, { name: "StructMake1", argLen: 1, generic: true, }, { name: "StructMake2", argLen: 2, generic: true, }, { name: "StructMake3", argLen: 3, generic: true, }, { name: "StructMake4", argLen: 4, generic: true, }, { name: "StructSelect", auxType: auxInt64, argLen: 1, generic: true, }, { name: "StoreReg", argLen: 1, generic: true, }, { name: "LoadReg", argLen: 1, generic: true, }, { name: "FwdRef", auxType: auxSym, argLen: 0, generic: true, }, { name: "Unknown", argLen: 0, generic: true, }, { name: "VarDef", auxType: auxSym, argLen: 1, generic: true, }, { name: "VarKill", auxType: auxSym, argLen: 1, generic: true, }, { name: "VarLive", auxType: auxSym, argLen: 1, generic: true, }, { name: "KeepAlive", argLen: 2, generic: true, }, { name: "Int64Make", argLen: 2, generic: true, }, { name: "Int64Hi", argLen: 1, generic: true, }, { name: "Int64Lo", argLen: 1, generic: true, }, { name: "Add32carry", argLen: 2, commutative: true, generic: true, }, { name: "Add32withcarry", argLen: 3, commutative: true, generic: true, }, { name: "Sub32carry", argLen: 2, generic: true, }, { name: "Sub32withcarry", argLen: 3, generic: true, }, { name: "Mul32uhilo", argLen: 2, generic: true, }, { name: "Signmask", argLen: 1, generic: true, }, { name: "Zeromask", argLen: 1, generic: true, }, { name: "Cvt32Uto32F", argLen: 1, generic: true, }, { name: "Cvt32Uto64F", argLen: 1, generic: true, }, { name: "Cvt32Fto32U", argLen: 1, generic: true, }, { name: "Cvt64Fto32U", argLen: 1, generic: true, }, { name: "Select0", argLen: 1, generic: true, }, { name: "Select1", argLen: 1, generic: true, }, { name: "ADD", argLen: 2, commutative: true, asm: ppc64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ADDconst", auxType: auxSymOff, argLen: 1, asm: ppc64.AADD, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FADD", argLen: 2, commutative: true, asm: ppc64.AFADD, reg: regInfo{ inputs: []inputInfo{ {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []regMask{ 576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FADDS", argLen: 2, commutative: true, asm: ppc64.AFADDS, reg: regInfo{ inputs: []inputInfo{ {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []regMask{ 576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "SUB", argLen: 2, asm: ppc64.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FSUB", argLen: 2, asm: ppc64.AFSUB, reg: regInfo{ inputs: []inputInfo{ {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []regMask{ 576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FSUBS", argLen: 2, asm: ppc64.AFSUBS, reg: regInfo{ inputs: []inputInfo{ {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []regMask{ 576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "MULLD", argLen: 2, commutative: true, asm: ppc64.AMULLD, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MULLW", argLen: 2, commutative: true, asm: ppc64.AMULLW, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMUL", argLen: 2, commutative: true, asm: ppc64.AFMUL, reg: regInfo{ inputs: []inputInfo{ {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []regMask{ 576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FMULS", argLen: 2, commutative: true, asm: ppc64.AFMULS, reg: regInfo{ inputs: []inputInfo{ {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []regMask{ 576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FDIV", argLen: 2, asm: ppc64.AFDIV, reg: regInfo{ inputs: []inputInfo{ {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []regMask{ 576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FDIVS", argLen: 2, asm: ppc64.AFDIVS, reg: regInfo{ inputs: []inputInfo{ {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []regMask{ 576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "AND", argLen: 2, commutative: true, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ANDconst", auxType: auxInt32, argLen: 1, asm: ppc64.AAND, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "OR", argLen: 2, commutative: true, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "ORconst", auxType: auxInt32, argLen: 1, asm: ppc64.AOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XOR", argLen: 2, commutative: true, asm: ppc64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "XORconst", auxType: auxInt32, argLen: 1, asm: ppc64.AXOR, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NEG", argLen: 1, asm: ppc64.ANEG, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBreg", argLen: 1, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZreg", argLen: 1, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHreg", argLen: 1, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZreg", argLen: 1, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWreg", argLen: 1, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZreg", argLen: 1, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBload", argLen: 2, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBZload", argLen: 2, asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHload", argLen: 2, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHZload", argLen: 2, asm: ppc64.AMOVHZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWload", argLen: 2, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWZload", argLen: 2, asm: ppc64.AMOVWZ, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDload", argLen: 2, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDload", argLen: 2, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FMOVSload", argLen: 2, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "MOVBstore", auxType: auxSymOff, argLen: 3, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstore", auxType: auxSymOff, argLen: 3, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstore", auxType: auxSymOff, argLen: 3, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstore", auxType: auxSymOff, argLen: 3, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDstore", auxType: auxSymOff, argLen: 3, asm: ppc64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVSstore", auxType: auxSymOff, argLen: 3, asm: ppc64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: ppc64.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: ppc64.AMOVH, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: ppc64.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDstoreconst", auxType: auxSymValAndOff, argLen: 2, asm: ppc64.AMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVDconst", auxType: auxInt64, argLen: 0, rematerializeable: true, asm: ppc64.AMOVD, reg: regInfo{ outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVWconst", auxType: auxInt32, argLen: 0, rematerializeable: true, asm: ppc64.AMOVW, reg: regInfo{ outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVHconst", auxType: auxInt16, argLen: 0, rematerializeable: true, asm: ppc64.AMOVH, reg: regInfo{ outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MOVBconst", auxType: auxInt8, argLen: 0, rematerializeable: true, asm: ppc64.AMOVB, reg: regInfo{ outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "FMOVDconst", auxType: auxFloat64, argLen: 0, rematerializeable: true, asm: ppc64.AFMOVD, reg: regInfo{ outputs: []regMask{ 576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FMOVSconst", auxType: auxFloat32, argLen: 0, rematerializeable: true, asm: ppc64.AFMOVS, reg: regInfo{ outputs: []regMask{ 576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, }, { name: "FCMPU", argLen: 2, asm: ppc64.AFCMPU, reg: regInfo{ inputs: []inputInfo{ {0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 {1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, outputs: []regMask{ 576460752303423488, // CR }, }, }, { name: "CMP", argLen: 2, asm: ppc64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 576460752303423488, // CR }, }, }, { name: "CMPU", argLen: 2, asm: ppc64.ACMPU, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 576460752303423488, // CR }, }, }, { name: "CMPW", argLen: 2, asm: ppc64.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 576460752303423488, // CR }, }, }, { name: "CMPWU", argLen: 2, asm: ppc64.ACMPWU, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 {1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 576460752303423488, // CR }, }, }, { name: "CMPconst", auxType: auxInt32, argLen: 1, asm: ppc64.ACMP, reg: regInfo{ inputs: []inputInfo{ {0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, outputs: []regMask{ 576460752303423488, // CR }, }, }, { name: "CALLstatic", auxType: auxSymOff, argLen: 1, reg: regInfo{ clobbers: 576460744787220472, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 }, }, { name: "Equal", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 576460752303423488}, // CR }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "NotEqual", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 576460752303423488}, // CR }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LessThan", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 576460752303423488}, // CR }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "LessEqual", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 576460752303423488}, // CR }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "GreaterThan", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 576460752303423488}, // CR }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "GreaterEqual", argLen: 1, reg: regInfo{ inputs: []inputInfo{ {0, 576460752303423488}, // CR }, outputs: []regMask{ 1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, } func (o Op) Asm() obj.As { return opcodeTable[o].asm } func (o Op) String() string { return opcodeTable[o].name } var registersAMD64 = [...]Register{ {0, "AX"}, {1, "CX"}, {2, "DX"}, {3, "BX"}, {4, "SP"}, {5, "BP"}, {6, "SI"}, {7, "DI"}, {8, "R8"}, {9, "R9"}, {10, "R10"}, {11, "R11"}, {12, "R12"}, {13, "R13"}, {14, "R14"}, {15, "R15"}, {16, "X0"}, {17, "X1"}, {18, "X2"}, {19, "X3"}, {20, "X4"}, {21, "X5"}, {22, "X6"}, {23, "X7"}, {24, "X8"}, {25, "X9"}, {26, "X10"}, {27, "X11"}, {28, "X12"}, {29, "X13"}, {30, "X14"}, {31, "X15"}, {32, "SB"}, {33, "FLAGS"}, } var gpRegMaskAMD64 = regMask(65519) var fpRegMaskAMD64 = regMask(4294901760) var flagRegMaskAMD64 = regMask(8589934592) var framepointerRegAMD64 = int8(5) var registersARM = [...]Register{ {0, "R0"}, {1, "R1"}, {2, "R2"}, {3, "R3"}, {4, "R4"}, {5, "R5"}, {6, "R6"}, {7, "R7"}, {8, "R8"}, {9, "R9"}, {10, "g"}, {11, "R11"}, {12, "R12"}, {13, "SP"}, {14, "R14"}, {15, "R15"}, {16, "F0"}, {17, "F1"}, {18, "F2"}, {19, "F3"}, {20, "F4"}, {21, "F5"}, {22, "F6"}, {23, "F7"}, {24, "F8"}, {25, "F9"}, {26, "F10"}, {27, "F11"}, {28, "F12"}, {29, "F13"}, {30, "F14"}, {31, "F15"}, {32, "FLAGS"}, {33, "SB"}, } var gpRegMaskARM = regMask(5119) var fpRegMaskARM = regMask(4294901760) var flagRegMaskARM = regMask(4294967296) var framepointerRegARM = int8(-1) var registersPPC64 = [...]Register{ {0, "R0"}, {1, "SP"}, {2, "SB"}, {3, "R3"}, {4, "R4"}, {5, "R5"}, {6, "R6"}, {7, "R7"}, {8, "R8"}, {9, "R9"}, {10, "R10"}, {11, "R11"}, {12, "R12"}, {13, "R13"}, {14, "R14"}, {15, "R15"}, {16, "R16"}, {17, "R17"}, {18, "R18"}, {19, "R19"}, {20, "R20"}, {21, "R21"}, {22, "R22"}, {23, "R23"}, {24, "R24"}, {25, "R25"}, {26, "R26"}, {27, "R27"}, {28, "R28"}, {29, "R29"}, {30, "R30"}, {31, "R31"}, {32, "F0"}, {33, "F1"}, {34, "F2"}, {35, "F3"}, {36, "F4"}, {37, "F5"}, {38, "F6"}, {39, "F7"}, {40, "F8"}, {41, "F9"}, {42, "F10"}, {43, "F11"}, {44, "F12"}, {45, "F13"}, {46, "F14"}, {47, "F15"}, {48, "F16"}, {49, "F17"}, {50, "F18"}, {51, "F19"}, {52, "F20"}, {53, "F21"}, {54, "F22"}, {55, "F23"}, {56, "F24"}, {57, "F25"}, {58, "F26"}, {59, "CR"}, } var gpRegMaskPPC64 = regMask(1073731576) var fpRegMaskPPC64 = regMask(576460743713488896) var flagRegMaskPPC64 = regMask(0) var framepointerRegPPC64 = int8(1)