// autogenerated: do not edit! // generated from gen/*Ops.go package ssa import "cmd/internal/obj/x86" const ( BlockInvalid BlockKind = iota BlockAMD64EQ BlockAMD64NE BlockAMD64LT BlockAMD64LE BlockAMD64GT BlockAMD64GE BlockAMD64ULT BlockAMD64ULE BlockAMD64UGT BlockAMD64UGE BlockAMD64EQF BlockAMD64NEF BlockAMD64ORD BlockAMD64NAN BlockPlain BlockIf BlockCall BlockCheck BlockRet BlockRetJmp BlockExit BlockFirst BlockDead ) var blockString = [...]string{ BlockInvalid: "BlockInvalid", BlockAMD64EQ: "EQ", BlockAMD64NE: "NE", BlockAMD64LT: "LT", BlockAMD64LE: "LE", BlockAMD64GT: "GT", BlockAMD64GE: "GE", BlockAMD64ULT: "ULT", BlockAMD64ULE: "ULE", BlockAMD64UGT: "UGT", BlockAMD64UGE: "UGE", BlockAMD64EQF: "EQF", BlockAMD64NEF: "NEF", BlockAMD64ORD: "ORD", BlockAMD64NAN: "NAN", BlockPlain: "Plain", BlockIf: "If", BlockCall: "Call", BlockCheck: "Check", BlockRet: "Ret", BlockRetJmp: "RetJmp", BlockExit: "Exit", BlockFirst: "First", BlockDead: "Dead", } func (k BlockKind) String() string { return blockString[k] } const ( OpInvalid Op = iota OpAMD64ADDSS OpAMD64ADDSD OpAMD64SUBSS OpAMD64SUBSD OpAMD64MULSS OpAMD64MULSD OpAMD64DIVSS OpAMD64DIVSD OpAMD64MOVSSload OpAMD64MOVSDload OpAMD64MOVSSconst OpAMD64MOVSDconst OpAMD64MOVSSloadidx4 OpAMD64MOVSDloadidx8 OpAMD64MOVSSstore OpAMD64MOVSDstore OpAMD64MOVSSstoreidx4 OpAMD64MOVSDstoreidx8 OpAMD64ADDQ OpAMD64ADDL OpAMD64ADDW OpAMD64ADDB OpAMD64ADDQconst OpAMD64ADDLconst OpAMD64ADDWconst OpAMD64ADDBconst OpAMD64SUBQ OpAMD64SUBL OpAMD64SUBW OpAMD64SUBB OpAMD64SUBQconst OpAMD64SUBLconst OpAMD64SUBWconst OpAMD64SUBBconst OpAMD64MULQ OpAMD64MULL OpAMD64MULW OpAMD64MULB OpAMD64MULQconst OpAMD64MULLconst OpAMD64MULWconst OpAMD64MULBconst OpAMD64HMULL OpAMD64HMULW OpAMD64HMULB OpAMD64HMULLU OpAMD64HMULWU OpAMD64HMULBU OpAMD64DIVQ OpAMD64DIVL OpAMD64DIVW OpAMD64DIVQU OpAMD64DIVLU OpAMD64DIVWU OpAMD64MODQ OpAMD64MODL OpAMD64MODW OpAMD64MODQU OpAMD64MODLU OpAMD64MODWU OpAMD64ANDQ OpAMD64ANDL OpAMD64ANDW OpAMD64ANDB OpAMD64ANDQconst OpAMD64ANDLconst OpAMD64ANDWconst OpAMD64ANDBconst OpAMD64ORQ OpAMD64ORL OpAMD64ORW OpAMD64ORB OpAMD64ORQconst OpAMD64ORLconst OpAMD64ORWconst OpAMD64ORBconst OpAMD64XORQ OpAMD64XORL OpAMD64XORW OpAMD64XORB OpAMD64XORQconst OpAMD64XORLconst OpAMD64XORWconst OpAMD64XORBconst OpAMD64CMPQ OpAMD64CMPL OpAMD64CMPW OpAMD64CMPB OpAMD64CMPQconst OpAMD64CMPLconst OpAMD64CMPWconst OpAMD64CMPBconst OpAMD64UCOMISS OpAMD64UCOMISD OpAMD64TESTQ OpAMD64TESTL OpAMD64TESTW OpAMD64TESTB OpAMD64TESTQconst OpAMD64TESTLconst OpAMD64TESTWconst OpAMD64TESTBconst OpAMD64SHLQ OpAMD64SHLL OpAMD64SHLW OpAMD64SHLB OpAMD64SHLQconst OpAMD64SHLLconst OpAMD64SHLWconst OpAMD64SHLBconst OpAMD64SHRQ OpAMD64SHRL OpAMD64SHRW OpAMD64SHRB OpAMD64SHRQconst OpAMD64SHRLconst OpAMD64SHRWconst OpAMD64SHRBconst OpAMD64SARQ OpAMD64SARL OpAMD64SARW OpAMD64SARB OpAMD64SARQconst OpAMD64SARLconst OpAMD64SARWconst OpAMD64SARBconst OpAMD64ROLQconst OpAMD64ROLLconst OpAMD64ROLWconst OpAMD64ROLBconst OpAMD64NEGQ OpAMD64NEGL OpAMD64NEGW OpAMD64NEGB OpAMD64NOTQ OpAMD64NOTL OpAMD64NOTW OpAMD64NOTB OpAMD64SQRTSD OpAMD64SBBQcarrymask OpAMD64SBBLcarrymask OpAMD64SETEQ OpAMD64SETNE OpAMD64SETL OpAMD64SETLE OpAMD64SETG OpAMD64SETGE OpAMD64SETB OpAMD64SETBE OpAMD64SETA OpAMD64SETAE OpAMD64SETEQF OpAMD64SETNEF OpAMD64SETORD OpAMD64SETNAN OpAMD64SETGF OpAMD64SETGEF OpAMD64MOVBQSX OpAMD64MOVBQZX OpAMD64MOVWQSX OpAMD64MOVWQZX OpAMD64MOVLQSX OpAMD64MOVLQZX OpAMD64MOVBconst OpAMD64MOVWconst OpAMD64MOVLconst OpAMD64MOVQconst OpAMD64CVTTSD2SL OpAMD64CVTTSD2SQ OpAMD64CVTTSS2SL OpAMD64CVTTSS2SQ OpAMD64CVTSL2SS OpAMD64CVTSL2SD OpAMD64CVTSQ2SS OpAMD64CVTSQ2SD OpAMD64CVTSD2SS OpAMD64CVTSS2SD OpAMD64PXOR OpAMD64LEAQ OpAMD64LEAQ1 OpAMD64LEAQ2 OpAMD64LEAQ4 OpAMD64LEAQ8 OpAMD64MOVBload OpAMD64MOVBQSXload OpAMD64MOVBQZXload OpAMD64MOVWload OpAMD64MOVLload OpAMD64MOVQload OpAMD64MOVQloadidx8 OpAMD64MOVBstore OpAMD64MOVWstore OpAMD64MOVLstore OpAMD64MOVQstore OpAMD64MOVQstoreidx8 OpAMD64MOVOload OpAMD64MOVOstore OpAMD64MOVBstoreconst OpAMD64MOVWstoreconst OpAMD64MOVLstoreconst OpAMD64MOVQstoreconst OpAMD64DUFFZERO OpAMD64MOVOconst OpAMD64REPSTOSQ OpAMD64CALLstatic OpAMD64CALLclosure OpAMD64CALLdefer OpAMD64CALLgo OpAMD64CALLinter OpAMD64DUFFCOPY OpAMD64REPMOVSQ OpAMD64InvertFlags OpAMD64LoweredGetG OpAMD64LoweredGetClosurePtr OpAMD64LoweredNilCheck OpAdd8 OpAdd16 OpAdd32 OpAdd64 OpAddPtr OpAdd32F OpAdd64F OpSub8 OpSub16 OpSub32 OpSub64 OpSubPtr OpSub32F OpSub64F OpMul8 OpMul16 OpMul32 OpMul64 OpMul32F OpMul64F OpDiv32F OpDiv64F OpHmul8 OpHmul8u OpHmul16 OpHmul16u OpHmul32 OpHmul32u OpDiv8 OpDiv8u OpDiv16 OpDiv16u OpDiv32 OpDiv32u OpDiv64 OpDiv64u OpMod8 OpMod8u OpMod16 OpMod16u OpMod32 OpMod32u OpMod64 OpMod64u OpAnd8 OpAnd16 OpAnd32 OpAnd64 OpOr8 OpOr16 OpOr32 OpOr64 OpXor8 OpXor16 OpXor32 OpXor64 OpLsh8x8 OpLsh8x16 OpLsh8x32 OpLsh8x64 OpLsh16x8 OpLsh16x16 OpLsh16x32 OpLsh16x64 OpLsh32x8 OpLsh32x16 OpLsh32x32 OpLsh32x64 OpLsh64x8 OpLsh64x16 OpLsh64x32 OpLsh64x64 OpRsh8x8 OpRsh8x16 OpRsh8x32 OpRsh8x64 OpRsh16x8 OpRsh16x16 OpRsh16x32 OpRsh16x64 OpRsh32x8 OpRsh32x16 OpRsh32x32 OpRsh32x64 OpRsh64x8 OpRsh64x16 OpRsh64x32 OpRsh64x64 OpRsh8Ux8 OpRsh8Ux16 OpRsh8Ux32 OpRsh8Ux64 OpRsh16Ux8 OpRsh16Ux16 OpRsh16Ux32 OpRsh16Ux64 OpRsh32Ux8 OpRsh32Ux16 OpRsh32Ux32 OpRsh32Ux64 OpRsh64Ux8 OpRsh64Ux16 OpRsh64Ux32 OpRsh64Ux64 OpLrot8 OpLrot16 OpLrot32 OpLrot64 OpEq8 OpEq16 OpEq32 OpEq64 OpEqPtr OpEqInter OpEqSlice OpEq32F OpEq64F OpNeq8 OpNeq16 OpNeq32 OpNeq64 OpNeqPtr OpNeqInter OpNeqSlice OpNeq32F OpNeq64F OpLess8 OpLess8U OpLess16 OpLess16U OpLess32 OpLess32U OpLess64 OpLess64U OpLess32F OpLess64F OpLeq8 OpLeq8U OpLeq16 OpLeq16U OpLeq32 OpLeq32U OpLeq64 OpLeq64U OpLeq32F OpLeq64F OpGreater8 OpGreater8U OpGreater16 OpGreater16U OpGreater32 OpGreater32U OpGreater64 OpGreater64U OpGreater32F OpGreater64F OpGeq8 OpGeq8U OpGeq16 OpGeq16U OpGeq32 OpGeq32U OpGeq64 OpGeq64U OpGeq32F OpGeq64F OpNot OpNeg8 OpNeg16 OpNeg32 OpNeg64 OpNeg32F OpNeg64F OpCom8 OpCom16 OpCom32 OpCom64 OpSqrt OpPhi OpCopy OpConvert OpConstBool OpConstString OpConstNil OpConst8 OpConst16 OpConst32 OpConst64 OpConst32F OpConst64F OpConstInterface OpConstSlice OpArg OpAddr OpSP OpSB OpFunc OpLoad OpStore OpMove OpZero OpClosureCall OpStaticCall OpDeferCall OpGoCall OpInterCall OpSignExt8to16 OpSignExt8to32 OpSignExt8to64 OpSignExt16to32 OpSignExt16to64 OpSignExt32to64 OpZeroExt8to16 OpZeroExt8to32 OpZeroExt8to64 OpZeroExt16to32 OpZeroExt16to64 OpZeroExt32to64 OpTrunc16to8 OpTrunc32to8 OpTrunc32to16 OpTrunc64to8 OpTrunc64to16 OpTrunc64to32 OpCvt32to32F OpCvt32to64F OpCvt64to32F OpCvt64to64F OpCvt32Fto32 OpCvt32Fto64 OpCvt64Fto32 OpCvt64Fto64 OpCvt32Fto64F OpCvt64Fto32F OpIsNonNil OpIsInBounds OpIsSliceInBounds OpNilCheck OpGetG OpGetClosurePtr OpArrayIndex OpPtrIndex OpOffPtr OpStructSelect OpSliceMake OpSlicePtr OpSliceLen OpSliceCap OpComplexMake OpComplexReal OpComplexImag OpStringMake OpStringPtr OpStringLen OpIMake OpITab OpIData OpStoreReg OpLoadReg OpFwdRef OpVarDef OpVarKill ) var opcodeTable = [...]opInfo{ {name: "OpInvalid"}, { name: "ADDSS", asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "ADDSD", asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "SUBSS", asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 {1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 }, clobbers: 2147483648, // .X15 outputs: []regMask{ 2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 }, }, }, { name: "SUBSD", asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 {1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 }, clobbers: 2147483648, // .X15 outputs: []regMask{ 2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 }, }, }, { name: "MULSS", asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "MULSD", asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "DIVSS", asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 {1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 }, clobbers: 2147483648, // .X15 outputs: []regMask{ 2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 }, }, }, { name: "DIVSD", asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ {0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 {1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 }, clobbers: 2147483648, // .X15 outputs: []regMask{ 2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 }, }, }, { name: "MOVSSload", asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "MOVSDload", asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "MOVSSconst", asm: x86.AMOVSS, reg: regInfo{ outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "MOVSDconst", asm: x86.AMOVSD, reg: regInfo{ outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "MOVSSloadidx4", asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "MOVSDloadidx8", asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "MOVSSstore", asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "MOVSDstore", asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "MOVSSstoreidx4", asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {2, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "MOVSDstoreidx8", asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {2, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "ADDQ", asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ADDL", asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ADDW", asm: x86.AADDW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ADDB", asm: x86.AADDB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ADDQconst", asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ADDLconst", asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ADDWconst", asm: x86.AADDW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ADDBconst", asm: x86.AADDB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SUBQ", asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SUBL", asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SUBW", asm: x86.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SUBB", asm: x86.ASUBB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SUBQconst", asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SUBLconst", asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SUBWconst", asm: x86.ASUBW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SUBBconst", asm: x86.ASUBB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MULQ", asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MULL", asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MULW", asm: x86.AIMULW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MULB", asm: x86.AIMULW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MULQconst", asm: x86.AIMULQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MULLconst", asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MULWconst", asm: x86.AIMULW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MULBconst", asm: x86.AIMULW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "HMULL", asm: x86.AIMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 4, // .DX }, }, }, { name: "HMULW", asm: x86.AIMULW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 4, // .DX }, }, }, { name: "HMULB", asm: x86.AIMULB, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 4, // .DX }, }, }, { name: "HMULLU", asm: x86.AMULL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 4, // .DX }, }, }, { name: "HMULWU", asm: x86.AMULW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 4, // .DX }, }, }, { name: "HMULBU", asm: x86.AMULB, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 4, // .DX }, }, }, { name: "DIVQ", asm: x86.AIDIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934596, // .DX .FLAGS outputs: []regMask{ 1, // .AX }, }, }, { name: "DIVL", asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934596, // .DX .FLAGS outputs: []regMask{ 1, // .AX }, }, }, { name: "DIVW", asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934596, // .DX .FLAGS outputs: []regMask{ 1, // .AX }, }, }, { name: "DIVQU", asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934596, // .DX .FLAGS outputs: []regMask{ 1, // .AX }, }, }, { name: "DIVLU", asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934596, // .DX .FLAGS outputs: []regMask{ 1, // .AX }, }, }, { name: "DIVWU", asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934596, // .DX .FLAGS outputs: []regMask{ 1, // .AX }, }, }, { name: "MODQ", asm: x86.AIDIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 4, // .DX }, }, }, { name: "MODL", asm: x86.AIDIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 4, // .DX }, }, }, { name: "MODW", asm: x86.AIDIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 4, // .DX }, }, }, { name: "MODQU", asm: x86.ADIVQ, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 4, // .DX }, }, }, { name: "MODLU", asm: x86.ADIVL, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 4, // .DX }, }, }, { name: "MODWU", asm: x86.ADIVW, reg: regInfo{ inputs: []inputInfo{ {0, 1}, // .AX {1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 4, // .DX }, }, }, { name: "ANDQ", asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ANDL", asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ANDW", asm: x86.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ANDB", asm: x86.AANDB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ANDQconst", asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ANDLconst", asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ANDWconst", asm: x86.AANDW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ANDBconst", asm: x86.AANDB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ORQ", asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ORL", asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ORW", asm: x86.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ORB", asm: x86.AORB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ORQconst", asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ORLconst", asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ORWconst", asm: x86.AORW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ORBconst", asm: x86.AORB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "XORQ", asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "XORL", asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "XORW", asm: x86.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "XORB", asm: x86.AXORB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "XORQconst", asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "XORLconst", asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "XORWconst", asm: x86.AXORW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "XORBconst", asm: x86.AXORB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "CMPQ", asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "CMPL", asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "CMPW", asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "CMPB", asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "CMPQconst", asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "CMPLconst", asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "CMPWconst", asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "CMPBconst", asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "UCOMISS", asm: x86.AUCOMISS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "UCOMISD", asm: x86.AUCOMISD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "TESTQ", asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "TESTL", asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "TESTW", asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "TESTB", asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "TESTQconst", asm: x86.ATESTQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "TESTLconst", asm: x86.ATESTL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "TESTWconst", asm: x86.ATESTW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "TESTBconst", asm: x86.ATESTB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 8589934592, // .FLAGS }, }, }, { name: "SHLQ", asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // .CX {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHLL", asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // .CX {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHLW", asm: x86.ASHLW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // .CX {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHLB", asm: x86.ASHLB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // .CX {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHLQconst", asm: x86.ASHLQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHLLconst", asm: x86.ASHLL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHLWconst", asm: x86.ASHLW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHLBconst", asm: x86.ASHLB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHRQ", asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // .CX {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHRL", asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // .CX {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHRW", asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // .CX {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHRB", asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // .CX {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHRQconst", asm: x86.ASHRQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHRLconst", asm: x86.ASHRL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHRWconst", asm: x86.ASHRW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SHRBconst", asm: x86.ASHRB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SARQ", asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // .CX {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SARL", asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // .CX {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SARW", asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // .CX {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SARB", asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {1, 2}, // .CX {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SARQconst", asm: x86.ASARQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SARLconst", asm: x86.ASARL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SARWconst", asm: x86.ASARW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SARBconst", asm: x86.ASARB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ROLQconst", asm: x86.AROLQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ROLLconst", asm: x86.AROLL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ROLWconst", asm: x86.AROLW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "ROLBconst", asm: x86.AROLB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "NEGQ", asm: x86.ANEGQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "NEGL", asm: x86.ANEGL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "NEGW", asm: x86.ANEGW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "NEGB", asm: x86.ANEGB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "NOTQ", asm: x86.ANOTQ, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "NOTL", asm: x86.ANOTL, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "NOTW", asm: x86.ANOTW, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "NOTB", asm: x86.ANOTB, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SQRTSD", asm: x86.ASQRTSD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "SBBQcarrymask", asm: x86.ASBBQ, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SBBLcarrymask", asm: x86.ASBBL, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETEQ", asm: x86.ASETEQ, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETNE", asm: x86.ASETNE, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETL", asm: x86.ASETLT, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETLE", asm: x86.ASETLE, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETG", asm: x86.ASETGT, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETGE", asm: x86.ASETGE, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETB", asm: x86.ASETCS, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETBE", asm: x86.ASETLS, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETA", asm: x86.ASETHI, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETAE", asm: x86.ASETCC, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETEQF", asm: x86.ASETEQ, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 65518, // .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETNEF", asm: x86.ASETNE, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, clobbers: 8589934593, // .AX .FLAGS outputs: []regMask{ 65518, // .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETORD", asm: x86.ASETPC, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETNAN", asm: x86.ASETPS, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETGF", asm: x86.ASETHI, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "SETGEF", asm: x86.ASETCC, reg: regInfo{ inputs: []inputInfo{ {0, 8589934592}, // .FLAGS }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVBQSX", asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVBQZX", asm: x86.AMOVBQZX, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVWQSX", asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVWQZX", asm: x86.AMOVWQZX, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVLQSX", asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVLQZX", asm: x86.AMOVLQZX, reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVBconst", asm: x86.AMOVB, reg: regInfo{ clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVWconst", asm: x86.AMOVW, reg: regInfo{ clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVLconst", asm: x86.AMOVL, reg: regInfo{ clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVQconst", asm: x86.AMOVQ, reg: regInfo{ clobbers: 8589934592, // .FLAGS outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "CVTTSD2SL", asm: x86.ACVTTSD2SL, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "CVTTSD2SQ", asm: x86.ACVTTSD2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "CVTTSS2SL", asm: x86.ACVTTSS2SL, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "CVTTSS2SQ", asm: x86.ACVTTSS2SQ, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "CVTSL2SS", asm: x86.ACVTSL2SS, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "CVTSL2SD", asm: x86.ACVTSL2SD, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "CVTSQ2SS", asm: x86.ACVTSQ2SS, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "CVTSQ2SD", asm: x86.ACVTSQ2SD, reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "CVTSD2SS", asm: x86.ACVTSD2SS, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "CVTSS2SD", asm: x86.ACVTSS2SD, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "PXOR", asm: x86.APXOR, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "LEAQ", reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "LEAQ1", reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "LEAQ2", reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "LEAQ4", reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "LEAQ8", reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVBload", asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVBQSXload", asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVBQZXload", asm: x86.AMOVBQZX, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVWload", asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVLload", asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVQload", asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVQloadidx8", asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "MOVBstore", asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "MOVWstore", asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "MOVLstore", asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "MOVQstore", asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "MOVQstoreidx8", asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {2, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "MOVOload", asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "MOVOstore", asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ {1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "MOVBstoreconst", asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "MOVWstoreconst", asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "MOVLstoreconst", asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "MOVQstoreconst", asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB }, }, }, { name: "DUFFZERO", reg: regInfo{ inputs: []inputInfo{ {0, 128}, // .DI {1, 65536}, // .X0 }, clobbers: 8589934720, // .DI .FLAGS }, }, { name: "MOVOconst", reg: regInfo{ outputs: []regMask{ 4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 }, }, }, { name: "REPSTOSQ", reg: regInfo{ inputs: []inputInfo{ {0, 128}, // .DI {1, 2}, // .CX {2, 1}, // .AX }, clobbers: 8589934722, // .CX .DI .FLAGS }, }, { name: "CALLstatic", reg: regInfo{ clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS }, }, { name: "CALLclosure", reg: regInfo{ inputs: []inputInfo{ {1, 4}, // .DX {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS }, }, { name: "CALLdefer", reg: regInfo{ clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS }, }, { name: "CALLgo", reg: regInfo{ clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS }, }, { name: "CALLinter", reg: regInfo{ inputs: []inputInfo{ {0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS }, }, { name: "DUFFCOPY", reg: regInfo{ inputs: []inputInfo{ {0, 128}, // .DI {1, 64}, // .SI }, clobbers: 65728, // .SI .DI .X0 }, }, { name: "REPMOVSQ", reg: regInfo{ inputs: []inputInfo{ {0, 128}, // .DI {1, 64}, // .SI {2, 2}, // .CX }, clobbers: 194, // .CX .SI .DI }, }, { name: "InvertFlags", reg: regInfo{}, }, { name: "LoweredGetG", reg: regInfo{ outputs: []regMask{ 65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, }, }, { name: "LoweredGetClosurePtr", reg: regInfo{ outputs: []regMask{ 4, // .DX }, }, }, { name: "LoweredNilCheck", reg: regInfo{ inputs: []inputInfo{ {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 }, clobbers: 8589934592, // .FLAGS }, }, { name: "Add8", generic: true, }, { name: "Add16", generic: true, }, { name: "Add32", generic: true, }, { name: "Add64", generic: true, }, { name: "AddPtr", generic: true, }, { name: "Add32F", generic: true, }, { name: "Add64F", generic: true, }, { name: "Sub8", generic: true, }, { name: "Sub16", generic: true, }, { name: "Sub32", generic: true, }, { name: "Sub64", generic: true, }, { name: "SubPtr", generic: true, }, { name: "Sub32F", generic: true, }, { name: "Sub64F", generic: true, }, { name: "Mul8", generic: true, }, { name: "Mul16", generic: true, }, { name: "Mul32", generic: true, }, { name: "Mul64", generic: true, }, { name: "Mul32F", generic: true, }, { name: "Mul64F", generic: true, }, { name: "Div32F", generic: true, }, { name: "Div64F", generic: true, }, { name: "Hmul8", generic: true, }, { name: "Hmul8u", generic: true, }, { name: "Hmul16", generic: true, }, { name: "Hmul16u", generic: true, }, { name: "Hmul32", generic: true, }, { name: "Hmul32u", generic: true, }, { name: "Div8", generic: true, }, { name: "Div8u", generic: true, }, { name: "Div16", generic: true, }, { name: "Div16u", generic: true, }, { name: "Div32", generic: true, }, { name: "Div32u", generic: true, }, { name: "Div64", generic: true, }, { name: "Div64u", generic: true, }, { name: "Mod8", generic: true, }, { name: "Mod8u", generic: true, }, { name: "Mod16", generic: true, }, { name: "Mod16u", generic: true, }, { name: "Mod32", generic: true, }, { name: "Mod32u", generic: true, }, { name: "Mod64", generic: true, }, { name: "Mod64u", generic: true, }, { name: "And8", generic: true, }, { name: "And16", generic: true, }, { name: "And32", generic: true, }, { name: "And64", generic: true, }, { name: "Or8", generic: true, }, { name: "Or16", generic: true, }, { name: "Or32", generic: true, }, { name: "Or64", generic: true, }, { name: "Xor8", generic: true, }, { name: "Xor16", generic: true, }, { name: "Xor32", generic: true, }, { name: "Xor64", generic: true, }, { name: "Lsh8x8", generic: true, }, { name: "Lsh8x16", generic: true, }, { name: "Lsh8x32", generic: true, }, { name: "Lsh8x64", generic: true, }, { name: "Lsh16x8", generic: true, }, { name: "Lsh16x16", generic: true, }, { name: "Lsh16x32", generic: true, }, { name: "Lsh16x64", generic: true, }, { name: "Lsh32x8", generic: true, }, { name: "Lsh32x16", generic: true, }, { name: "Lsh32x32", generic: true, }, { name: "Lsh32x64", generic: true, }, { name: "Lsh64x8", generic: true, }, { name: "Lsh64x16", generic: true, }, { name: "Lsh64x32", generic: true, }, { name: "Lsh64x64", generic: true, }, { name: "Rsh8x8", generic: true, }, { name: "Rsh8x16", generic: true, }, { name: "Rsh8x32", generic: true, }, { name: "Rsh8x64", generic: true, }, { name: "Rsh16x8", generic: true, }, { name: "Rsh16x16", generic: true, }, { name: "Rsh16x32", generic: true, }, { name: "Rsh16x64", generic: true, }, { name: "Rsh32x8", generic: true, }, { name: "Rsh32x16", generic: true, }, { name: "Rsh32x32", generic: true, }, { name: "Rsh32x64", generic: true, }, { name: "Rsh64x8", generic: true, }, { name: "Rsh64x16", generic: true, }, { name: "Rsh64x32", generic: true, }, { name: "Rsh64x64", generic: true, }, { name: "Rsh8Ux8", generic: true, }, { name: "Rsh8Ux16", generic: true, }, { name: "Rsh8Ux32", generic: true, }, { name: "Rsh8Ux64", generic: true, }, { name: "Rsh16Ux8", generic: true, }, { name: "Rsh16Ux16", generic: true, }, { name: "Rsh16Ux32", generic: true, }, { name: "Rsh16Ux64", generic: true, }, { name: "Rsh32Ux8", generic: true, }, { name: "Rsh32Ux16", generic: true, }, { name: "Rsh32Ux32", generic: true, }, { name: "Rsh32Ux64", generic: true, }, { name: "Rsh64Ux8", generic: true, }, { name: "Rsh64Ux16", generic: true, }, { name: "Rsh64Ux32", generic: true, }, { name: "Rsh64Ux64", generic: true, }, { name: "Lrot8", generic: true, }, { name: "Lrot16", generic: true, }, { name: "Lrot32", generic: true, }, { name: "Lrot64", generic: true, }, { name: "Eq8", generic: true, }, { name: "Eq16", generic: true, }, { name: "Eq32", generic: true, }, { name: "Eq64", generic: true, }, { name: "EqPtr", generic: true, }, { name: "EqInter", generic: true, }, { name: "EqSlice", generic: true, }, { name: "Eq32F", generic: true, }, { name: "Eq64F", generic: true, }, { name: "Neq8", generic: true, }, { name: "Neq16", generic: true, }, { name: "Neq32", generic: true, }, { name: "Neq64", generic: true, }, { name: "NeqPtr", generic: true, }, { name: "NeqInter", generic: true, }, { name: "NeqSlice", generic: true, }, { name: "Neq32F", generic: true, }, { name: "Neq64F", generic: true, }, { name: "Less8", generic: true, }, { name: "Less8U", generic: true, }, { name: "Less16", generic: true, }, { name: "Less16U", generic: true, }, { name: "Less32", generic: true, }, { name: "Less32U", generic: true, }, { name: "Less64", generic: true, }, { name: "Less64U", generic: true, }, { name: "Less32F", generic: true, }, { name: "Less64F", generic: true, }, { name: "Leq8", generic: true, }, { name: "Leq8U", generic: true, }, { name: "Leq16", generic: true, }, { name: "Leq16U", generic: true, }, { name: "Leq32", generic: true, }, { name: "Leq32U", generic: true, }, { name: "Leq64", generic: true, }, { name: "Leq64U", generic: true, }, { name: "Leq32F", generic: true, }, { name: "Leq64F", generic: true, }, { name: "Greater8", generic: true, }, { name: "Greater8U", generic: true, }, { name: "Greater16", generic: true, }, { name: "Greater16U", generic: true, }, { name: "Greater32", generic: true, }, { name: "Greater32U", generic: true, }, { name: "Greater64", generic: true, }, { name: "Greater64U", generic: true, }, { name: "Greater32F", generic: true, }, { name: "Greater64F", generic: true, }, { name: "Geq8", generic: true, }, { name: "Geq8U", generic: true, }, { name: "Geq16", generic: true, }, { name: "Geq16U", generic: true, }, { name: "Geq32", generic: true, }, { name: "Geq32U", generic: true, }, { name: "Geq64", generic: true, }, { name: "Geq64U", generic: true, }, { name: "Geq32F", generic: true, }, { name: "Geq64F", generic: true, }, { name: "Not", generic: true, }, { name: "Neg8", generic: true, }, { name: "Neg16", generic: true, }, { name: "Neg32", generic: true, }, { name: "Neg64", generic: true, }, { name: "Neg32F", generic: true, }, { name: "Neg64F", generic: true, }, { name: "Com8", generic: true, }, { name: "Com16", generic: true, }, { name: "Com32", generic: true, }, { name: "Com64", generic: true, }, { name: "Sqrt", generic: true, }, { name: "Phi", generic: true, }, { name: "Copy", generic: true, }, { name: "Convert", generic: true, }, { name: "ConstBool", generic: true, }, { name: "ConstString", generic: true, }, { name: "ConstNil", generic: true, }, { name: "Const8", generic: true, }, { name: "Const16", generic: true, }, { name: "Const32", generic: true, }, { name: "Const64", generic: true, }, { name: "Const32F", generic: true, }, { name: "Const64F", generic: true, }, { name: "ConstInterface", generic: true, }, { name: "ConstSlice", generic: true, }, { name: "Arg", generic: true, }, { name: "Addr", generic: true, }, { name: "SP", generic: true, }, { name: "SB", generic: true, }, { name: "Func", generic: true, }, { name: "Load", generic: true, }, { name: "Store", generic: true, }, { name: "Move", generic: true, }, { name: "Zero", generic: true, }, { name: "ClosureCall", generic: true, }, { name: "StaticCall", generic: true, }, { name: "DeferCall", generic: true, }, { name: "GoCall", generic: true, }, { name: "InterCall", generic: true, }, { name: "SignExt8to16", generic: true, }, { name: "SignExt8to32", generic: true, }, { name: "SignExt8to64", generic: true, }, { name: "SignExt16to32", generic: true, }, { name: "SignExt16to64", generic: true, }, { name: "SignExt32to64", generic: true, }, { name: "ZeroExt8to16", generic: true, }, { name: "ZeroExt8to32", generic: true, }, { name: "ZeroExt8to64", generic: true, }, { name: "ZeroExt16to32", generic: true, }, { name: "ZeroExt16to64", generic: true, }, { name: "ZeroExt32to64", generic: true, }, { name: "Trunc16to8", generic: true, }, { name: "Trunc32to8", generic: true, }, { name: "Trunc32to16", generic: true, }, { name: "Trunc64to8", generic: true, }, { name: "Trunc64to16", generic: true, }, { name: "Trunc64to32", generic: true, }, { name: "Cvt32to32F", generic: true, }, { name: "Cvt32to64F", generic: true, }, { name: "Cvt64to32F", generic: true, }, { name: "Cvt64to64F", generic: true, }, { name: "Cvt32Fto32", generic: true, }, { name: "Cvt32Fto64", generic: true, }, { name: "Cvt64Fto32", generic: true, }, { name: "Cvt64Fto64", generic: true, }, { name: "Cvt32Fto64F", generic: true, }, { name: "Cvt64Fto32F", generic: true, }, { name: "IsNonNil", generic: true, }, { name: "IsInBounds", generic: true, }, { name: "IsSliceInBounds", generic: true, }, { name: "NilCheck", generic: true, }, { name: "GetG", generic: true, }, { name: "GetClosurePtr", generic: true, }, { name: "ArrayIndex", generic: true, }, { name: "PtrIndex", generic: true, }, { name: "OffPtr", generic: true, }, { name: "StructSelect", generic: true, }, { name: "SliceMake", generic: true, }, { name: "SlicePtr", generic: true, }, { name: "SliceLen", generic: true, }, { name: "SliceCap", generic: true, }, { name: "ComplexMake", generic: true, }, { name: "ComplexReal", generic: true, }, { name: "ComplexImag", generic: true, }, { name: "StringMake", generic: true, }, { name: "StringPtr", generic: true, }, { name: "StringLen", generic: true, }, { name: "IMake", generic: true, }, { name: "ITab", generic: true, }, { name: "IData", generic: true, }, { name: "StoreReg", generic: true, }, { name: "LoadReg", generic: true, }, { name: "FwdRef", generic: true, }, { name: "VarDef", generic: true, }, { name: "VarKill", generic: true, }, } func (o Op) Asm() int { return opcodeTable[o].asm } func (o Op) String() string { return opcodeTable[o].name }