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2d33a456c6
Change-Id: I8d10399ba71e5fa97ead06a717fc972c806c0856 Reviewed-on: https://go-review.googlesource.com/c/go/+/715042 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Randall <khr@golang.org> Auto-Submit: Jorropo <jorropo.pgm@gmail.com> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Michael Pratt <mpratt@google.com>
742 lines
22 KiB
Go
742 lines
22 KiB
Go
// Copyright 2015 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package ssa
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import (
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"cmd/compile/internal/abi"
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"cmd/compile/internal/base"
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"cmd/compile/internal/ir"
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"cmd/compile/internal/types"
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"cmd/internal/obj"
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"cmd/internal/src"
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)
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// A Config holds readonly compilation information.
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// It is created once, early during compilation,
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// and shared across all compilations.
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type Config struct {
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arch string // "amd64", etc.
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PtrSize int64 // 4 or 8; copy of cmd/internal/sys.Arch.PtrSize
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RegSize int64 // 4 or 8; copy of cmd/internal/sys.Arch.RegSize
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Types Types
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lowerBlock blockRewriter // block lowering function, first round
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lowerValue valueRewriter // value lowering function, first round
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lateLowerBlock blockRewriter // block lowering function that needs to be run after the first round; only used on some architectures
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lateLowerValue valueRewriter // value lowering function that needs to be run after the first round; only used on some architectures
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splitLoad valueRewriter // function for splitting merged load ops; only used on some architectures
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registers []Register // machine registers
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gpRegMask regMask // general purpose integer register mask
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fpRegMask regMask // floating point register mask
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fp32RegMask regMask // floating point register mask
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fp64RegMask regMask // floating point register mask
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specialRegMask regMask // special register mask
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intParamRegs []int8 // register numbers of integer param (in/out) registers
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floatParamRegs []int8 // register numbers of floating param (in/out) registers
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ABI1 *abi.ABIConfig // "ABIInternal" under development // TODO change comment when this becomes current
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ABI0 *abi.ABIConfig
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FPReg int8 // register number of frame pointer, -1 if not used
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LinkReg int8 // register number of link register if it is a general purpose register, -1 if not used
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hasGReg bool // has hardware g register
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ctxt *obj.Link // Generic arch information
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optimize bool // Do optimization
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useAvg bool // Use optimizations that need Avg* operations
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useHmul bool // Use optimizations that need Hmul* operations
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SoftFloat bool //
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Race bool // race detector enabled
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BigEndian bool //
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unalignedOK bool // Unaligned loads/stores are ok
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haveBswap64 bool // architecture implements Bswap64
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haveBswap32 bool // architecture implements Bswap32
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haveBswap16 bool // architecture implements Bswap16
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haveCondSelect bool // architecture implements CondSelect
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// mulRecipes[x] = function to build v * x from v.
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mulRecipes map[int64]mulRecipe
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}
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type mulRecipe struct {
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cost int
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build func(*Value, *Value) *Value // build(m, v) returns v * x built at m.
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}
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type (
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blockRewriter func(*Block) bool
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valueRewriter func(*Value) bool
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)
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type Types struct {
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Bool *types.Type
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Int8 *types.Type
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Int16 *types.Type
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Int32 *types.Type
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Int64 *types.Type
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UInt8 *types.Type
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UInt16 *types.Type
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UInt32 *types.Type
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UInt64 *types.Type
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Int *types.Type
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Float32 *types.Type
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Float64 *types.Type
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UInt *types.Type
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Uintptr *types.Type
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String *types.Type
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BytePtr *types.Type // TODO: use unsafe.Pointer instead?
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Int32Ptr *types.Type
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UInt32Ptr *types.Type
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IntPtr *types.Type
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UintptrPtr *types.Type
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Float32Ptr *types.Type
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Float64Ptr *types.Type
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BytePtrPtr *types.Type
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}
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// NewTypes creates and populates a Types.
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func NewTypes() *Types {
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t := new(Types)
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t.SetTypPtrs()
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return t
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}
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// SetTypPtrs populates t.
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func (t *Types) SetTypPtrs() {
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t.Bool = types.Types[types.TBOOL]
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t.Int8 = types.Types[types.TINT8]
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t.Int16 = types.Types[types.TINT16]
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t.Int32 = types.Types[types.TINT32]
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t.Int64 = types.Types[types.TINT64]
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t.UInt8 = types.Types[types.TUINT8]
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t.UInt16 = types.Types[types.TUINT16]
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t.UInt32 = types.Types[types.TUINT32]
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t.UInt64 = types.Types[types.TUINT64]
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t.Int = types.Types[types.TINT]
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t.Float32 = types.Types[types.TFLOAT32]
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t.Float64 = types.Types[types.TFLOAT64]
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t.UInt = types.Types[types.TUINT]
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t.Uintptr = types.Types[types.TUINTPTR]
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t.String = types.Types[types.TSTRING]
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t.BytePtr = types.NewPtr(types.Types[types.TUINT8])
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t.Int32Ptr = types.NewPtr(types.Types[types.TINT32])
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t.UInt32Ptr = types.NewPtr(types.Types[types.TUINT32])
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t.IntPtr = types.NewPtr(types.Types[types.TINT])
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t.UintptrPtr = types.NewPtr(types.Types[types.TUINTPTR])
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t.Float32Ptr = types.NewPtr(types.Types[types.TFLOAT32])
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t.Float64Ptr = types.NewPtr(types.Types[types.TFLOAT64])
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t.BytePtrPtr = types.NewPtr(types.NewPtr(types.Types[types.TUINT8]))
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}
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type Logger interface {
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// Logf logs a message from the compiler.
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Logf(string, ...interface{})
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// Log reports whether logging is not a no-op
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// some logging calls account for more than a few heap allocations.
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Log() bool
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// Fatalf reports a compiler error and exits.
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Fatalf(pos src.XPos, msg string, args ...interface{})
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// Warnl writes compiler messages in the form expected by "errorcheck" tests
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Warnl(pos src.XPos, fmt_ string, args ...interface{})
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// Forwards the Debug flags from gc
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Debug_checknil() bool
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}
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type Frontend interface {
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Logger
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// StringData returns a symbol pointing to the given string's contents.
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StringData(string) *obj.LSym
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// Given the name for a compound type, returns the name we should use
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// for the parts of that compound type.
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SplitSlot(parent *LocalSlot, suffix string, offset int64, t *types.Type) LocalSlot
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// Syslook returns a symbol of the runtime function/variable with the
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// given name.
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Syslook(string) *obj.LSym
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// UseWriteBarrier reports whether write barrier is enabled
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UseWriteBarrier() bool
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// Func returns the ir.Func of the function being compiled.
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Func() *ir.Func
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}
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// NewConfig returns a new configuration object for the given architecture.
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func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat bool) *Config {
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c := &Config{arch: arch, Types: types}
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c.useAvg = true
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c.useHmul = true
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switch arch {
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case "amd64":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockAMD64
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c.lowerValue = rewriteValueAMD64
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c.lateLowerBlock = rewriteBlockAMD64latelower
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c.lateLowerValue = rewriteValueAMD64latelower
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c.splitLoad = rewriteValueAMD64splitload
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c.registers = registersAMD64[:]
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c.gpRegMask = gpRegMaskAMD64
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c.fpRegMask = fpRegMaskAMD64
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c.specialRegMask = specialRegMaskAMD64
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c.intParamRegs = paramIntRegAMD64
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c.floatParamRegs = paramFloatRegAMD64
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c.FPReg = framepointerRegAMD64
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c.LinkReg = linkRegAMD64
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c.hasGReg = true
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c.unalignedOK = true
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c.haveBswap64 = true
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c.haveBswap32 = true
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c.haveBswap16 = true
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c.haveCondSelect = true
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case "386":
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c.PtrSize = 4
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c.RegSize = 4
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c.lowerBlock = rewriteBlock386
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c.lowerValue = rewriteValue386
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c.splitLoad = rewriteValue386splitload
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c.registers = registers386[:]
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c.gpRegMask = gpRegMask386
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c.fpRegMask = fpRegMask386
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c.FPReg = framepointerReg386
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c.LinkReg = linkReg386
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c.hasGReg = false
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c.unalignedOK = true
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c.haveBswap32 = true
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c.haveBswap16 = true
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case "arm":
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c.PtrSize = 4
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c.RegSize = 4
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c.lowerBlock = rewriteBlockARM
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c.lowerValue = rewriteValueARM
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c.registers = registersARM[:]
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c.gpRegMask = gpRegMaskARM
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c.fpRegMask = fpRegMaskARM
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c.FPReg = framepointerRegARM
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c.LinkReg = linkRegARM
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c.hasGReg = true
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case "arm64":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockARM64
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c.lowerValue = rewriteValueARM64
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c.lateLowerBlock = rewriteBlockARM64latelower
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c.lateLowerValue = rewriteValueARM64latelower
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c.registers = registersARM64[:]
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c.gpRegMask = gpRegMaskARM64
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c.fpRegMask = fpRegMaskARM64
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c.intParamRegs = paramIntRegARM64
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c.floatParamRegs = paramFloatRegARM64
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c.FPReg = framepointerRegARM64
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c.LinkReg = linkRegARM64
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c.hasGReg = true
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c.unalignedOK = true
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c.haveBswap64 = true
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c.haveBswap32 = true
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c.haveBswap16 = true
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c.haveCondSelect = true
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case "ppc64":
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c.BigEndian = true
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fallthrough
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case "ppc64le":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockPPC64
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c.lowerValue = rewriteValuePPC64
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c.lateLowerBlock = rewriteBlockPPC64latelower
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c.lateLowerValue = rewriteValuePPC64latelower
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c.registers = registersPPC64[:]
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c.gpRegMask = gpRegMaskPPC64
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c.fpRegMask = fpRegMaskPPC64
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c.specialRegMask = specialRegMaskPPC64
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c.intParamRegs = paramIntRegPPC64
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c.floatParamRegs = paramFloatRegPPC64
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c.FPReg = framepointerRegPPC64
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c.LinkReg = linkRegPPC64
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c.hasGReg = true
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c.unalignedOK = true
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// Note: ppc64 has register bswap ops only when GOPPC64>=10.
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// But it has bswap+load and bswap+store ops for all ppc64 variants.
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// That is the sense we're using them here - they are only used
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// in contexts where they can be merged with a load or store.
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c.haveBswap64 = true
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c.haveBswap32 = true
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c.haveBswap16 = true
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c.haveCondSelect = true
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case "mips64":
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c.BigEndian = true
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fallthrough
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case "mips64le":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockMIPS64
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c.lowerValue = rewriteValueMIPS64
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c.lateLowerBlock = rewriteBlockMIPS64latelower
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c.lateLowerValue = rewriteValueMIPS64latelower
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c.registers = registersMIPS64[:]
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c.gpRegMask = gpRegMaskMIPS64
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c.fpRegMask = fpRegMaskMIPS64
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c.specialRegMask = specialRegMaskMIPS64
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c.FPReg = framepointerRegMIPS64
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c.LinkReg = linkRegMIPS64
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c.hasGReg = true
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case "loong64":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockLOONG64
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c.lowerValue = rewriteValueLOONG64
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c.lateLowerBlock = rewriteBlockLOONG64latelower
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c.lateLowerValue = rewriteValueLOONG64latelower
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c.registers = registersLOONG64[:]
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c.gpRegMask = gpRegMaskLOONG64
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c.fpRegMask = fpRegMaskLOONG64
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c.intParamRegs = paramIntRegLOONG64
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c.floatParamRegs = paramFloatRegLOONG64
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c.FPReg = framepointerRegLOONG64
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c.LinkReg = linkRegLOONG64
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c.hasGReg = true
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c.unalignedOK = true
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c.haveCondSelect = true
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case "s390x":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockS390X
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c.lowerValue = rewriteValueS390X
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c.registers = registersS390X[:]
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c.gpRegMask = gpRegMaskS390X
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c.fpRegMask = fpRegMaskS390X
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c.FPReg = framepointerRegS390X
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c.LinkReg = linkRegS390X
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c.hasGReg = true
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c.BigEndian = true
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c.unalignedOK = true
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c.haveBswap64 = true
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c.haveBswap32 = true
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c.haveBswap16 = true // only for loads&stores, see ppc64 comment
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case "mips":
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c.BigEndian = true
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fallthrough
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case "mipsle":
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c.PtrSize = 4
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c.RegSize = 4
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c.lowerBlock = rewriteBlockMIPS
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c.lowerValue = rewriteValueMIPS
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c.registers = registersMIPS[:]
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c.gpRegMask = gpRegMaskMIPS
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c.fpRegMask = fpRegMaskMIPS
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c.specialRegMask = specialRegMaskMIPS
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c.FPReg = framepointerRegMIPS
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c.LinkReg = linkRegMIPS
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c.hasGReg = true
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case "riscv64":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockRISCV64
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c.lowerValue = rewriteValueRISCV64
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c.lateLowerBlock = rewriteBlockRISCV64latelower
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c.lateLowerValue = rewriteValueRISCV64latelower
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c.registers = registersRISCV64[:]
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c.gpRegMask = gpRegMaskRISCV64
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c.fpRegMask = fpRegMaskRISCV64
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c.intParamRegs = paramIntRegRISCV64
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c.floatParamRegs = paramFloatRegRISCV64
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c.FPReg = framepointerRegRISCV64
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c.hasGReg = true
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case "wasm":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockWasm
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c.lowerValue = rewriteValueWasm
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c.registers = registersWasm[:]
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c.gpRegMask = gpRegMaskWasm
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c.fpRegMask = fpRegMaskWasm
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c.fp32RegMask = fp32RegMaskWasm
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c.fp64RegMask = fp64RegMaskWasm
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c.FPReg = framepointerRegWasm
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c.LinkReg = linkRegWasm
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c.hasGReg = true
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c.useAvg = false
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c.useHmul = false
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c.unalignedOK = true
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c.haveCondSelect = true
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default:
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ctxt.Diag("arch %s not implemented", arch)
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}
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c.ctxt = ctxt
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c.optimize = optimize
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c.SoftFloat = softfloat
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if softfloat {
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c.floatParamRegs = nil // no FP registers in softfloat mode
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}
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c.ABI0 = abi.NewABIConfig(0, 0, ctxt.Arch.FixedFrameSize, 0)
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c.ABI1 = abi.NewABIConfig(len(c.intParamRegs), len(c.floatParamRegs), ctxt.Arch.FixedFrameSize, 1)
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if ctxt.Flag_shared {
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// LoweredWB is secretly a CALL and CALLs on 386 in
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// shared mode get rewritten by obj6.go to go through
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// the GOT, which clobbers BX.
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opcodeTable[Op386LoweredWB].reg.clobbers |= 1 << 3 // BX
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}
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c.buildRecipes(arch)
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return c
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}
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func (c *Config) Ctxt() *obj.Link { return c.ctxt }
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func (c *Config) haveByteSwap(size int64) bool {
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switch size {
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case 8:
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return c.haveBswap64
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case 4:
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return c.haveBswap32
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case 2:
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return c.haveBswap16
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default:
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base.Fatalf("bad size %d\n", size)
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return false
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}
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}
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func (c *Config) buildRecipes(arch string) {
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// Information for strength-reducing multiplies.
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type linearCombo struct {
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// we can compute a*x+b*y in one instruction
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a, b int64
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// cost, in arbitrary units (tenths of cycles, usually)
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cost int
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// builds SSA value for a*x+b*y. Use the position
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// information from m.
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build func(m, x, y *Value) *Value
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}
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// List all the linear combination instructions we have.
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var linearCombos []linearCombo
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r := func(a, b int64, cost int, build func(m, x, y *Value) *Value) {
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linearCombos = append(linearCombos, linearCombo{a: a, b: b, cost: cost, build: build})
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}
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var mulCost int
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switch arch {
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case "amd64":
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// Assumes that the following costs from https://gmplib.org/~tege/x86-timing.pdf:
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// 1 - addq, shlq, leaq, negq, subq
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// 3 - imulq
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// These costs limit the rewrites to two instructions.
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// Operations which have to happen in place (and thus
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// may require a reg-reg move) score slightly higher.
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mulCost = 30
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// add
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r(1, 1, 10,
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func(m, x, y *Value) *Value {
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v := m.Block.NewValue2(m.Pos, OpAMD64ADDQ, m.Type, x, y)
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if m.Type.Size() == 4 {
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v.Op = OpAMD64ADDL
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}
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return v
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})
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// neg
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r(-1, 0, 11,
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func(m, x, y *Value) *Value {
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v := m.Block.NewValue1(m.Pos, OpAMD64NEGQ, m.Type, x)
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if m.Type.Size() == 4 {
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v.Op = OpAMD64NEGL
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}
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return v
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})
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// sub
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r(1, -1, 11,
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func(m, x, y *Value) *Value {
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v := m.Block.NewValue2(m.Pos, OpAMD64SUBQ, m.Type, x, y)
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if m.Type.Size() == 4 {
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v.Op = OpAMD64SUBL
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}
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return v
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})
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// lea
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r(1, 2, 10,
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func(m, x, y *Value) *Value {
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v := m.Block.NewValue2(m.Pos, OpAMD64LEAQ2, m.Type, x, y)
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if m.Type.Size() == 4 {
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v.Op = OpAMD64LEAL2
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}
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return v
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})
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r(1, 4, 10,
|
|
func(m, x, y *Value) *Value {
|
|
v := m.Block.NewValue2(m.Pos, OpAMD64LEAQ4, m.Type, x, y)
|
|
if m.Type.Size() == 4 {
|
|
v.Op = OpAMD64LEAL4
|
|
}
|
|
return v
|
|
})
|
|
r(1, 8, 10,
|
|
func(m, x, y *Value) *Value {
|
|
v := m.Block.NewValue2(m.Pos, OpAMD64LEAQ8, m.Type, x, y)
|
|
if m.Type.Size() == 4 {
|
|
v.Op = OpAMD64LEAL8
|
|
}
|
|
return v
|
|
})
|
|
// regular shifts
|
|
for i := 2; i < 64; i++ {
|
|
r(1<<i, 0, 11,
|
|
func(m, x, y *Value) *Value {
|
|
v := m.Block.NewValue1I(m.Pos, OpAMD64SHLQconst, m.Type, int64(i), x)
|
|
if m.Type.Size() == 4 {
|
|
v.Op = OpAMD64SHLLconst
|
|
}
|
|
return v
|
|
})
|
|
}
|
|
|
|
case "arm64":
|
|
// Rationale (for M2 ultra):
|
|
// - multiply is 3 cycles.
|
|
// - add/neg/sub/shift are 1 cycle.
|
|
// - add/neg/sub+shiftLL are 2 cycles.
|
|
// We break ties against the multiply because using a
|
|
// multiply also needs to load the constant into a register.
|
|
// (It's 3 cycles and 2 instructions either way, but the
|
|
// linear combo one might use 1 less register.)
|
|
// The multiply constant might get lifted out of a loop though. Hmm....
|
|
// Other arm64 chips have different tradeoffs.
|
|
// Some chip's add+shift instructions are 1 cycle for shifts up to 4
|
|
// and 2 cycles for shifts bigger than 4. So weight the larger shifts
|
|
// a bit more.
|
|
// TODO: figure out a happy medium.
|
|
mulCost = 35
|
|
// add
|
|
r(1, 1, 10,
|
|
func(m, x, y *Value) *Value {
|
|
return m.Block.NewValue2(m.Pos, OpARM64ADD, m.Type, x, y)
|
|
})
|
|
// neg
|
|
r(-1, 0, 10,
|
|
func(m, x, y *Value) *Value {
|
|
return m.Block.NewValue1(m.Pos, OpARM64NEG, m.Type, x)
|
|
})
|
|
// sub
|
|
r(1, -1, 10,
|
|
func(m, x, y *Value) *Value {
|
|
return m.Block.NewValue2(m.Pos, OpARM64SUB, m.Type, x, y)
|
|
})
|
|
// regular shifts
|
|
for i := 1; i < 64; i++ {
|
|
c := 10
|
|
if i == 1 {
|
|
// Prefer x<<1 over x+x.
|
|
// Note that we eventually reverse this decision in ARM64latelower.rules,
|
|
// but this makes shift combining rules in ARM64.rules simpler.
|
|
c--
|
|
}
|
|
r(1<<i, 0, c,
|
|
func(m, x, y *Value) *Value {
|
|
return m.Block.NewValue1I(m.Pos, OpARM64SLLconst, m.Type, int64(i), x)
|
|
})
|
|
}
|
|
// ADDshiftLL
|
|
for i := 1; i < 64; i++ {
|
|
c := 20
|
|
if i > 4 {
|
|
c++
|
|
}
|
|
r(1, 1<<i, c,
|
|
func(m, x, y *Value) *Value {
|
|
return m.Block.NewValue2I(m.Pos, OpARM64ADDshiftLL, m.Type, int64(i), x, y)
|
|
})
|
|
}
|
|
// NEGshiftLL
|
|
for i := 1; i < 64; i++ {
|
|
c := 20
|
|
if i > 4 {
|
|
c++
|
|
}
|
|
r(-1<<i, 0, c,
|
|
func(m, x, y *Value) *Value {
|
|
return m.Block.NewValue1I(m.Pos, OpARM64NEGshiftLL, m.Type, int64(i), x)
|
|
})
|
|
}
|
|
// SUBshiftLL
|
|
for i := 1; i < 64; i++ {
|
|
c := 20
|
|
if i > 4 {
|
|
c++
|
|
}
|
|
r(1, -1<<i, c,
|
|
func(m, x, y *Value) *Value {
|
|
return m.Block.NewValue2I(m.Pos, OpARM64SUBshiftLL, m.Type, int64(i), x, y)
|
|
})
|
|
}
|
|
case "loong64":
|
|
// - multiply is 4 cycles.
|
|
// - add/sub/shift/alsl are 1 cycle.
|
|
// On loong64, using a multiply also needs to load the constant into a register.
|
|
// TODO: figure out a happy medium.
|
|
mulCost = 45
|
|
|
|
// add
|
|
r(1, 1, 10,
|
|
func(m, x, y *Value) *Value {
|
|
return m.Block.NewValue2(m.Pos, OpLOONG64ADDV, m.Type, x, y)
|
|
})
|
|
// neg
|
|
r(-1, 0, 10,
|
|
func(m, x, y *Value) *Value {
|
|
return m.Block.NewValue1(m.Pos, OpLOONG64NEGV, m.Type, x)
|
|
})
|
|
// sub
|
|
r(1, -1, 10,
|
|
func(m, x, y *Value) *Value {
|
|
return m.Block.NewValue2(m.Pos, OpLOONG64SUBV, m.Type, x, y)
|
|
})
|
|
|
|
// regular shifts
|
|
for i := 1; i < 64; i++ {
|
|
c := 10
|
|
if i == 1 {
|
|
// Prefer x<<1 over x+x.
|
|
// Note that we eventually reverse this decision in LOONG64latelower.rules,
|
|
// but this makes shift combining rules in LOONG64.rules simpler.
|
|
c--
|
|
}
|
|
r(1<<i, 0, c,
|
|
func(m, x, y *Value) *Value {
|
|
return m.Block.NewValue1I(m.Pos, OpLOONG64SLLVconst, m.Type, int64(i), x)
|
|
})
|
|
}
|
|
|
|
// ADDshiftLLV
|
|
for i := 1; i < 5; i++ {
|
|
c := 10
|
|
r(1, 1<<i, c,
|
|
func(m, x, y *Value) *Value {
|
|
return m.Block.NewValue2I(m.Pos, OpLOONG64ADDshiftLLV, m.Type, int64(i), x, y)
|
|
})
|
|
}
|
|
}
|
|
|
|
c.mulRecipes = map[int64]mulRecipe{}
|
|
|
|
// Single-instruction recipes.
|
|
// The only option for the input value(s) is v.
|
|
for _, combo := range linearCombos {
|
|
x := combo.a + combo.b
|
|
cost := combo.cost
|
|
old := c.mulRecipes[x]
|
|
if (old.build == nil || cost < old.cost) && cost < mulCost {
|
|
c.mulRecipes[x] = mulRecipe{cost: cost, build: func(m, v *Value) *Value {
|
|
return combo.build(m, v, v)
|
|
}}
|
|
}
|
|
}
|
|
// Two-instruction recipes.
|
|
// A: Both of the outer's inputs are from the same single-instruction recipe.
|
|
// B: First input is v and the second is from a single-instruction recipe.
|
|
// C: Second input is v and the first is from a single-instruction recipe.
|
|
// A is slightly preferred because it often needs 1 less register, so it
|
|
// goes first.
|
|
|
|
// A
|
|
for _, inner := range linearCombos {
|
|
for _, outer := range linearCombos {
|
|
x := (inner.a + inner.b) * (outer.a + outer.b)
|
|
cost := inner.cost + outer.cost
|
|
old := c.mulRecipes[x]
|
|
if (old.build == nil || cost < old.cost) && cost < mulCost {
|
|
c.mulRecipes[x] = mulRecipe{cost: cost, build: func(m, v *Value) *Value {
|
|
v = inner.build(m, v, v)
|
|
return outer.build(m, v, v)
|
|
}}
|
|
}
|
|
}
|
|
}
|
|
|
|
// B
|
|
for _, inner := range linearCombos {
|
|
for _, outer := range linearCombos {
|
|
x := outer.a + outer.b*(inner.a+inner.b)
|
|
cost := inner.cost + outer.cost
|
|
old := c.mulRecipes[x]
|
|
if (old.build == nil || cost < old.cost) && cost < mulCost {
|
|
c.mulRecipes[x] = mulRecipe{cost: cost, build: func(m, v *Value) *Value {
|
|
return outer.build(m, v, inner.build(m, v, v))
|
|
}}
|
|
}
|
|
}
|
|
}
|
|
|
|
// C
|
|
for _, inner := range linearCombos {
|
|
for _, outer := range linearCombos {
|
|
x := outer.a*(inner.a+inner.b) + outer.b
|
|
cost := inner.cost + outer.cost
|
|
old := c.mulRecipes[x]
|
|
if (old.build == nil || cost < old.cost) && cost < mulCost {
|
|
c.mulRecipes[x] = mulRecipe{cost: cost, build: func(m, v *Value) *Value {
|
|
return outer.build(m, inner.build(m, v, v), v)
|
|
}}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Currently we only process 3 linear combination instructions for loong64.
|
|
if arch == "loong64" {
|
|
// Three-instruction recipes.
|
|
// D: The first and the second are all single-instruction recipes, and they are also the third's inputs.
|
|
// E: The first single-instruction is the second's input, and the second is the third's input.
|
|
|
|
// D
|
|
for _, first := range linearCombos {
|
|
for _, second := range linearCombos {
|
|
for _, third := range linearCombos {
|
|
x := third.a*(first.a+first.b) + third.b*(second.a+second.b)
|
|
cost := first.cost + second.cost + third.cost
|
|
old := c.mulRecipes[x]
|
|
if (old.build == nil || cost < old.cost) && cost < mulCost {
|
|
c.mulRecipes[x] = mulRecipe{cost: cost, build: func(m, v *Value) *Value {
|
|
v1 := first.build(m, v, v)
|
|
v2 := second.build(m, v, v)
|
|
return third.build(m, v1, v2)
|
|
}}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// E
|
|
for _, first := range linearCombos {
|
|
for _, second := range linearCombos {
|
|
for _, third := range linearCombos {
|
|
x := third.a*(second.a*(first.a+first.b)+second.b) + third.b
|
|
cost := first.cost + second.cost + third.cost
|
|
old := c.mulRecipes[x]
|
|
if (old.build == nil || cost < old.cost) && cost < mulCost {
|
|
c.mulRecipes[x] = mulRecipe{cost: cost, build: func(m, v *Value) *Value {
|
|
v1 := first.build(m, v, v)
|
|
v2 := second.build(m, v1, v)
|
|
return third.build(m, v2, v)
|
|
}}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// These cases should be handled specially by rewrite rules.
|
|
// (Otherwise v * 1 == (neg (neg v)))
|
|
delete(c.mulRecipes, 0)
|
|
delete(c.mulRecipes, 1)
|
|
|
|
// Currently:
|
|
// len(c.mulRecipes) == 5984 on arm64
|
|
// 680 on amd64
|
|
// 9738 on loong64
|
|
// This function takes ~2.5ms on arm64.
|
|
//println(len(c.mulRecipes))
|
|
}
|