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656f0888b7
Previously, softfloat mode does not work with register ABI, mainly because the compiler doesn't know how to pass floating point arguments and results. According to the ABI it should be passed in FP registers, but there isn't any in softfloat mode. This CL makes it work. When softfloat is used, we define the ABI as having 0 floating point registers (because there aren't any). The integer registers are unchanged. So floating point arguments and results are passed in memory. Another option is to pass (the bit representation of) floating point values in integer registers. But this complicates things because it'd need to reorder integer argument registers. Change-Id: Ibecbeccb658c10a868fa7f2dcf75138f719cc809 Reviewed-on: https://go-review.googlesource.com/c/go/+/327274 Trust: Cherry Mui <cherryyz@google.com> Run-TryBot: Cherry Mui <cherryyz@google.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: David Chase <drchase@google.com>
368 lines
11 KiB
Go
368 lines
11 KiB
Go
// Copyright 2015 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package ssa
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import (
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"cmd/compile/internal/abi"
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"cmd/compile/internal/ir"
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"cmd/compile/internal/types"
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"cmd/internal/obj"
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"cmd/internal/src"
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"internal/buildcfg"
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)
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// A Config holds readonly compilation information.
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// It is created once, early during compilation,
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// and shared across all compilations.
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type Config struct {
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arch string // "amd64", etc.
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PtrSize int64 // 4 or 8; copy of cmd/internal/sys.Arch.PtrSize
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RegSize int64 // 4 or 8; copy of cmd/internal/sys.Arch.RegSize
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Types Types
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lowerBlock blockRewriter // lowering function
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lowerValue valueRewriter // lowering function
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splitLoad valueRewriter // function for splitting merged load ops; only used on some architectures
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registers []Register // machine registers
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gpRegMask regMask // general purpose integer register mask
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fpRegMask regMask // floating point register mask
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fp32RegMask regMask // floating point register mask
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fp64RegMask regMask // floating point register mask
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specialRegMask regMask // special register mask
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intParamRegs []int8 // register numbers of integer param (in/out) registers
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floatParamRegs []int8 // register numbers of floating param (in/out) registers
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ABI1 *abi.ABIConfig // "ABIInternal" under development // TODO change comment when this becomes current
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ABI0 *abi.ABIConfig
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GCRegMap []*Register // garbage collector register map, by GC register index
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FPReg int8 // register number of frame pointer, -1 if not used
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LinkReg int8 // register number of link register if it is a general purpose register, -1 if not used
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hasGReg bool // has hardware g register
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ctxt *obj.Link // Generic arch information
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optimize bool // Do optimization
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noDuffDevice bool // Don't use Duff's device
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useSSE bool // Use SSE for non-float operations
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useAvg bool // Use optimizations that need Avg* operations
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useHmul bool // Use optimizations that need Hmul* operations
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SoftFloat bool //
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Race bool // race detector enabled
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BigEndian bool //
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UseFMA bool // Use hardware FMA operation
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}
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type (
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blockRewriter func(*Block) bool
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valueRewriter func(*Value) bool
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)
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type Types struct {
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Bool *types.Type
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Int8 *types.Type
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Int16 *types.Type
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Int32 *types.Type
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Int64 *types.Type
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UInt8 *types.Type
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UInt16 *types.Type
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UInt32 *types.Type
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UInt64 *types.Type
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Int *types.Type
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Float32 *types.Type
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Float64 *types.Type
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UInt *types.Type
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Uintptr *types.Type
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String *types.Type
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BytePtr *types.Type // TODO: use unsafe.Pointer instead?
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Int32Ptr *types.Type
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UInt32Ptr *types.Type
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IntPtr *types.Type
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UintptrPtr *types.Type
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Float32Ptr *types.Type
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Float64Ptr *types.Type
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BytePtrPtr *types.Type
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}
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// NewTypes creates and populates a Types.
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func NewTypes() *Types {
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t := new(Types)
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t.SetTypPtrs()
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return t
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}
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// SetTypPtrs populates t.
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func (t *Types) SetTypPtrs() {
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t.Bool = types.Types[types.TBOOL]
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t.Int8 = types.Types[types.TINT8]
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t.Int16 = types.Types[types.TINT16]
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t.Int32 = types.Types[types.TINT32]
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t.Int64 = types.Types[types.TINT64]
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t.UInt8 = types.Types[types.TUINT8]
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t.UInt16 = types.Types[types.TUINT16]
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t.UInt32 = types.Types[types.TUINT32]
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t.UInt64 = types.Types[types.TUINT64]
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t.Int = types.Types[types.TINT]
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t.Float32 = types.Types[types.TFLOAT32]
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t.Float64 = types.Types[types.TFLOAT64]
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t.UInt = types.Types[types.TUINT]
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t.Uintptr = types.Types[types.TUINTPTR]
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t.String = types.Types[types.TSTRING]
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t.BytePtr = types.NewPtr(types.Types[types.TUINT8])
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t.Int32Ptr = types.NewPtr(types.Types[types.TINT32])
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t.UInt32Ptr = types.NewPtr(types.Types[types.TUINT32])
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t.IntPtr = types.NewPtr(types.Types[types.TINT])
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t.UintptrPtr = types.NewPtr(types.Types[types.TUINTPTR])
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t.Float32Ptr = types.NewPtr(types.Types[types.TFLOAT32])
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t.Float64Ptr = types.NewPtr(types.Types[types.TFLOAT64])
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t.BytePtrPtr = types.NewPtr(types.NewPtr(types.Types[types.TUINT8]))
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}
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type Logger interface {
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// Logf logs a message from the compiler.
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Logf(string, ...interface{})
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// Log reports whether logging is not a no-op
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// some logging calls account for more than a few heap allocations.
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Log() bool
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// Fatal reports a compiler error and exits.
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Fatalf(pos src.XPos, msg string, args ...interface{})
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// Warnl writes compiler messages in the form expected by "errorcheck" tests
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Warnl(pos src.XPos, fmt_ string, args ...interface{})
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// Forwards the Debug flags from gc
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Debug_checknil() bool
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}
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type Frontend interface {
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CanSSA(t *types.Type) bool
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Logger
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// StringData returns a symbol pointing to the given string's contents.
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StringData(string) *obj.LSym
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// Auto returns a Node for an auto variable of the given type.
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// The SSA compiler uses this function to allocate space for spills.
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Auto(src.XPos, *types.Type) *ir.Name
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// Given the name for a compound type, returns the name we should use
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// for the parts of that compound type.
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SplitSlot(parent *LocalSlot, suffix string, offset int64, t *types.Type) LocalSlot
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// Line returns a string describing the given position.
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Line(src.XPos) string
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// AllocFrame assigns frame offsets to all live auto variables.
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AllocFrame(f *Func)
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// Syslook returns a symbol of the runtime function/variable with the
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// given name.
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Syslook(string) *obj.LSym
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// UseWriteBarrier reports whether write barrier is enabled
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UseWriteBarrier() bool
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// SetWBPos indicates that a write barrier has been inserted
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// in this function at position pos.
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SetWBPos(pos src.XPos)
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// MyImportPath provides the import name (roughly, the package) for the function being compiled.
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MyImportPath() string
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}
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// NewConfig returns a new configuration object for the given architecture.
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func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat bool) *Config {
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c := &Config{arch: arch, Types: types}
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c.useAvg = true
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c.useHmul = true
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switch arch {
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case "amd64":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockAMD64
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c.lowerValue = rewriteValueAMD64
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c.splitLoad = rewriteValueAMD64splitload
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c.registers = registersAMD64[:]
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c.gpRegMask = gpRegMaskAMD64
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c.fpRegMask = fpRegMaskAMD64
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c.specialRegMask = specialRegMaskAMD64
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c.intParamRegs = paramIntRegAMD64
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c.floatParamRegs = paramFloatRegAMD64
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c.FPReg = framepointerRegAMD64
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c.LinkReg = linkRegAMD64
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c.hasGReg = true
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case "386":
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c.PtrSize = 4
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c.RegSize = 4
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c.lowerBlock = rewriteBlock386
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c.lowerValue = rewriteValue386
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c.splitLoad = rewriteValue386splitload
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c.registers = registers386[:]
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c.gpRegMask = gpRegMask386
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c.fpRegMask = fpRegMask386
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c.FPReg = framepointerReg386
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c.LinkReg = linkReg386
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c.hasGReg = false
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case "arm":
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c.PtrSize = 4
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c.RegSize = 4
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c.lowerBlock = rewriteBlockARM
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c.lowerValue = rewriteValueARM
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c.registers = registersARM[:]
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c.gpRegMask = gpRegMaskARM
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c.fpRegMask = fpRegMaskARM
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c.FPReg = framepointerRegARM
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c.LinkReg = linkRegARM
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c.hasGReg = true
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case "arm64":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockARM64
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c.lowerValue = rewriteValueARM64
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c.registers = registersARM64[:]
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c.gpRegMask = gpRegMaskARM64
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c.fpRegMask = fpRegMaskARM64
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c.intParamRegs = paramIntRegARM64
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c.floatParamRegs = paramFloatRegARM64
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c.FPReg = framepointerRegARM64
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c.LinkReg = linkRegARM64
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c.hasGReg = true
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c.noDuffDevice = buildcfg.GOOS == "darwin" || buildcfg.GOOS == "ios" // darwin linker cannot handle BR26 reloc with non-zero addend
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case "ppc64":
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c.BigEndian = true
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fallthrough
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case "ppc64le":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockPPC64
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c.lowerValue = rewriteValuePPC64
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c.registers = registersPPC64[:]
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c.gpRegMask = gpRegMaskPPC64
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c.fpRegMask = fpRegMaskPPC64
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c.FPReg = framepointerRegPPC64
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c.LinkReg = linkRegPPC64
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c.noDuffDevice = true // TODO: Resolve PPC64 DuffDevice (has zero, but not copy)
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c.hasGReg = true
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case "mips64":
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c.BigEndian = true
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fallthrough
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case "mips64le":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockMIPS64
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c.lowerValue = rewriteValueMIPS64
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c.registers = registersMIPS64[:]
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c.gpRegMask = gpRegMaskMIPS64
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c.fpRegMask = fpRegMaskMIPS64
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c.specialRegMask = specialRegMaskMIPS64
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c.FPReg = framepointerRegMIPS64
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c.LinkReg = linkRegMIPS64
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c.hasGReg = true
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case "s390x":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockS390X
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c.lowerValue = rewriteValueS390X
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c.registers = registersS390X[:]
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c.gpRegMask = gpRegMaskS390X
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c.fpRegMask = fpRegMaskS390X
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c.FPReg = framepointerRegS390X
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c.LinkReg = linkRegS390X
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c.hasGReg = true
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c.noDuffDevice = true
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c.BigEndian = true
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case "mips":
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c.BigEndian = true
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fallthrough
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case "mipsle":
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c.PtrSize = 4
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c.RegSize = 4
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c.lowerBlock = rewriteBlockMIPS
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c.lowerValue = rewriteValueMIPS
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c.registers = registersMIPS[:]
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c.gpRegMask = gpRegMaskMIPS
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c.fpRegMask = fpRegMaskMIPS
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c.specialRegMask = specialRegMaskMIPS
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c.FPReg = framepointerRegMIPS
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c.LinkReg = linkRegMIPS
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c.hasGReg = true
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c.noDuffDevice = true
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case "riscv64":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockRISCV64
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c.lowerValue = rewriteValueRISCV64
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c.registers = registersRISCV64[:]
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c.gpRegMask = gpRegMaskRISCV64
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c.fpRegMask = fpRegMaskRISCV64
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c.FPReg = framepointerRegRISCV64
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c.hasGReg = true
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case "wasm":
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c.PtrSize = 8
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c.RegSize = 8
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c.lowerBlock = rewriteBlockWasm
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c.lowerValue = rewriteValueWasm
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c.registers = registersWasm[:]
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c.gpRegMask = gpRegMaskWasm
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c.fpRegMask = fpRegMaskWasm
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c.fp32RegMask = fp32RegMaskWasm
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c.fp64RegMask = fp64RegMaskWasm
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c.FPReg = framepointerRegWasm
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c.LinkReg = linkRegWasm
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c.hasGReg = true
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c.noDuffDevice = true
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c.useAvg = false
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c.useHmul = false
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default:
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ctxt.Diag("arch %s not implemented", arch)
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}
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c.ctxt = ctxt
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c.optimize = optimize
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c.useSSE = true
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c.UseFMA = true
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c.SoftFloat = softfloat
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if softfloat {
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c.floatParamRegs = nil // no FP registers in softfloat mode
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}
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c.ABI0 = abi.NewABIConfig(0, 0, ctxt.FixedFrameSize())
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c.ABI1 = abi.NewABIConfig(len(c.intParamRegs), len(c.floatParamRegs), ctxt.FixedFrameSize())
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// On Plan 9, floating point operations are not allowed in note handler.
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if buildcfg.GOOS == "plan9" {
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// Don't use FMA on Plan 9
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c.UseFMA = false
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// Don't use Duff's device and SSE on Plan 9 AMD64.
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if arch == "amd64" {
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c.noDuffDevice = true
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c.useSSE = false
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}
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}
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if ctxt.Flag_shared {
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// LoweredWB is secretly a CALL and CALLs on 386 in
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// shared mode get rewritten by obj6.go to go through
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// the GOT, which clobbers BX.
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opcodeTable[Op386LoweredWB].reg.clobbers |= 1 << 3 // BX
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}
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// Create the GC register map index.
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// TODO: This is only used for debug printing. Maybe export config.registers?
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gcRegMapSize := int16(0)
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for _, r := range c.registers {
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if r.gcNum+1 > gcRegMapSize {
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gcRegMapSize = r.gcNum + 1
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}
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}
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c.GCRegMap = make([]*Register, gcRegMapSize)
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for i, r := range c.registers {
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if r.gcNum != -1 {
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c.GCRegMap[r.gcNum] = &c.registers[i]
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}
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}
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return c
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}
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func (c *Config) Ctxt() *obj.Link { return c.ctxt }
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