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6b8d507508
https://github.com/riscv/riscv-opcodes/pull/361. After this pr was merged, riscv-opcode can generate RVV segment load/store instructions for Go. Implement vector segment load/store instuctions. Change-Id: I154bb75be70c0a45e2279a75c67f68b5bb57c36e Reviewed-on: https://go-review.googlesource.com/c/go/+/691695 Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
1716 lines
27 KiB
Go
1716 lines
27 KiB
Go
// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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// Portions Copyright © 1997-1999 Vita Nuova Limited
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// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
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// Portions Copyright © 2004,2006 Bruce Ellis
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// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
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// Portions Copyright © 2009 The Go Authors. All rights reserved.
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// Portions Copyright © 2019 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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package riscv
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import (
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"errors"
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"fmt"
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"cmd/internal/obj"
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)
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var CSRs map[uint16]string = csrs
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//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
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const (
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// Base register numberings.
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REG_X0 = obj.RBaseRISCV + iota
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REG_X1
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REG_X2
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REG_X3
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REG_X4
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REG_X5
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REG_X6
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REG_X7
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REG_X8
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REG_X9
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REG_X10
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REG_X11
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REG_X12
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REG_X13
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REG_X14
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REG_X15
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REG_X16
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REG_X17
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REG_X18
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REG_X19
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REG_X20
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REG_X21
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REG_X22
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REG_X23
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REG_X24
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REG_X25
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REG_X26
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REG_X27
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REG_X28
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REG_X29
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REG_X30
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REG_X31
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// Floating Point register numberings.
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REG_F0
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REG_F1
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REG_F2
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REG_F3
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REG_F4
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REG_F5
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REG_F6
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REG_F7
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REG_F8
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REG_F9
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REG_F10
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REG_F11
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REG_F12
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REG_F13
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REG_F14
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REG_F15
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REG_F16
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REG_F17
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REG_F18
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REG_F19
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REG_F20
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REG_F21
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REG_F22
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REG_F23
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REG_F24
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REG_F25
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REG_F26
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REG_F27
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REG_F28
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REG_F29
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REG_F30
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REG_F31
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// Vector register numberings.
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REG_V0
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REG_V1
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REG_V2
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REG_V3
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REG_V4
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REG_V5
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REG_V6
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REG_V7
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REG_V8
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REG_V9
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REG_V10
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REG_V11
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REG_V12
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REG_V13
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REG_V14
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REG_V15
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REG_V16
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REG_V17
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REG_V18
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REG_V19
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REG_V20
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REG_V21
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REG_V22
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REG_V23
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REG_V24
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REG_V25
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REG_V26
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REG_V27
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REG_V28
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REG_V29
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REG_V30
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REG_V31
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// This marks the end of the register numbering.
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REG_END
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// General registers reassigned to ABI names.
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REG_ZERO = REG_X0
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REG_RA = REG_X1 // aka REG_LR
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REG_SP = REG_X2
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REG_GP = REG_X3 // aka REG_SB
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REG_TP = REG_X4
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REG_T0 = REG_X5
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REG_T1 = REG_X6
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REG_T2 = REG_X7
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REG_S0 = REG_X8
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REG_S1 = REG_X9
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REG_A0 = REG_X10
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REG_A1 = REG_X11
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REG_A2 = REG_X12
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REG_A3 = REG_X13
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REG_A4 = REG_X14
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REG_A5 = REG_X15
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REG_A6 = REG_X16
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REG_A7 = REG_X17
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REG_S2 = REG_X18
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REG_S3 = REG_X19
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REG_S4 = REG_X20
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REG_S5 = REG_X21
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REG_S6 = REG_X22
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REG_S7 = REG_X23
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REG_S8 = REG_X24
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REG_S9 = REG_X25
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REG_S10 = REG_X26 // aka REG_CTXT
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REG_S11 = REG_X27 // aka REG_G
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REG_T3 = REG_X28
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REG_T4 = REG_X29
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REG_T5 = REG_X30
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REG_T6 = REG_X31 // aka REG_TMP
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// Go runtime register names.
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REG_CTXT = REG_S10 // Context for closures.
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REG_G = REG_S11 // G pointer.
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REG_LR = REG_RA // Link register.
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REG_TMP = REG_T6 // Reserved for assembler use.
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// ABI names for floating point registers.
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REG_FT0 = REG_F0
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REG_FT1 = REG_F1
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REG_FT2 = REG_F2
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REG_FT3 = REG_F3
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REG_FT4 = REG_F4
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REG_FT5 = REG_F5
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REG_FT6 = REG_F6
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REG_FT7 = REG_F7
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REG_FS0 = REG_F8
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REG_FS1 = REG_F9
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REG_FA0 = REG_F10
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REG_FA1 = REG_F11
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REG_FA2 = REG_F12
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REG_FA3 = REG_F13
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REG_FA4 = REG_F14
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REG_FA5 = REG_F15
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REG_FA6 = REG_F16
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REG_FA7 = REG_F17
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REG_FS2 = REG_F18
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REG_FS3 = REG_F19
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REG_FS4 = REG_F20
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REG_FS5 = REG_F21
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REG_FS6 = REG_F22
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REG_FS7 = REG_F23
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REG_FS8 = REG_F24
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REG_FS9 = REG_F25
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REG_FS10 = REG_F26
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REG_FS11 = REG_F27
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REG_FT8 = REG_F28
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REG_FT9 = REG_F29
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REG_FT10 = REG_F30
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REG_FT11 = REG_F31
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// Names generated by the SSA compiler.
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REGSP = REG_SP
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REGG = REG_G
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)
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// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers
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var RISCV64DWARFRegisters = map[int16]int16{
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// Integer Registers.
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REG_X0: 0,
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REG_X1: 1,
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REG_X2: 2,
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REG_X3: 3,
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REG_X4: 4,
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REG_X5: 5,
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REG_X6: 6,
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REG_X7: 7,
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REG_X8: 8,
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REG_X9: 9,
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REG_X10: 10,
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REG_X11: 11,
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REG_X12: 12,
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REG_X13: 13,
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REG_X14: 14,
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REG_X15: 15,
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REG_X16: 16,
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REG_X17: 17,
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REG_X18: 18,
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REG_X19: 19,
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REG_X20: 20,
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REG_X21: 21,
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REG_X22: 22,
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REG_X23: 23,
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REG_X24: 24,
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REG_X25: 25,
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REG_X26: 26,
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REG_X27: 27,
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REG_X28: 28,
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REG_X29: 29,
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REG_X30: 30,
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REG_X31: 31,
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// Floating-Point Registers.
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REG_F0: 32,
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REG_F1: 33,
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REG_F2: 34,
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REG_F3: 35,
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REG_F4: 36,
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REG_F5: 37,
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REG_F6: 38,
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REG_F7: 39,
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REG_F8: 40,
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REG_F9: 41,
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REG_F10: 42,
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REG_F11: 43,
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REG_F12: 44,
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REG_F13: 45,
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REG_F14: 46,
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REG_F15: 47,
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REG_F16: 48,
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REG_F17: 49,
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REG_F18: 50,
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REG_F19: 51,
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REG_F20: 52,
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REG_F21: 53,
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REG_F22: 54,
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REG_F23: 55,
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REG_F24: 56,
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REG_F25: 57,
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REG_F26: 58,
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REG_F27: 59,
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REG_F28: 60,
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REG_F29: 61,
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REG_F30: 62,
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REG_F31: 63,
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}
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// Prog.Mark flags.
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const (
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// USES_REG_TMP indicates that a machine instruction generated from the
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// corresponding *obj.Prog uses the temporary register.
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USES_REG_TMP = 1 << iota
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// NEED_JAL_RELOC is set on JAL instructions to indicate that a
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// R_RISCV_JAL relocation is needed.
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NEED_JAL_RELOC
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// NEED_CALL_RELOC is set on an AUIPC instruction to indicate that it
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// is the first instruction in an AUIPC + JAL pair that needs a
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// R_RISCV_CALL relocation.
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NEED_CALL_RELOC
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// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
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// it is the first instruction in an AUIPC + I-type pair that needs a
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// R_RISCV_PCREL_ITYPE relocation.
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NEED_PCREL_ITYPE_RELOC
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// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
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// it is the first instruction in an AUIPC + S-type pair that needs a
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// R_RISCV_PCREL_STYPE relocation.
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NEED_PCREL_STYPE_RELOC
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// NEED_GOT_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
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// it is the first instruction in an AUIPC + I-type pair that needs a
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// R_RISCV_GOT_PCREL_ITYPE relocation.
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NEED_GOT_PCREL_ITYPE_RELOC
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)
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// RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
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// at https://github.com/riscv/riscv-opcodes.
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//
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// As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
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//
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// See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/.
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//
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// If you modify this table, you MUST run 'go generate' to regenerate anames.go!
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const (
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//
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// Unprivileged ISA (version 20240411)
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//
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// 2.4: Integer Computational Instructions
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AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
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ASLTI
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ASLTIU
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AANDI
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AORI
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AXORI
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ASLLI
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ASRLI
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ASRAI
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ALUI
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AAUIPC
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AADD
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ASLT
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ASLTU
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AAND
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AOR
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AXOR
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ASLL
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ASRL
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ASUB
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ASRA
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// 2.5: Control Transfer Instructions
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AJAL
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AJALR
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ABEQ
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ABNE
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ABLT
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ABLTU
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ABGE
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ABGEU
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// 2.6: Load and Store Instructions
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ALW
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ALWU
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ALH
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ALHU
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ALB
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ALBU
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ASW
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ASH
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ASB
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// 2.7: Memory Ordering Instructions
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AFENCE
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// 4.2: Integer Computational Instructions (RV64I)
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AADDIW
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ASLLIW
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ASRLIW
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ASRAIW
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AADDW
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ASLLW
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ASRLW
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ASUBW
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ASRAW
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// 4.3: Load and Store Instructions (RV64I)
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ALD
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ASD
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// 7.1: CSR Instructions (Zicsr)
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ACSRRW
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ACSRRS
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ACSRRC
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ACSRRWI
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ACSRRSI
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ACSRRCI
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// 13.1: Multiplication Operations
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AMUL
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AMULH
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AMULHU
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AMULHSU
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AMULW
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// 13.2: Division Operations
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ADIV
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ADIVU
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AREM
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AREMU
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ADIVW
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ADIVUW
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AREMW
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AREMUW
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// 14.2: Load-Reserved/Store-Conditional Instructions (Zalrsc)
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ALRD
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ASCD
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ALRW
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ASCW
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// 14.4: Atomic Memory Operations (Zaamo)
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AAMOSWAPD
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AAMOADDD
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AAMOANDD
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AAMOORD
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AAMOXORD
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AAMOMAXD
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AAMOMAXUD
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AAMOMIND
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AAMOMINUD
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AAMOSWAPW
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AAMOADDW
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AAMOANDW
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AAMOORW
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AAMOXORW
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AAMOMAXW
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AAMOMAXUW
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AAMOMINW
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AAMOMINUW
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// 20.5: Single-Precision Load and Store Instructions
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AFLW
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AFSW
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// 20.6: Single-Precision Floating-Point Computational Instructions
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AFADDS
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AFSUBS
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AFMULS
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AFDIVS
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AFMINS
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AFMAXS
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AFSQRTS
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AFMADDS
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AFMSUBS
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AFNMADDS
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AFNMSUBS
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// 20.7: Single-Precision Floating-Point Conversion and Move Instructions
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AFCVTWS
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AFCVTLS
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AFCVTSW
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AFCVTSL
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AFCVTWUS
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AFCVTLUS
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AFCVTSWU
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AFCVTSLU
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AFSGNJS
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AFSGNJNS
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AFSGNJXS
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AFMVXS
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AFMVSX
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AFMVXW
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AFMVWX
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// 20.8: Single-Precision Floating-Point Compare Instructions
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AFEQS
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AFLTS
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AFLES
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// 20.9: Single-Precision Floating-Point Classify Instruction
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AFCLASSS
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// 21.3: Double-Precision Load and Store Instructions
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AFLD
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AFSD
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// 21.4: Double-Precision Floating-Point Computational Instructions
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AFADDD
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AFSUBD
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AFMULD
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AFDIVD
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AFMIND
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AFMAXD
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AFSQRTD
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AFMADDD
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AFMSUBD
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AFNMADDD
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AFNMSUBD
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// 21.5: Double-Precision Floating-Point Conversion and Move Instructions
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AFCVTWD
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AFCVTLD
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AFCVTDW
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AFCVTDL
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AFCVTWUD
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AFCVTLUD
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AFCVTDWU
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AFCVTDLU
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AFCVTSD
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AFCVTDS
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AFSGNJD
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AFSGNJND
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AFSGNJXD
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AFMVXD
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AFMVDX
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// 21.6: Double-Precision Floating-Point Compare Instructions
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AFEQD
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AFLTD
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AFLED
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// 21.7: Double-Precision Floating-Point Classify Instruction
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AFCLASSD
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// 22.1 Quad-Precision Load and Store Instructions
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AFLQ
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AFSQ
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// 22.2: Quad-Precision Computational Instructions
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AFADDQ
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AFSUBQ
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AFMULQ
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AFDIVQ
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AFMINQ
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AFMAXQ
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AFSQRTQ
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AFMADDQ
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AFMSUBQ
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AFNMADDQ
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AFNMSUBQ
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// 22.3: Quad-Precision Convert and Move Instructions
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AFCVTWQ
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AFCVTLQ
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AFCVTSQ
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|
AFCVTDQ
|
|
AFCVTQW
|
|
AFCVTQL
|
|
AFCVTQS
|
|
AFCVTQD
|
|
AFCVTWUQ
|
|
AFCVTLUQ
|
|
AFCVTQWU
|
|
AFCVTQLU
|
|
AFSGNJQ
|
|
AFSGNJNQ
|
|
AFSGNJXQ
|
|
|
|
// 22.4: Quad-Precision Floating-Point Compare Instructions
|
|
AFEQQ
|
|
AFLEQ
|
|
AFLTQ
|
|
|
|
// 22.5: Quad-Precision Floating-Point Classify Instruction
|
|
AFCLASSQ
|
|
|
|
//
|
|
// "C" Extension for Compressed Instructions
|
|
//
|
|
|
|
// 26.3.1: Compressed Stack-Pointer-Based Loads and Stores
|
|
ACLWSP
|
|
ACFLWSP
|
|
ACLDSP
|
|
ACFLDSP
|
|
ACSWSP
|
|
ACSDSP
|
|
ACFSWSP
|
|
ACFSDSP
|
|
|
|
// 26.3.2: Compressed Register-Based Loads and Stores
|
|
ACLW
|
|
ACLD
|
|
ACFLW
|
|
ACFLD
|
|
ACSW
|
|
ACSD
|
|
ACFSW
|
|
ACFSD
|
|
|
|
// 26.4: Compressed Control Transfer Instructions
|
|
ACJ
|
|
ACJR
|
|
ACJALR
|
|
ACBEQZ
|
|
ACBNEZ
|
|
|
|
// 26.5.1: Compressed Integer Constant-Generation Instructions
|
|
ACLI
|
|
ACLUI
|
|
ACADDI
|
|
ACADDIW
|
|
ACADDI16SP
|
|
ACADDI4SPN
|
|
ACSLLI
|
|
ACSRLI
|
|
ACSRAI
|
|
ACANDI
|
|
|
|
// 26.5.3: Compressed Integer Register-Register Operations
|
|
ACMV
|
|
ACADD
|
|
ACAND
|
|
ACOR
|
|
ACXOR
|
|
ACSUB
|
|
ACADDW
|
|
ACSUBW
|
|
|
|
// 26.5.5: Compressed NOP Instruction
|
|
ACNOP
|
|
|
|
// 26.5.6: Compressed Breakpoint Instruction
|
|
ACEBREAK
|
|
|
|
//
|
|
// "B" Extension for Bit Manipulation, Version 1.0.0
|
|
//
|
|
|
|
// 28.4.1: Address Generation Instructions (Zba)
|
|
AADDUW
|
|
ASH1ADD
|
|
ASH1ADDUW
|
|
ASH2ADD
|
|
ASH2ADDUW
|
|
ASH3ADD
|
|
ASH3ADDUW
|
|
ASLLIUW
|
|
|
|
// 28.4.2: Basic Bit Manipulation (Zbb)
|
|
AANDN
|
|
AORN
|
|
AXNOR
|
|
ACLZ
|
|
ACLZW
|
|
ACTZ
|
|
ACTZW
|
|
ACPOP
|
|
ACPOPW
|
|
AMAX
|
|
AMAXU
|
|
AMIN
|
|
AMINU
|
|
ASEXTB
|
|
ASEXTH
|
|
AZEXTH
|
|
|
|
// 28.4.3: Bitwise Rotation (Zbb)
|
|
AROL
|
|
AROLW
|
|
AROR
|
|
ARORI
|
|
ARORIW
|
|
ARORW
|
|
AORCB
|
|
AREV8
|
|
|
|
// 28.4.4: Single-bit Instructions (Zbs)
|
|
ABCLR
|
|
ABCLRI
|
|
ABEXT
|
|
ABEXTI
|
|
ABINV
|
|
ABINVI
|
|
ABSET
|
|
ABSETI
|
|
|
|
//
|
|
// "V" Standard Extension for Vector Operations, Version 1.0
|
|
//
|
|
|
|
// 31.6: Configuration-Setting Instructions
|
|
AVSETVLI
|
|
AVSETIVLI
|
|
AVSETVL
|
|
|
|
// 31.7.4: Vector Unit-Stride Instructions
|
|
AVLE8V
|
|
AVLE16V
|
|
AVLE32V
|
|
AVLE64V
|
|
AVSE8V
|
|
AVSE16V
|
|
AVSE32V
|
|
AVSE64V
|
|
AVLMV
|
|
AVSMV
|
|
|
|
// 31.7.5: Vector Strided Instructions
|
|
AVLSE8V
|
|
AVLSE16V
|
|
AVLSE32V
|
|
AVLSE64V
|
|
AVSSE8V
|
|
AVSSE16V
|
|
AVSSE32V
|
|
AVSSE64V
|
|
|
|
// 31.7.6: Vector Indexed Instructions
|
|
AVLUXEI8V
|
|
AVLUXEI16V
|
|
AVLUXEI32V
|
|
AVLUXEI64V
|
|
AVLOXEI8V
|
|
AVLOXEI16V
|
|
AVLOXEI32V
|
|
AVLOXEI64V
|
|
AVSUXEI8V
|
|
AVSUXEI16V
|
|
AVSUXEI32V
|
|
AVSUXEI64V
|
|
AVSOXEI8V
|
|
AVSOXEI16V
|
|
AVSOXEI32V
|
|
AVSOXEI64V
|
|
|
|
// 31.7.7: Unit-stride Fault-Only-First Loads
|
|
AVLE8FFV
|
|
AVLE16FFV
|
|
AVLE32FFV
|
|
AVLE64FFV
|
|
|
|
// 31.7.8. Vector Load/Store Segment Instructions
|
|
|
|
// 31.7.8.1. Vector Unit-Stride Segment Loads and Stores
|
|
AVLSEG2E8V
|
|
AVLSEG3E8V
|
|
AVLSEG4E8V
|
|
AVLSEG5E8V
|
|
AVLSEG6E8V
|
|
AVLSEG7E8V
|
|
AVLSEG8E8V
|
|
AVLSEG2E16V
|
|
AVLSEG3E16V
|
|
AVLSEG4E16V
|
|
AVLSEG5E16V
|
|
AVLSEG6E16V
|
|
AVLSEG7E16V
|
|
AVLSEG8E16V
|
|
AVLSEG2E32V
|
|
AVLSEG3E32V
|
|
AVLSEG4E32V
|
|
AVLSEG5E32V
|
|
AVLSEG6E32V
|
|
AVLSEG7E32V
|
|
AVLSEG8E32V
|
|
AVLSEG2E64V
|
|
AVLSEG3E64V
|
|
AVLSEG4E64V
|
|
AVLSEG5E64V
|
|
AVLSEG6E64V
|
|
AVLSEG7E64V
|
|
AVLSEG8E64V
|
|
|
|
AVSSEG2E8V
|
|
AVSSEG3E8V
|
|
AVSSEG4E8V
|
|
AVSSEG5E8V
|
|
AVSSEG6E8V
|
|
AVSSEG7E8V
|
|
AVSSEG8E8V
|
|
AVSSEG2E16V
|
|
AVSSEG3E16V
|
|
AVSSEG4E16V
|
|
AVSSEG5E16V
|
|
AVSSEG6E16V
|
|
AVSSEG7E16V
|
|
AVSSEG8E16V
|
|
AVSSEG2E32V
|
|
AVSSEG3E32V
|
|
AVSSEG4E32V
|
|
AVSSEG5E32V
|
|
AVSSEG6E32V
|
|
AVSSEG7E32V
|
|
AVSSEG8E32V
|
|
AVSSEG2E64V
|
|
AVSSEG3E64V
|
|
AVSSEG4E64V
|
|
AVSSEG5E64V
|
|
AVSSEG6E64V
|
|
AVSSEG7E64V
|
|
AVSSEG8E64V
|
|
|
|
AVLSEG2E8FFV
|
|
AVLSEG3E8FFV
|
|
AVLSEG4E8FFV
|
|
AVLSEG5E8FFV
|
|
AVLSEG6E8FFV
|
|
AVLSEG7E8FFV
|
|
AVLSEG8E8FFV
|
|
AVLSEG2E16FFV
|
|
AVLSEG3E16FFV
|
|
AVLSEG4E16FFV
|
|
AVLSEG5E16FFV
|
|
AVLSEG6E16FFV
|
|
AVLSEG7E16FFV
|
|
AVLSEG8E16FFV
|
|
AVLSEG2E32FFV
|
|
AVLSEG3E32FFV
|
|
AVLSEG4E32FFV
|
|
AVLSEG5E32FFV
|
|
AVLSEG6E32FFV
|
|
AVLSEG7E32FFV
|
|
AVLSEG8E32FFV
|
|
AVLSEG2E64FFV
|
|
AVLSEG3E64FFV
|
|
AVLSEG4E64FFV
|
|
AVLSEG5E64FFV
|
|
AVLSEG6E64FFV
|
|
AVLSEG7E64FFV
|
|
AVLSEG8E64FFV
|
|
|
|
// 31.7.8.2. Vector Strided Segment Loads and Stores
|
|
AVLSSEG2E8V
|
|
AVLSSEG3E8V
|
|
AVLSSEG4E8V
|
|
AVLSSEG5E8V
|
|
AVLSSEG6E8V
|
|
AVLSSEG7E8V
|
|
AVLSSEG8E8V
|
|
AVLSSEG2E16V
|
|
AVLSSEG3E16V
|
|
AVLSSEG4E16V
|
|
AVLSSEG5E16V
|
|
AVLSSEG6E16V
|
|
AVLSSEG7E16V
|
|
AVLSSEG8E16V
|
|
AVLSSEG2E32V
|
|
AVLSSEG3E32V
|
|
AVLSSEG4E32V
|
|
AVLSSEG5E32V
|
|
AVLSSEG6E32V
|
|
AVLSSEG7E32V
|
|
AVLSSEG8E32V
|
|
AVLSSEG2E64V
|
|
AVLSSEG3E64V
|
|
AVLSSEG4E64V
|
|
AVLSSEG5E64V
|
|
AVLSSEG6E64V
|
|
AVLSSEG7E64V
|
|
AVLSSEG8E64V
|
|
|
|
AVSSSEG2E8V
|
|
AVSSSEG3E8V
|
|
AVSSSEG4E8V
|
|
AVSSSEG5E8V
|
|
AVSSSEG6E8V
|
|
AVSSSEG7E8V
|
|
AVSSSEG8E8V
|
|
AVSSSEG2E16V
|
|
AVSSSEG3E16V
|
|
AVSSSEG4E16V
|
|
AVSSSEG5E16V
|
|
AVSSSEG6E16V
|
|
AVSSSEG7E16V
|
|
AVSSSEG8E16V
|
|
AVSSSEG2E32V
|
|
AVSSSEG3E32V
|
|
AVSSSEG4E32V
|
|
AVSSSEG5E32V
|
|
AVSSSEG6E32V
|
|
AVSSSEG7E32V
|
|
AVSSSEG8E32V
|
|
AVSSSEG2E64V
|
|
AVSSSEG3E64V
|
|
AVSSSEG4E64V
|
|
AVSSSEG5E64V
|
|
AVSSSEG6E64V
|
|
AVSSSEG7E64V
|
|
AVSSSEG8E64V
|
|
|
|
// 31.7.8.3. Vector Indexed Segment Loads and Stores
|
|
AVLOXSEG2EI8V
|
|
AVLOXSEG3EI8V
|
|
AVLOXSEG4EI8V
|
|
AVLOXSEG5EI8V
|
|
AVLOXSEG6EI8V
|
|
AVLOXSEG7EI8V
|
|
AVLOXSEG8EI8V
|
|
AVLOXSEG2EI16V
|
|
AVLOXSEG3EI16V
|
|
AVLOXSEG4EI16V
|
|
AVLOXSEG5EI16V
|
|
AVLOXSEG6EI16V
|
|
AVLOXSEG7EI16V
|
|
AVLOXSEG8EI16V
|
|
AVLOXSEG2EI32V
|
|
AVLOXSEG3EI32V
|
|
AVLOXSEG4EI32V
|
|
AVLOXSEG5EI32V
|
|
AVLOXSEG6EI32V
|
|
AVLOXSEG7EI32V
|
|
AVLOXSEG8EI32V
|
|
AVLOXSEG2EI64V
|
|
AVLOXSEG3EI64V
|
|
AVLOXSEG4EI64V
|
|
AVLOXSEG5EI64V
|
|
AVLOXSEG6EI64V
|
|
AVLOXSEG7EI64V
|
|
AVLOXSEG8EI64V
|
|
|
|
AVSOXSEG2EI8V
|
|
AVSOXSEG3EI8V
|
|
AVSOXSEG4EI8V
|
|
AVSOXSEG5EI8V
|
|
AVSOXSEG6EI8V
|
|
AVSOXSEG7EI8V
|
|
AVSOXSEG8EI8V
|
|
AVSOXSEG2EI16V
|
|
AVSOXSEG3EI16V
|
|
AVSOXSEG4EI16V
|
|
AVSOXSEG5EI16V
|
|
AVSOXSEG6EI16V
|
|
AVSOXSEG7EI16V
|
|
AVSOXSEG8EI16V
|
|
AVSOXSEG2EI32V
|
|
AVSOXSEG3EI32V
|
|
AVSOXSEG4EI32V
|
|
AVSOXSEG5EI32V
|
|
AVSOXSEG6EI32V
|
|
AVSOXSEG7EI32V
|
|
AVSOXSEG8EI32V
|
|
AVSOXSEG2EI64V
|
|
AVSOXSEG3EI64V
|
|
AVSOXSEG4EI64V
|
|
AVSOXSEG5EI64V
|
|
AVSOXSEG6EI64V
|
|
AVSOXSEG7EI64V
|
|
AVSOXSEG8EI64V
|
|
|
|
AVLUXSEG2EI8V
|
|
AVLUXSEG3EI8V
|
|
AVLUXSEG4EI8V
|
|
AVLUXSEG5EI8V
|
|
AVLUXSEG6EI8V
|
|
AVLUXSEG7EI8V
|
|
AVLUXSEG8EI8V
|
|
AVLUXSEG2EI16V
|
|
AVLUXSEG3EI16V
|
|
AVLUXSEG4EI16V
|
|
AVLUXSEG5EI16V
|
|
AVLUXSEG6EI16V
|
|
AVLUXSEG7EI16V
|
|
AVLUXSEG8EI16V
|
|
AVLUXSEG2EI32V
|
|
AVLUXSEG3EI32V
|
|
AVLUXSEG4EI32V
|
|
AVLUXSEG5EI32V
|
|
AVLUXSEG6EI32V
|
|
AVLUXSEG7EI32V
|
|
AVLUXSEG8EI32V
|
|
AVLUXSEG2EI64V
|
|
AVLUXSEG3EI64V
|
|
AVLUXSEG4EI64V
|
|
AVLUXSEG5EI64V
|
|
AVLUXSEG6EI64V
|
|
AVLUXSEG7EI64V
|
|
AVLUXSEG8EI64V
|
|
|
|
AVSUXSEG2EI8V
|
|
AVSUXSEG3EI8V
|
|
AVSUXSEG4EI8V
|
|
AVSUXSEG5EI8V
|
|
AVSUXSEG6EI8V
|
|
AVSUXSEG7EI8V
|
|
AVSUXSEG8EI8V
|
|
AVSUXSEG2EI16V
|
|
AVSUXSEG3EI16V
|
|
AVSUXSEG4EI16V
|
|
AVSUXSEG5EI16V
|
|
AVSUXSEG6EI16V
|
|
AVSUXSEG7EI16V
|
|
AVSUXSEG8EI16V
|
|
AVSUXSEG2EI32V
|
|
AVSUXSEG3EI32V
|
|
AVSUXSEG4EI32V
|
|
AVSUXSEG5EI32V
|
|
AVSUXSEG6EI32V
|
|
AVSUXSEG7EI32V
|
|
AVSUXSEG8EI32V
|
|
AVSUXSEG2EI64V
|
|
AVSUXSEG3EI64V
|
|
AVSUXSEG4EI64V
|
|
AVSUXSEG5EI64V
|
|
AVSUXSEG6EI64V
|
|
AVSUXSEG7EI64V
|
|
AVSUXSEG8EI64V
|
|
|
|
// 31.7.9: Vector Load/Store Whole Register Instructions
|
|
AVL1RE8V
|
|
AVL1RE16V
|
|
AVL1RE32V
|
|
AVL1RE64V
|
|
AVL2RE8V
|
|
AVL2RE16V
|
|
AVL2RE32V
|
|
AVL2RE64V
|
|
AVL4RE8V
|
|
AVL4RE16V
|
|
AVL4RE32V
|
|
AVL4RE64V
|
|
AVL8RE8V
|
|
AVL8RE16V
|
|
AVL8RE32V
|
|
AVL8RE64V
|
|
AVS1RV
|
|
AVS2RV
|
|
AVS4RV
|
|
AVS8RV
|
|
|
|
// 31.11.1: Vector Single-Width Integer Add and Subtract
|
|
AVADDVV
|
|
AVADDVX
|
|
AVADDVI
|
|
AVSUBVV
|
|
AVSUBVX
|
|
AVRSUBVX
|
|
AVRSUBVI
|
|
|
|
// 31.11.2: Vector Widening Integer Add/Subtract
|
|
AVWADDUVV
|
|
AVWADDUVX
|
|
AVWSUBUVV
|
|
AVWSUBUVX
|
|
AVWADDVV
|
|
AVWADDVX
|
|
AVWSUBVV
|
|
AVWSUBVX
|
|
AVWADDUWV
|
|
AVWADDUWX
|
|
AVWSUBUWV
|
|
AVWSUBUWX
|
|
AVWADDWV
|
|
AVWADDWX
|
|
AVWSUBWV
|
|
AVWSUBWX
|
|
|
|
// 31.11.3: Vector Integer Extension
|
|
AVZEXTVF2
|
|
AVSEXTVF2
|
|
AVZEXTVF4
|
|
AVSEXTVF4
|
|
AVZEXTVF8
|
|
AVSEXTVF8
|
|
|
|
// 31.11.4: Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
|
|
AVADCVVM
|
|
AVADCVXM
|
|
AVADCVIM
|
|
AVMADCVVM
|
|
AVMADCVXM
|
|
AVMADCVIM
|
|
AVMADCVV
|
|
AVMADCVX
|
|
AVMADCVI
|
|
AVSBCVVM
|
|
AVSBCVXM
|
|
AVMSBCVVM
|
|
AVMSBCVXM
|
|
AVMSBCVV
|
|
AVMSBCVX
|
|
|
|
// 31.11.5: Vector Bitwise Logical Instructions
|
|
AVANDVV
|
|
AVANDVX
|
|
AVANDVI
|
|
AVORVV
|
|
AVORVX
|
|
AVORVI
|
|
AVXORVV
|
|
AVXORVX
|
|
AVXORVI
|
|
|
|
// 31.11.6: Vector Single-Width Shift Instructions
|
|
AVSLLVV
|
|
AVSLLVX
|
|
AVSLLVI
|
|
AVSRLVV
|
|
AVSRLVX
|
|
AVSRLVI
|
|
AVSRAVV
|
|
AVSRAVX
|
|
AVSRAVI
|
|
|
|
// 31.11.7: Vector Narrowing Integer Right Shift Instructions
|
|
AVNSRLWV
|
|
AVNSRLWX
|
|
AVNSRLWI
|
|
AVNSRAWV
|
|
AVNSRAWX
|
|
AVNSRAWI
|
|
|
|
// 31.11.8: Vector Integer Compare Instructions
|
|
AVMSEQVV
|
|
AVMSEQVX
|
|
AVMSEQVI
|
|
AVMSNEVV
|
|
AVMSNEVX
|
|
AVMSNEVI
|
|
AVMSLTUVV
|
|
AVMSLTUVX
|
|
AVMSLTVV
|
|
AVMSLTVX
|
|
AVMSLEUVV
|
|
AVMSLEUVX
|
|
AVMSLEUVI
|
|
AVMSLEVV
|
|
AVMSLEVX
|
|
AVMSLEVI
|
|
AVMSGTUVX
|
|
AVMSGTUVI
|
|
AVMSGTVX
|
|
AVMSGTVI
|
|
|
|
// 31.11.9: Vector Integer Min/Max Instructions
|
|
AVMINUVV
|
|
AVMINUVX
|
|
AVMINVV
|
|
AVMINVX
|
|
AVMAXUVV
|
|
AVMAXUVX
|
|
AVMAXVV
|
|
AVMAXVX
|
|
|
|
// 31.11.10: Vector Single-Width Integer Multiply Instructions
|
|
AVMULVV
|
|
AVMULVX
|
|
AVMULHVV
|
|
AVMULHVX
|
|
AVMULHUVV
|
|
AVMULHUVX
|
|
AVMULHSUVV
|
|
AVMULHSUVX
|
|
|
|
// 31.11.11: Vector Integer Divide Instructions
|
|
AVDIVUVV
|
|
AVDIVUVX
|
|
AVDIVVV
|
|
AVDIVVX
|
|
AVREMUVV
|
|
AVREMUVX
|
|
AVREMVV
|
|
AVREMVX
|
|
|
|
// 31.11.12: Vector Widening Integer Multiply Instructions
|
|
AVWMULVV
|
|
AVWMULVX
|
|
AVWMULUVV
|
|
AVWMULUVX
|
|
AVWMULSUVV
|
|
AVWMULSUVX
|
|
|
|
// 31.11.13: Vector Single-Width Integer Multiply-Add Instructions
|
|
AVMACCVV
|
|
AVMACCVX
|
|
AVNMSACVV
|
|
AVNMSACVX
|
|
AVMADDVV
|
|
AVMADDVX
|
|
AVNMSUBVV
|
|
AVNMSUBVX
|
|
|
|
// 31.11.14: Vector Widening Integer Multiply-Add Instructions
|
|
AVWMACCUVV
|
|
AVWMACCUVX
|
|
AVWMACCVV
|
|
AVWMACCVX
|
|
AVWMACCSUVV
|
|
AVWMACCSUVX
|
|
AVWMACCUSVX
|
|
|
|
// 31.11.15: Vector Integer Merge Instructions
|
|
AVMERGEVVM
|
|
AVMERGEVXM
|
|
AVMERGEVIM
|
|
|
|
// 31.11.16: Vector Integer Move Instructions
|
|
AVMVVV
|
|
AVMVVX
|
|
AVMVVI
|
|
|
|
// 31.12.1: Vector Single-Width Saturating Add and Subtract
|
|
AVSADDUVV
|
|
AVSADDUVX
|
|
AVSADDUVI
|
|
AVSADDVV
|
|
AVSADDVX
|
|
AVSADDVI
|
|
AVSSUBUVV
|
|
AVSSUBUVX
|
|
AVSSUBVV
|
|
AVSSUBVX
|
|
|
|
// 31.12.2: Vector Single-Width Averaging Add and Subtract
|
|
AVAADDUVV
|
|
AVAADDUVX
|
|
AVAADDVV
|
|
AVAADDVX
|
|
AVASUBUVV
|
|
AVASUBUVX
|
|
AVASUBVV
|
|
AVASUBVX
|
|
|
|
// 31.12.3: Vector Single-Width Fractional Multiply with Rounding and Saturation
|
|
AVSMULVV
|
|
AVSMULVX
|
|
|
|
// 31.12.4: Vector Single-Width Scaling Shift Instructions
|
|
AVSSRLVV
|
|
AVSSRLVX
|
|
AVSSRLVI
|
|
AVSSRAVV
|
|
AVSSRAVX
|
|
AVSSRAVI
|
|
|
|
// 31.12.5: Vector Narrowing Fixed-Point Clip Instructions
|
|
AVNCLIPUWV
|
|
AVNCLIPUWX
|
|
AVNCLIPUWI
|
|
AVNCLIPWV
|
|
AVNCLIPWX
|
|
AVNCLIPWI
|
|
|
|
// 31.13.2: Vector Single-Width Floating-Point Add/Subtract Instructions
|
|
AVFADDVV
|
|
AVFADDVF
|
|
AVFSUBVV
|
|
AVFSUBVF
|
|
AVFRSUBVF
|
|
|
|
// 31.13.3: Vector Widening Floating-Point Add/Subtract Instructions
|
|
AVFWADDVV
|
|
AVFWADDVF
|
|
AVFWSUBVV
|
|
AVFWSUBVF
|
|
AVFWADDWV
|
|
AVFWADDWF
|
|
AVFWSUBWV
|
|
AVFWSUBWF
|
|
|
|
// 31.13.4: Vector Single-Width Floating-Point Multiply/Divide Instructions
|
|
AVFMULVV
|
|
AVFMULVF
|
|
AVFDIVVV
|
|
AVFDIVVF
|
|
AVFRDIVVF
|
|
|
|
// 31.13.5: Vector Widening Floating-Point Multiply
|
|
AVFWMULVV
|
|
AVFWMULVF
|
|
|
|
// 31.13.6: Vector Single-Width Floating-Point Fused Multiply-Add Instructions
|
|
AVFMACCVV
|
|
AVFMACCVF
|
|
AVFNMACCVV
|
|
AVFNMACCVF
|
|
AVFMSACVV
|
|
AVFMSACVF
|
|
AVFNMSACVV
|
|
AVFNMSACVF
|
|
AVFMADDVV
|
|
AVFMADDVF
|
|
AVFNMADDVV
|
|
AVFNMADDVF
|
|
AVFMSUBVV
|
|
AVFMSUBVF
|
|
AVFNMSUBVV
|
|
AVFNMSUBVF
|
|
|
|
// 31.13.7: Vector Widening Floating-Point Fused Multiply-Add Instructions
|
|
AVFWMACCVV
|
|
AVFWMACCVF
|
|
AVFWNMACCVV
|
|
AVFWNMACCVF
|
|
AVFWMSACVV
|
|
AVFWMSACVF
|
|
AVFWNMSACVV
|
|
AVFWNMSACVF
|
|
|
|
// 31.13.8: Vector Floating-Point Square-Root Instruction
|
|
AVFSQRTV
|
|
|
|
// 31.13.9: Vector Floating-Point Reciprocal Square-Root Estimate Instruction
|
|
AVFRSQRT7V
|
|
|
|
// 31.13.10: Vector Floating-Point Reciprocal Estimate Instruction
|
|
AVFREC7V
|
|
|
|
// 31.13.11: Vector Floating-Point MIN/MAX Instructions
|
|
AVFMINVV
|
|
AVFMINVF
|
|
AVFMAXVV
|
|
AVFMAXVF
|
|
|
|
// 31.13.12: Vector Floating-Point Sign-Injection Instructions
|
|
AVFSGNJVV
|
|
AVFSGNJVF
|
|
AVFSGNJNVV
|
|
AVFSGNJNVF
|
|
AVFSGNJXVV
|
|
AVFSGNJXVF
|
|
|
|
// 31.13.13: Vector Floating-Point Compare Instructions
|
|
AVMFEQVV
|
|
AVMFEQVF
|
|
AVMFNEVV
|
|
AVMFNEVF
|
|
AVMFLTVV
|
|
AVMFLTVF
|
|
AVMFLEVV
|
|
AVMFLEVF
|
|
AVMFGTVF
|
|
AVMFGEVF
|
|
|
|
// 31.13.14: Vector Floating-Point Classify Instruction
|
|
AVFCLASSV
|
|
|
|
// 31.13.15: Vector Floating-Point Merge Instruction
|
|
AVFMERGEVFM
|
|
|
|
// 31.13.16: Vector Floating-Point Move Instruction
|
|
AVFMVVF
|
|
|
|
// 31.13.17: Single-Width Floating-Point/Integer Type-Convert Instructions
|
|
AVFCVTXUFV
|
|
AVFCVTXFV
|
|
AVFCVTRTZXUFV
|
|
AVFCVTRTZXFV
|
|
AVFCVTFXUV
|
|
AVFCVTFXV
|
|
|
|
// 31.13.18: Widening Floating-Point/Integer Type-Convert Instructions
|
|
AVFWCVTXUFV
|
|
AVFWCVTXFV
|
|
AVFWCVTRTZXUFV
|
|
AVFWCVTRTZXFV
|
|
AVFWCVTFXUV
|
|
AVFWCVTFXV
|
|
AVFWCVTFFV
|
|
|
|
// 31.13.19: Narrowing Floating-Point/Integer Type-Convert Instructions
|
|
AVFNCVTXUFW
|
|
AVFNCVTXFW
|
|
AVFNCVTRTZXUFW
|
|
AVFNCVTRTZXFW
|
|
AVFNCVTFXUW
|
|
AVFNCVTFXW
|
|
AVFNCVTFFW
|
|
AVFNCVTRODFFW
|
|
|
|
// 31.14.1: Vector Single-Width Integer Reduction Instructions
|
|
AVREDSUMVS
|
|
AVREDMAXUVS
|
|
AVREDMAXVS
|
|
AVREDMINUVS
|
|
AVREDMINVS
|
|
AVREDANDVS
|
|
AVREDORVS
|
|
AVREDXORVS
|
|
|
|
// 31.14.2: Vector Widening Integer Reduction Instructions
|
|
AVWREDSUMUVS
|
|
AVWREDSUMVS
|
|
|
|
// 31.14.3: Vector Single-Width Floating-Point Reduction Instructions
|
|
AVFREDOSUMVS
|
|
AVFREDUSUMVS
|
|
AVFREDMAXVS
|
|
AVFREDMINVS
|
|
|
|
// 31.14.4: Vector Widening Floating-Point Reduction Instructions
|
|
AVFWREDOSUMVS
|
|
AVFWREDUSUMVS
|
|
|
|
// 31.15: Vector Mask Instructions
|
|
AVMANDMM
|
|
AVMNANDMM
|
|
AVMANDNMM
|
|
AVMXORMM
|
|
AVMORMM
|
|
AVMNORMM
|
|
AVMORNMM
|
|
AVMXNORMM
|
|
AVCPOPM
|
|
AVFIRSTM
|
|
AVMSBFM
|
|
AVMSIFM
|
|
AVMSOFM
|
|
AVIOTAM
|
|
AVIDV
|
|
|
|
// 31.16.1: Integer Scalar Move Instructions
|
|
AVMVXS
|
|
AVMVSX
|
|
|
|
// 31.16.2: Floating-Point Scalar Move Instructions
|
|
AVFMVFS
|
|
AVFMVSF
|
|
|
|
// 31.16.3: Vector Slide Instructions
|
|
AVSLIDEUPVX
|
|
AVSLIDEUPVI
|
|
AVSLIDEDOWNVX
|
|
AVSLIDEDOWNVI
|
|
AVSLIDE1UPVX
|
|
AVFSLIDE1UPVF
|
|
AVSLIDE1DOWNVX
|
|
AVFSLIDE1DOWNVF
|
|
|
|
// 31.16.4: Vector Register Gather Instructions
|
|
AVRGATHERVV
|
|
AVRGATHEREI16VV
|
|
AVRGATHERVX
|
|
AVRGATHERVI
|
|
|
|
// 31.16.5: Vector Compress Instruction
|
|
AVCOMPRESSVM
|
|
|
|
// 31.16.6: Whole Vector Register Move
|
|
AVMV1RV
|
|
AVMV2RV
|
|
AVMV4RV
|
|
AVMV8RV
|
|
|
|
//
|
|
// Privileged ISA (version 20240411)
|
|
//
|
|
|
|
// 3.3.1: Environment Call and Breakpoint
|
|
AECALL
|
|
ASCALL
|
|
AEBREAK
|
|
ASBREAK
|
|
|
|
// 3.3.2: Trap-Return Instructions
|
|
AMRET
|
|
ASRET
|
|
ADRET
|
|
|
|
// 3.3.3: Wait for Interrupt
|
|
AWFI
|
|
|
|
// 10.2: Supervisor Memory-Management Fence Instruction
|
|
ASFENCEVMA
|
|
|
|
// The escape hatch. Inserts a single 32-bit word.
|
|
AWORD
|
|
|
|
// Pseudo-instructions. These get translated by the assembler into other
|
|
// instructions, based on their operands.
|
|
ABEQZ
|
|
ABGEZ
|
|
ABGT
|
|
ABGTU
|
|
ABGTZ
|
|
ABLE
|
|
ABLEU
|
|
ABLEZ
|
|
ABLTZ
|
|
ABNEZ
|
|
AFABSD
|
|
AFABSS
|
|
AFNED
|
|
AFNEGD
|
|
AFNEGS
|
|
AFNES
|
|
AMOV
|
|
AMOVB
|
|
AMOVBU
|
|
AMOVD
|
|
AMOVF
|
|
AMOVH
|
|
AMOVHU
|
|
AMOVW
|
|
AMOVWU
|
|
ANEG
|
|
ANEGW
|
|
ANOT
|
|
ARDCYCLE
|
|
ARDINSTRET
|
|
ARDTIME
|
|
ASEQZ
|
|
ASNEZ
|
|
AVFABSV
|
|
AVFNEGV
|
|
AVL1RV
|
|
AVL2RV
|
|
AVL4RV
|
|
AVL8RV
|
|
AVMCLRM
|
|
AVMFGEVV
|
|
AVMFGTVV
|
|
AVMMVM
|
|
AVMNOTM
|
|
AVMSETM
|
|
AVMSGEUVI
|
|
AVMSGEUVV
|
|
AVMSGEVI
|
|
AVMSGEVV
|
|
AVMSGTUVV
|
|
AVMSGTVV
|
|
AVMSLTUVI
|
|
AVMSLTVI
|
|
AVNCVTXXW
|
|
AVNEGV
|
|
AVNOTV
|
|
AVWCVTUXXV
|
|
AVWCVTXXV
|
|
|
|
// End marker
|
|
ALAST
|
|
)
|
|
|
|
// opSuffix encoding to uint8 which fit into p.Scond
|
|
var rmSuffixSet = map[string]uint8{
|
|
"RNE": RM_RNE,
|
|
"RTZ": RM_RTZ,
|
|
"RDN": RM_RDN,
|
|
"RUP": RM_RUP,
|
|
"RMM": RM_RMM,
|
|
}
|
|
|
|
const rmSuffixBit uint8 = 1 << 7
|
|
|
|
func rmSuffixEncode(s string) (uint8, error) {
|
|
if s == "" {
|
|
return 0, errors.New("empty suffix")
|
|
}
|
|
enc, ok := rmSuffixSet[s]
|
|
if !ok {
|
|
return 0, fmt.Errorf("invalid encoding for unknown suffix:%q", s)
|
|
}
|
|
return enc | rmSuffixBit, nil
|
|
}
|
|
|
|
func rmSuffixString(u uint8) (string, error) {
|
|
if u&rmSuffixBit == 0 {
|
|
return "", fmt.Errorf("invalid suffix, require round mode bit:%x", u)
|
|
}
|
|
|
|
u &^= rmSuffixBit
|
|
for k, v := range rmSuffixSet {
|
|
if v == u {
|
|
return k, nil
|
|
}
|
|
}
|
|
return "", fmt.Errorf("unknown suffix:%x", u)
|
|
}
|
|
|
|
const (
|
|
RM_RNE uint8 = iota // Round to Nearest, ties to Even
|
|
RM_RTZ // Round towards Zero
|
|
RM_RDN // Round Down
|
|
RM_RUP // Round Up
|
|
RM_RMM // Round to Nearest, ties to Max Magnitude
|
|
)
|
|
|
|
type SpecialOperand int
|
|
|
|
const (
|
|
SPOP_BEGIN SpecialOperand = obj.SpecialOperandRISCVBase
|
|
SPOP_RVV_BEGIN
|
|
|
|
// Vector mask policy.
|
|
SPOP_MA SpecialOperand = obj.SpecialOperandRISCVBase + iota - 2
|
|
SPOP_MU
|
|
|
|
// Vector tail policy.
|
|
SPOP_TA
|
|
SPOP_TU
|
|
|
|
// Vector register group multiplier (VLMUL).
|
|
SPOP_M1
|
|
SPOP_M2
|
|
SPOP_M4
|
|
SPOP_M8
|
|
SPOP_MF2
|
|
SPOP_MF4
|
|
SPOP_MF8
|
|
|
|
// Vector selected element width (VSEW).
|
|
SPOP_E8
|
|
SPOP_E16
|
|
SPOP_E32
|
|
SPOP_E64
|
|
SPOP_RVV_END
|
|
|
|
// CSR names. 4096 special operands are reserved for RISC-V CSR names.
|
|
SPOP_CSR_BEGIN = SPOP_RVV_END
|
|
SPOP_CSR_END = SPOP_CSR_BEGIN + 4096
|
|
|
|
SPOP_END = SPOP_CSR_END + 1
|
|
)
|
|
|
|
var specialOperands = map[SpecialOperand]struct {
|
|
encoding uint32
|
|
name string
|
|
}{
|
|
SPOP_MA: {encoding: 1, name: "MA"},
|
|
SPOP_MU: {encoding: 0, name: "MU"},
|
|
|
|
SPOP_TA: {encoding: 1, name: "TA"},
|
|
SPOP_TU: {encoding: 0, name: "TU"},
|
|
|
|
SPOP_M1: {encoding: 0, name: "M1"},
|
|
SPOP_M2: {encoding: 1, name: "M2"},
|
|
SPOP_M4: {encoding: 2, name: "M4"},
|
|
SPOP_M8: {encoding: 3, name: "M8"},
|
|
SPOP_MF8: {encoding: 5, name: "MF8"},
|
|
SPOP_MF4: {encoding: 6, name: "MF4"},
|
|
SPOP_MF2: {encoding: 7, name: "MF2"},
|
|
|
|
SPOP_E8: {encoding: 0, name: "E8"},
|
|
SPOP_E16: {encoding: 1, name: "E16"},
|
|
SPOP_E32: {encoding: 2, name: "E32"},
|
|
SPOP_E64: {encoding: 3, name: "E64"},
|
|
}
|
|
|
|
func (so SpecialOperand) encode() uint32 {
|
|
switch {
|
|
case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
|
|
op, ok := specialOperands[so]
|
|
if ok {
|
|
return op.encoding
|
|
}
|
|
case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
|
|
csrNum := uint16(so - SPOP_CSR_BEGIN)
|
|
if _, ok := csrs[csrNum]; ok {
|
|
return uint32(csrNum)
|
|
}
|
|
}
|
|
return 0
|
|
}
|
|
|
|
// String returns the textual representation of a SpecialOperand.
|
|
func (so SpecialOperand) String() string {
|
|
switch {
|
|
case so >= SPOP_RVV_BEGIN && so < SPOP_RVV_END:
|
|
op, ok := specialOperands[so]
|
|
if ok {
|
|
return op.name
|
|
}
|
|
case so >= SPOP_CSR_BEGIN && so < SPOP_CSR_END:
|
|
if csrName, ok := csrs[uint16(so-SPOP_CSR_BEGIN)]; ok {
|
|
return csrName
|
|
}
|
|
}
|
|
return ""
|
|
}
|
|
|
|
// All unary instructions which write to their arguments (as opposed to reading
|
|
// from them) go here. The assembly parser uses this information to populate
|
|
// its AST in a semantically reasonable way.
|
|
//
|
|
// Any instructions not listed here are assumed to either be non-unary or to read
|
|
// from its argument.
|
|
var unaryDst = map[obj.As]bool{
|
|
ARDCYCLE: true,
|
|
ARDTIME: true,
|
|
ARDINSTRET: true,
|
|
}
|
|
|
|
// Instruction encoding masks.
|
|
const (
|
|
// BTypeImmMask is a mask including only the immediate portion of
|
|
// B-type instructions.
|
|
BTypeImmMask = 0xfe000f80
|
|
|
|
// CBTypeImmMask is a mask including only the immediate portion of
|
|
// CB-type instructions.
|
|
CBTypeImmMask = 0x1c7c
|
|
|
|
// CJTypeImmMask is a mask including only the immediate portion of
|
|
// CJ-type instructions.
|
|
CJTypeImmMask = 0x1f7c
|
|
|
|
// ITypeImmMask is a mask including only the immediate portion of
|
|
// I-type instructions.
|
|
ITypeImmMask = 0xfff00000
|
|
|
|
// JTypeImmMask is a mask including only the immediate portion of
|
|
// J-type instructions.
|
|
JTypeImmMask = 0xfffff000
|
|
|
|
// STypeImmMask is a mask including only the immediate portion of
|
|
// S-type instructions.
|
|
STypeImmMask = 0xfe000f80
|
|
|
|
// UTypeImmMask is a mask including only the immediate portion of
|
|
// U-type instructions.
|
|
UTypeImmMask = 0xfffff000
|
|
)
|