go/test/codegen/simd.go
Junyang Shao 771a1dc216 [dev.simd] cmd/compile: add peepholes for all masked ops and bug fixes
For 512-bits they are unchanged. This CL adds the optimization rules for
128/256-bits under feature check.

This CL also fixed a bug for masked load variant of instructions and
make them zeroing by default as well.

Change-Id: I6fe395541c0cd509984a81841420e71c3af732f2
Reviewed-on: https://go-review.googlesource.com/c/go/+/717822
Reviewed-by: David Chase <drchase@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-11-10 09:53:24 -08:00

69 lines
1.5 KiB
Go

// asmcheck
// Copyright 2025 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// These tests check code generation of simd peephole optimizations.
//go:build goexperiment.simd
package codegen
import "simd"
func vptest1() bool {
v1 := simd.LoadUint64x2Slice([]uint64{0, 1})
v2 := simd.LoadUint64x2Slice([]uint64{0, 0})
// amd64:`VPTEST\s(.*)(.*)$`
// amd64:`SETCS\s(.*)$`
return v1.AndNot(v2).IsZero()
}
func vptest2() bool {
v1 := simd.LoadUint64x2Slice([]uint64{0, 1})
v2 := simd.LoadUint64x2Slice([]uint64{0, 0})
// amd64:`VPTEST\s(.*)(.*)$`
// amd64:`SETEQ\s(.*)$`
return v1.And(v2).IsZero()
}
type Args2 struct {
V0 simd.Uint8x32
V1 simd.Uint8x32
x string
}
//go:noinline
func simdStructNoSpill(a Args2) simd.Uint8x32 {
// amd64:-`VMOVDQU\s.*$`
return a.V0.Xor(a.V1)
}
func simdStructWrapperNoSpill(a Args2) simd.Uint8x32 {
// amd64:-`VMOVDQU\s.*$`
a.x = "test"
return simdStructNoSpill(a)
}
//go:noinline
func simdArrayNoSpill(a [1]Args2) simd.Uint8x32 {
// amd64:-`VMOVDQU\s.*$`
return a[0].V0.Xor(a[0].V1)
}
func simdArrayWrapperNoSpill(a [1]Args2) simd.Uint8x32 {
// amd64:-`VMOVDQU\s.*$`
a[0].x = "test"
return simdArrayNoSpill(a)
}
func simdFeatureGuardedMaskOpt() simd.Int16x16 {
var x, y simd.Int16x16
if simd.HasAVX512() {
mask := simd.Mask16x16FromBits(5)
return x.Add(y).Masked(mask) // amd64:`VPADDW.Z\s.*$`
}
mask := simd.Mask16x16FromBits(5)
return x.Add(y).Masked(mask) // amd64:`VPAND\s.*$`
}