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12befc3ce3
Convert the scheduling pass from scheduling backwards to scheduling forwards. Forward scheduling makes it easier to prioritize scheduling values as soon as they are ready, which is important for things like nil checks, select ops, etc. Forward scheduling is also quite a bit clearer. It was originally backwards because computing uses is tricky, but I found a way to do it simply and with n lg n complexity. The new scheme also makes it easy to add new scheduling edges if needed. Fixes #42673 Update #56568 Change-Id: Ibbb38c52d191f50ce7a94f8c1cbd3cd9b614ea8b Reviewed-on: https://go-review.googlesource.com/c/go/+/270940 TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Keith Randall <khr@google.com> Run-TryBot: Keith Randall <khr@golang.org> Reviewed-by: David Chase <drchase@google.com>
482 lines
28 KiB
Go
482 lines
28 KiB
Go
// Copyright 2016 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package main
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import (
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"fmt"
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)
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// Notes:
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// - Boolean types occupy the entire register. 0=false, 1=true.
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// Suffixes encode the bit width of various instructions:
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//
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// D (double word) = 64 bit int
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// W (word) = 32 bit int
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// H (half word) = 16 bit int
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// B (byte) = 8 bit int
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// S (single) = 32 bit float
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// D (double) = 64 bit float
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// L = 64 bit int, used when the opcode starts with F
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const (
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riscv64REG_G = 27
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riscv64REG_CTXT = 26
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riscv64REG_LR = 1
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riscv64REG_SP = 2
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riscv64REG_GP = 3
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riscv64REG_TP = 4
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riscv64REG_TMP = 31
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riscv64REG_ZERO = 0
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)
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func riscv64RegName(r int) string {
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switch {
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case r == riscv64REG_G:
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return "g"
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case r == riscv64REG_SP:
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return "SP"
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case 0 <= r && r <= 31:
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return fmt.Sprintf("X%d", r)
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case 32 <= r && r <= 63:
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return fmt.Sprintf("F%d", r-32)
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default:
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panic(fmt.Sprintf("unknown register %d", r))
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}
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}
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func init() {
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var regNamesRISCV64 []string
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var gpMask, fpMask, gpgMask, gpspMask, gpspsbMask, gpspsbgMask regMask
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regNamed := make(map[string]regMask)
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// Build the list of register names, creating an appropriately indexed
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// regMask for the gp and fp registers as we go.
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//
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// If name is specified, use it rather than the riscv reg number.
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addreg := func(r int, name string) regMask {
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mask := regMask(1) << uint(len(regNamesRISCV64))
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if name == "" {
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name = riscv64RegName(r)
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}
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regNamesRISCV64 = append(regNamesRISCV64, name)
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regNamed[name] = mask
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return mask
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}
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// General purpose registers.
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for r := 0; r <= 31; r++ {
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if r == riscv64REG_LR {
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// LR is not used by regalloc, so we skip it to leave
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// room for pseudo-register SB.
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continue
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}
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mask := addreg(r, "")
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// Add general purpose registers to gpMask.
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switch r {
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// ZERO, GP, TP and TMP are not in any gp mask.
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case riscv64REG_ZERO, riscv64REG_GP, riscv64REG_TP, riscv64REG_TMP:
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case riscv64REG_G:
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gpgMask |= mask
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gpspsbgMask |= mask
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case riscv64REG_SP:
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gpspMask |= mask
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gpspsbMask |= mask
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gpspsbgMask |= mask
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default:
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gpMask |= mask
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gpgMask |= mask
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gpspMask |= mask
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gpspsbMask |= mask
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gpspsbgMask |= mask
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}
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}
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// Floating pointer registers.
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for r := 32; r <= 63; r++ {
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mask := addreg(r, "")
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fpMask |= mask
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}
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// Pseudo-register: SB
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mask := addreg(-1, "SB")
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gpspsbMask |= mask
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gpspsbgMask |= mask
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if len(regNamesRISCV64) > 64 {
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// regMask is only 64 bits.
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panic("Too many RISCV64 registers")
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}
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regCtxt := regNamed["X26"]
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callerSave := gpMask | fpMask | regNamed["g"]
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var (
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gpstore = regInfo{inputs: []regMask{gpspsbMask, gpspMask, 0}} // SB in first input so we can load from a global, but not in second to avoid using SB as a temporary register
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gpstore0 = regInfo{inputs: []regMask{gpspsbMask}}
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gp01 = regInfo{outputs: []regMask{gpMask}}
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gp11 = regInfo{inputs: []regMask{gpMask}, outputs: []regMask{gpMask}}
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gp21 = regInfo{inputs: []regMask{gpMask, gpMask}, outputs: []regMask{gpMask}}
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gp22 = regInfo{inputs: []regMask{gpMask, gpMask}, outputs: []regMask{gpMask, gpMask}}
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gpload = regInfo{inputs: []regMask{gpspsbMask, 0}, outputs: []regMask{gpMask}}
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gp11sb = regInfo{inputs: []regMask{gpspsbMask}, outputs: []regMask{gpMask}}
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gpxchg = regInfo{inputs: []regMask{gpspsbgMask, gpgMask}, outputs: []regMask{gpMask}}
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gpcas = regInfo{inputs: []regMask{gpspsbgMask, gpgMask, gpgMask}, outputs: []regMask{gpMask}}
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gpatomic = regInfo{inputs: []regMask{gpspsbgMask, gpgMask}}
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fp11 = regInfo{inputs: []regMask{fpMask}, outputs: []regMask{fpMask}}
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fp21 = regInfo{inputs: []regMask{fpMask, fpMask}, outputs: []regMask{fpMask}}
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fp31 = regInfo{inputs: []regMask{fpMask, fpMask, fpMask}, outputs: []regMask{fpMask}}
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gpfp = regInfo{inputs: []regMask{gpMask}, outputs: []regMask{fpMask}}
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fpgp = regInfo{inputs: []regMask{fpMask}, outputs: []regMask{gpMask}}
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fpstore = regInfo{inputs: []regMask{gpspsbMask, fpMask, 0}}
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fpload = regInfo{inputs: []regMask{gpspsbMask, 0}, outputs: []regMask{fpMask}}
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fp2gp = regInfo{inputs: []regMask{fpMask, fpMask}, outputs: []regMask{gpMask}}
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call = regInfo{clobbers: callerSave}
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callClosure = regInfo{inputs: []regMask{gpspMask, regCtxt, 0}, clobbers: callerSave}
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callInter = regInfo{inputs: []regMask{gpMask}, clobbers: callerSave}
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)
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RISCV64ops := []opData{
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{name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1
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{name: "ADDI", argLength: 1, reg: gp11sb, asm: "ADDI", aux: "Int64"}, // arg0 + auxint
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{name: "ADDIW", argLength: 1, reg: gp11, asm: "ADDIW", aux: "Int64"}, // 32 low bits of arg0 + auxint, sign extended to 64 bits
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{name: "NEG", argLength: 1, reg: gp11, asm: "NEG"}, // -arg0
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{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW"}, // -arg0 of 32 bits, sign extended to 64 bits
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{name: "SUB", argLength: 2, reg: gp21, asm: "SUB"}, // arg0 - arg1
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{name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW"}, // 32 low bits of arg 0 - 32 low bits of arg 1, sign extended to 64 bits
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// M extension. H means high (i.e., it returns the top bits of
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// the result). U means unsigned. W means word (i.e., 32-bit).
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{name: "MUL", argLength: 2, reg: gp21, asm: "MUL", commutative: true, typ: "Int64"}, // arg0 * arg1
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{name: "MULW", argLength: 2, reg: gp21, asm: "MULW", commutative: true, typ: "Int32"},
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{name: "MULH", argLength: 2, reg: gp21, asm: "MULH", commutative: true, typ: "Int64"},
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{name: "MULHU", argLength: 2, reg: gp21, asm: "MULHU", commutative: true, typ: "UInt64"},
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{name: "LoweredMuluhilo", argLength: 2, reg: gp22, resultNotInArgs: true}, // arg0 * arg1, return (hi, lo)
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{name: "LoweredMuluover", argLength: 2, reg: gp22, resultNotInArgs: true}, // arg0 * arg1, return (64 bits of arg0*arg1, overflow)
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{name: "DIV", argLength: 2, reg: gp21, asm: "DIV", typ: "Int64"}, // arg0 / arg1
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{name: "DIVU", argLength: 2, reg: gp21, asm: "DIVU", typ: "UInt64"},
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{name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"},
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{name: "DIVUW", argLength: 2, reg: gp21, asm: "DIVUW", typ: "UInt32"},
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{name: "REM", argLength: 2, reg: gp21, asm: "REM", typ: "Int64"}, // arg0 % arg1
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{name: "REMU", argLength: 2, reg: gp21, asm: "REMU", typ: "UInt64"},
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{name: "REMW", argLength: 2, reg: gp21, asm: "REMW", typ: "Int32"},
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{name: "REMUW", argLength: 2, reg: gp21, asm: "REMUW", typ: "UInt32"},
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{name: "MOVaddr", argLength: 1, reg: gp11sb, asm: "MOV", aux: "SymOff", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxint + offset encoded in aux
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// auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address
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{name: "MOVDconst", reg: gp01, asm: "MOV", typ: "UInt64", aux: "Int64", rematerializeable: true}, // auxint
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// Loads: load <size> bits from arg0+auxint+aux and extend to 64 bits; arg1=mem
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{name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVB", aux: "SymOff", typ: "Int8", faultOnNilArg0: true, symEffect: "Read"}, // 8 bits, sign extend
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{name: "MOVHload", argLength: 2, reg: gpload, asm: "MOVH", aux: "SymOff", typ: "Int16", faultOnNilArg0: true, symEffect: "Read"}, // 16 bits, sign extend
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{name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVW", aux: "SymOff", typ: "Int32", faultOnNilArg0: true, symEffect: "Read"}, // 32 bits, sign extend
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{name: "MOVDload", argLength: 2, reg: gpload, asm: "MOV", aux: "SymOff", typ: "Int64", faultOnNilArg0: true, symEffect: "Read"}, // 64 bits
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{name: "MOVBUload", argLength: 2, reg: gpload, asm: "MOVBU", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, // 8 bits, zero extend
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{name: "MOVHUload", argLength: 2, reg: gpload, asm: "MOVHU", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // 16 bits, zero extend
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{name: "MOVWUload", argLength: 2, reg: gpload, asm: "MOVWU", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // 32 bits, zero extend
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// Stores: store <size> lowest bits in arg1 to arg0+auxint+aux; arg2=mem
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{name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 8 bits
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{name: "MOVHstore", argLength: 3, reg: gpstore, asm: "MOVH", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 16 bits
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{name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 32 bits
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{name: "MOVDstore", argLength: 3, reg: gpstore, asm: "MOV", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 64 bits
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// Stores: store <size> of zero in arg0+auxint+aux; arg1=mem
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{name: "MOVBstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 8 bits
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{name: "MOVHstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 16 bits
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{name: "MOVWstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 32 bits
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{name: "MOVDstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // 64 bits
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// Conversions
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{name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"}, // move from arg0, sign-extended from byte
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{name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH"}, // move from arg0, sign-extended from half
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{name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW"}, // move from arg0, sign-extended from word
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{name: "MOVDreg", argLength: 1, reg: gp11, asm: "MOV"}, // move from arg0
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{name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte
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{name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half
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{name: "MOVWUreg", argLength: 1, reg: gp11, asm: "MOVWU"}, // move from arg0, unsign-extended from word
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{name: "MOVDnop", argLength: 1, reg: regInfo{inputs: []regMask{gpMask}, outputs: []regMask{gpMask}}, resultInArg0: true}, // nop, return arg0 in same register
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// Shift ops
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{name: "SLL", argLength: 2, reg: gp21, asm: "SLL"}, // arg0 << (aux1 & 63)
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{name: "SRA", argLength: 2, reg: gp21, asm: "SRA"}, // arg0 >> (aux1 & 63), signed
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{name: "SRL", argLength: 2, reg: gp21, asm: "SRL"}, // arg0 >> (aux1 & 63), unsigned
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{name: "SLLI", argLength: 1, reg: gp11, asm: "SLLI", aux: "Int64"}, // arg0 << auxint, shift amount 0-63
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{name: "SRAI", argLength: 1, reg: gp11, asm: "SRAI", aux: "Int64"}, // arg0 >> auxint, signed, shift amount 0-63
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{name: "SRLI", argLength: 1, reg: gp11, asm: "SRLI", aux: "Int64"}, // arg0 >> auxint, unsigned, shift amount 0-63
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// Bitwise ops
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{name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true}, // arg0 ^ arg1
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{name: "XORI", argLength: 1, reg: gp11, asm: "XORI", aux: "Int64"}, // arg0 ^ auxint
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{name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true}, // arg0 | arg1
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{name: "ORI", argLength: 1, reg: gp11, asm: "ORI", aux: "Int64"}, // arg0 | auxint
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{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1
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{name: "ANDI", argLength: 1, reg: gp11, asm: "ANDI", aux: "Int64"}, // arg0 & auxint
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{name: "NOT", argLength: 1, reg: gp11, asm: "NOT"}, // ^arg0
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// Generate boolean values
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{name: "SEQZ", argLength: 1, reg: gp11, asm: "SEQZ"}, // arg0 == 0, result is 0 or 1
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{name: "SNEZ", argLength: 1, reg: gp11, asm: "SNEZ"}, // arg0 != 0, result is 0 or 1
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{name: "SLT", argLength: 2, reg: gp21, asm: "SLT"}, // arg0 < arg1, result is 0 or 1
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{name: "SLTI", argLength: 1, reg: gp11, asm: "SLTI", aux: "Int64"}, // arg0 < auxint, result is 0 or 1
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{name: "SLTU", argLength: 2, reg: gp21, asm: "SLTU"}, // arg0 < arg1, unsigned, result is 0 or 1
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{name: "SLTIU", argLength: 1, reg: gp11, asm: "SLTIU", aux: "Int64"}, // arg0 < auxint, unsigned, result is 0 or 1
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// MOVconvert converts between pointers and integers.
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// We have a special op for this so as to not confuse GC
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// (particularly stack maps). It takes a memory arg so it
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// gets correctly ordered with respect to GC safepoints.
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{name: "MOVconvert", argLength: 2, reg: gp11, asm: "MOV"}, // arg0, but converted to int/ptr as appropriate; arg1=mem
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// Calls
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{name: "CALLstatic", argLength: -1, reg: call, aux: "CallOff", call: true}, // call static function aux.(*gc.Sym). last arg=mem, auxint=argsize, returns mem
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{name: "CALLtail", argLength: -1, reg: call, aux: "CallOff", call: true, tailCall: true}, // tail call static function aux.(*gc.Sym). last arg=mem, auxint=argsize, returns mem
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{name: "CALLclosure", argLength: -1, reg: callClosure, aux: "CallOff", call: true}, // call function via closure. arg0=codeptr, arg1=closure, last arg=mem, auxint=argsize, returns mem
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{name: "CALLinter", argLength: -1, reg: callInter, aux: "CallOff", call: true}, // call fn by pointer. arg0=codeptr, last arg=mem, auxint=argsize, returns mem
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// duffzero
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// arg0 = address of memory to zero (in X25, changed as side effect)
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// arg1 = mem
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// auxint = offset into duffzero code to start executing
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// X1 (link register) changed because of function call
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// returns mem
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{
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name: "DUFFZERO",
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aux: "Int64",
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argLength: 2,
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reg: regInfo{
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inputs: []regMask{regNamed["X25"]},
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clobbers: regNamed["X1"] | regNamed["X25"],
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},
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typ: "Mem",
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faultOnNilArg0: true,
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},
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// duffcopy
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// arg0 = address of dst memory (in X25, changed as side effect)
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// arg1 = address of src memory (in X24, changed as side effect)
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// arg2 = mem
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// auxint = offset into duffcopy code to start executing
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// X1 (link register) changed because of function call
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// returns mem
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{
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name: "DUFFCOPY",
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aux: "Int64",
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argLength: 3,
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reg: regInfo{
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inputs: []regMask{regNamed["X25"], regNamed["X24"]},
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clobbers: regNamed["X1"] | regNamed["X24"] | regNamed["X25"],
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},
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typ: "Mem",
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faultOnNilArg0: true,
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faultOnNilArg1: true,
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},
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// Generic moves and zeros
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// general unaligned zeroing
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// arg0 = address of memory to zero (in X5, changed as side effect)
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// arg1 = address of the last element to zero (inclusive)
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// arg2 = mem
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// auxint = element size
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// returns mem
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// mov ZERO, (X5)
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// ADD $sz, X5
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// BGEU Rarg1, X5, -2(PC)
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{
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name: "LoweredZero",
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aux: "Int64",
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argLength: 3,
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reg: regInfo{
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inputs: []regMask{regNamed["X5"], gpMask},
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clobbers: regNamed["X5"],
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},
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typ: "Mem",
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faultOnNilArg0: true,
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},
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// general unaligned move
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// arg0 = address of dst memory (in X5, changed as side effect)
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// arg1 = address of src memory (in X6, changed as side effect)
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// arg2 = address of the last element of src (can't be X7 as we clobber it before using arg2)
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// arg3 = mem
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// auxint = alignment
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// clobbers X7 as a tmp register.
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// returns mem
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// mov (X6), X7
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// mov X7, (X5)
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// ADD $sz, X5
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// ADD $sz, X6
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// BGEU Rarg2, X5, -4(PC)
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{
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name: "LoweredMove",
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aux: "Int64",
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argLength: 4,
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reg: regInfo{
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inputs: []regMask{regNamed["X5"], regNamed["X6"], gpMask &^ regNamed["X7"]},
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clobbers: regNamed["X5"] | regNamed["X6"] | regNamed["X7"],
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},
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typ: "Mem",
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faultOnNilArg0: true,
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faultOnNilArg1: true,
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},
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// Atomic loads.
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// load from arg0. arg1=mem.
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// returns <value,memory> so they can be properly ordered with other loads.
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{name: "LoweredAtomicLoad8", argLength: 2, reg: gpload, faultOnNilArg0: true},
|
|
{name: "LoweredAtomicLoad32", argLength: 2, reg: gpload, faultOnNilArg0: true},
|
|
{name: "LoweredAtomicLoad64", argLength: 2, reg: gpload, faultOnNilArg0: true},
|
|
|
|
// Atomic stores.
|
|
// store arg1 to *arg0. arg2=mem. returns memory.
|
|
{name: "LoweredAtomicStore8", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
|
|
{name: "LoweredAtomicStore32", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
|
|
{name: "LoweredAtomicStore64", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
|
|
|
|
// Atomic exchange.
|
|
// store arg1 to *arg0. arg2=mem. returns <old content of *arg0, memory>.
|
|
{name: "LoweredAtomicExchange32", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
|
|
{name: "LoweredAtomicExchange64", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
|
|
|
|
// Atomic add.
|
|
// *arg0 += arg1. arg2=mem. returns <new content of *arg0, memory>.
|
|
{name: "LoweredAtomicAdd32", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
|
{name: "LoweredAtomicAdd64", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
|
|
|
// Atomic compare and swap.
|
|
// arg0 = pointer, arg1 = old value, arg2 = new value, arg3 = memory.
|
|
// if *arg0 == arg1 {
|
|
// *arg0 = arg2
|
|
// return (true, memory)
|
|
// } else {
|
|
// return (false, memory)
|
|
// }
|
|
// MOV $0, Rout
|
|
// LR (Rarg0), Rtmp
|
|
// BNE Rtmp, Rarg1, 3(PC)
|
|
// SC Rarg2, (Rarg0), Rtmp
|
|
// BNE Rtmp, ZERO, -3(PC)
|
|
// MOV $1, Rout
|
|
{name: "LoweredAtomicCas32", argLength: 4, reg: gpcas, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
|
{name: "LoweredAtomicCas64", argLength: 4, reg: gpcas, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
|
|
|
// Atomic 32 bit AND/OR.
|
|
// *arg0 &= (|=) arg1. arg2=mem. returns nil.
|
|
{name: "LoweredAtomicAnd32", argLength: 3, reg: gpatomic, asm: "AMOANDW", faultOnNilArg0: true, hasSideEffects: true},
|
|
{name: "LoweredAtomicOr32", argLength: 3, reg: gpatomic, asm: "AMOORW", faultOnNilArg0: true, hasSideEffects: true},
|
|
|
|
// Lowering pass-throughs
|
|
{name: "LoweredNilCheck", argLength: 2, faultOnNilArg0: true, nilCheck: true, reg: regInfo{inputs: []regMask{gpspMask}}}, // arg0=ptr,arg1=mem, returns void. Faults if ptr is nil.
|
|
{name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{regCtxt}}}, // scheduler ensures only at beginning of entry block
|
|
|
|
// LoweredGetCallerSP returns the SP of the caller of the current function. arg0=mem.
|
|
{name: "LoweredGetCallerSP", argLength: 1, reg: gp01, rematerializeable: true},
|
|
|
|
// LoweredGetCallerPC evaluates to the PC to which its "caller" will return.
|
|
// I.e., if f calls g "calls" getcallerpc,
|
|
// the result should be the PC within f that g will return to.
|
|
// See runtime/stubs.go for a more detailed discussion.
|
|
{name: "LoweredGetCallerPC", reg: gp01, rematerializeable: true},
|
|
|
|
// LoweredWB invokes runtime.gcWriteBarrier. arg0=destptr, arg1=srcptr, arg2=mem, aux=runtime.gcWriteBarrier
|
|
// It saves all GP registers if necessary,
|
|
// but clobbers RA (LR) because it's a call
|
|
// and T6 (REG_TMP).
|
|
{name: "LoweredWB", argLength: 3, reg: regInfo{inputs: []regMask{regNamed["X5"], regNamed["X6"]}, clobbers: (callerSave &^ (gpMask | regNamed["g"])) | regNamed["X1"]}, clobberFlags: true, aux: "Sym", symEffect: "None"},
|
|
|
|
// There are three of these functions so that they can have three different register inputs.
|
|
// When we check 0 <= c <= cap (A), then 0 <= b <= c (B), then 0 <= a <= b (C), we want the
|
|
// default registers to match so we don't need to copy registers around unnecessarily.
|
|
{name: "LoweredPanicBoundsA", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{regNamed["X7"], regNamed["X28"]}}, typ: "Mem", call: true}, // arg0=idx, arg1=len, arg2=mem, returns memory. AuxInt contains report code (see PanicBounds in genericOps.go).
|
|
{name: "LoweredPanicBoundsB", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{regNamed["X6"], regNamed["X7"]}}, typ: "Mem", call: true}, // arg0=idx, arg1=len, arg2=mem, returns memory. AuxInt contains report code (see PanicBounds in genericOps.go).
|
|
{name: "LoweredPanicBoundsC", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{regNamed["X5"], regNamed["X6"]}}, typ: "Mem", call: true}, // arg0=idx, arg1=len, arg2=mem, returns memory. AuxInt contains report code (see PanicBounds in genericOps.go).
|
|
|
|
// F extension.
|
|
{name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true, typ: "Float32"}, // arg0 + arg1
|
|
{name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS", commutative: false, typ: "Float32"}, // arg0 - arg1
|
|
{name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true, typ: "Float32"}, // arg0 * arg1
|
|
{name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS", commutative: false, typ: "Float32"}, // arg0 / arg1
|
|
{name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS", typ: "Float32"}, // sqrt(arg0)
|
|
{name: "FNEGS", argLength: 1, reg: fp11, asm: "FNEGS", typ: "Float32"}, // -arg0
|
|
{name: "FMVSX", argLength: 1, reg: gpfp, asm: "FMVSX", typ: "Float32"}, // reinterpret arg0 as float
|
|
{name: "FCVTSW", argLength: 1, reg: gpfp, asm: "FCVTSW", typ: "Float32"}, // float32(low 32 bits of arg0)
|
|
{name: "FCVTSL", argLength: 1, reg: gpfp, asm: "FCVTSL", typ: "Float32"}, // float32(arg0)
|
|
{name: "FCVTWS", argLength: 1, reg: fpgp, asm: "FCVTWS", typ: "Int32"}, // int32(arg0)
|
|
{name: "FCVTLS", argLength: 1, reg: fpgp, asm: "FCVTLS", typ: "Int64"}, // int64(arg0)
|
|
{name: "FMOVWload", argLength: 2, reg: fpload, asm: "MOVF", aux: "SymOff", typ: "Float32", faultOnNilArg0: true, symEffect: "Read"}, // load float32 from arg0+auxint+aux
|
|
{name: "FMOVWstore", argLength: 3, reg: fpstore, asm: "MOVF", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store float32 to arg0+auxint+aux
|
|
{name: "FEQS", argLength: 2, reg: fp2gp, asm: "FEQS", commutative: true}, // arg0 == arg1
|
|
{name: "FNES", argLength: 2, reg: fp2gp, asm: "FNES", commutative: true}, // arg0 != arg1
|
|
{name: "FLTS", argLength: 2, reg: fp2gp, asm: "FLTS"}, // arg0 < arg1
|
|
{name: "FLES", argLength: 2, reg: fp2gp, asm: "FLES"}, // arg0 <= arg1
|
|
|
|
// D extension.
|
|
{name: "FADDD", argLength: 2, reg: fp21, asm: "FADDD", commutative: true, typ: "Float64"}, // arg0 + arg1
|
|
{name: "FSUBD", argLength: 2, reg: fp21, asm: "FSUBD", commutative: false, typ: "Float64"}, // arg0 - arg1
|
|
{name: "FMULD", argLength: 2, reg: fp21, asm: "FMULD", commutative: true, typ: "Float64"}, // arg0 * arg1
|
|
{name: "FDIVD", argLength: 2, reg: fp21, asm: "FDIVD", commutative: false, typ: "Float64"}, // arg0 / arg1
|
|
{name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD", commutative: true, typ: "Float64"}, // (arg0 * arg1) + arg2
|
|
{name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD", commutative: true, typ: "Float64"}, // (arg0 * arg1) - arg2
|
|
{name: "FNMADDD", argLength: 3, reg: fp31, asm: "FNMADDD", commutative: true, typ: "Float64"}, // -(arg0 * arg1) + arg2
|
|
{name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD", commutative: true, typ: "Float64"}, // -(arg0 * arg1) - arg2
|
|
{name: "FSQRTD", argLength: 1, reg: fp11, asm: "FSQRTD", typ: "Float64"}, // sqrt(arg0)
|
|
{name: "FNEGD", argLength: 1, reg: fp11, asm: "FNEGD", typ: "Float64"}, // -arg0
|
|
{name: "FABSD", argLength: 1, reg: fp11, asm: "FABSD", typ: "Float64"}, // abs(arg0)
|
|
{name: "FSGNJD", argLength: 2, reg: fp21, asm: "FSGNJD", typ: "Float64"}, // copy sign of arg1 to arg0
|
|
{name: "FMVDX", argLength: 1, reg: gpfp, asm: "FMVDX", typ: "Float64"}, // reinterpret arg0 as float
|
|
{name: "FCVTDW", argLength: 1, reg: gpfp, asm: "FCVTDW", typ: "Float64"}, // float64(low 32 bits of arg0)
|
|
{name: "FCVTDL", argLength: 1, reg: gpfp, asm: "FCVTDL", typ: "Float64"}, // float64(arg0)
|
|
{name: "FCVTWD", argLength: 1, reg: fpgp, asm: "FCVTWD", typ: "Int32"}, // int32(arg0)
|
|
{name: "FCVTLD", argLength: 1, reg: fpgp, asm: "FCVTLD", typ: "Int64"}, // int64(arg0)
|
|
{name: "FCVTDS", argLength: 1, reg: fp11, asm: "FCVTDS", typ: "Float64"}, // float64(arg0)
|
|
{name: "FCVTSD", argLength: 1, reg: fp11, asm: "FCVTSD", typ: "Float32"}, // float32(arg0)
|
|
{name: "FMOVDload", argLength: 2, reg: fpload, asm: "MOVD", aux: "SymOff", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"}, // load float64 from arg0+auxint+aux
|
|
{name: "FMOVDstore", argLength: 3, reg: fpstore, asm: "MOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store float6 to arg0+auxint+aux
|
|
{name: "FEQD", argLength: 2, reg: fp2gp, asm: "FEQD", commutative: true}, // arg0 == arg1
|
|
{name: "FNED", argLength: 2, reg: fp2gp, asm: "FNED", commutative: true}, // arg0 != arg1
|
|
{name: "FLTD", argLength: 2, reg: fp2gp, asm: "FLTD"}, // arg0 < arg1
|
|
{name: "FLED", argLength: 2, reg: fp2gp, asm: "FLED"}, // arg0 <= arg1
|
|
}
|
|
|
|
RISCV64blocks := []blockData{
|
|
{name: "BEQ", controls: 2},
|
|
{name: "BNE", controls: 2},
|
|
{name: "BLT", controls: 2},
|
|
{name: "BGE", controls: 2},
|
|
{name: "BLTU", controls: 2},
|
|
{name: "BGEU", controls: 2},
|
|
|
|
{name: "BEQZ", controls: 1},
|
|
{name: "BNEZ", controls: 1},
|
|
{name: "BLEZ", controls: 1},
|
|
{name: "BGEZ", controls: 1},
|
|
{name: "BLTZ", controls: 1},
|
|
{name: "BGTZ", controls: 1},
|
|
}
|
|
|
|
archs = append(archs, arch{
|
|
name: "RISCV64",
|
|
pkg: "cmd/internal/obj/riscv",
|
|
genfile: "../../riscv64/ssa.go",
|
|
ops: RISCV64ops,
|
|
blocks: RISCV64blocks,
|
|
regnames: regNamesRISCV64,
|
|
gpregmask: gpMask,
|
|
fpregmask: fpMask,
|
|
framepointerreg: -1, // not used
|
|
// Integer parameters passed in register X10-X17, X8-X9, X18-X23
|
|
ParamIntRegNames: "X10 X11 X12 X13 X14 X15 X16 X17 X8 X9 X18 X19 X20 X21 X22 X23",
|
|
// Float parameters passed in register F10-F17, F8-F9, F18-F23
|
|
ParamFloatRegNames: "F10 F11 F12 F13 F14 F15 F16 F17 F8 F9 F18 F19 F20 F21 F22 F23",
|
|
})
|
|
}
|