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raise IRQ only if IRQ bit in DOR is enabled

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The floppy controller's Digital Output Register (DOR) is a read/writeable
8 bit register. Amongst other things, this register allows the guest to
reset the floppy controller ("nRESET" bit 0x8) and to enable/disable the
use of the controller's IRQ line ("IRQ" bit 0x4). Note that the "nRESET"
bit is negated ("not RESET").

The floppy controller is expected to raise an IRQ when exiting the RESET
state, meaning when the guest changes the nRESET bit from 0 to 1.

That is what is currently done in the DOR write handler in floppy.js.

But the floppy controller is also expected to raise IRQs only if the IRQ
bit in DOR is set, and this was not considered in the DOR write handler.

This commit changes the DOR write handler to raise the IRQ only if the
IRQ bit is also set in the new DOR value received from the guest.
This commit is contained in:
Christian Schnell 2025-06-08 22:00:08 +02:00 • committed by Fabian
parent d603a779db
commit 10bb5bc0fa
1 changed files with 11 additions and 4 deletions
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15
src/floppy.js
View file

@ -343,16 +343,23 @@ FloppyController.prototype.port3F2_read = function()
FloppyController.prototype.port3F2_write = function(value)
{
if((value & 4) === 4 && (this.dor & 4) === 0)
// write Digital Output Register (DOR), relevant bits here:
// 0x4 (nRESET): 0: RESET mode, 1: NORMAL mode
// 0x8 (IRQ_DMA): 0: disable IRQ/DMA, 1: enable IRQ/DMA
if(!(this.dor & 0x4) && (value & 0x4))
{
// clear reset mode
// nRESET bit transition from 0 to 1: exit from RESET state
this.status_reg0 = 0xC0;
this.cpu.device_raise_irq(6);
if(value & 0x8)
{
// raise IRQ only if IRQ_DMA bit is 1 (in new DOR value)
this.cpu.device_raise_irq(6);
}
}
dbg_log("start motors: " + h(value >> 4), LOG_FLOPPY);
dbg_log("enable dma/irq: " + !!(value & 8), LOG_FLOPPY);
dbg_log("reset fdc: " + !!(value & 4), LOG_FLOPPY);
dbg_log("reset fdc: " + !(value & 4), LOG_FLOPPY);
dbg_log("drive select: " + (value & 3), LOG_FLOPPY);
if((value & 3) !== 0)
{