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improved single-device implementation
- immplemented Command and Status register requirements from the standard, ignored all others - rearranged IDE register definitions, added a descriptive comment to each (standard lingo) - fixed the EXECUTE DEVICE DIAGNOSTIC (90h) ATA command
This commit is contained in:
Christian Schnell
Fabian
parent
f5e35644da
commit
1e645e0f06
1 changed files with 76 additions and 23 deletions
99
src/ide.js
99
src/ide.js
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@ -25,7 +25,7 @@ const HD_SECTOR_SIZE = 512;
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* If is_cdrom is defined and true:
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* - If buffer is defined: create an ATAPI CD-ROM device using buffer as inserted disk
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* - If buffer is undefined: create an ATAPI CD-ROM device with ejectd disk
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* If is_cdrom is undfined or false:
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* If is_cdrom is undefined or false:
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* - If buffer is defined: create an ATA Hard-Disk using buffer as disk image
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* - If buffer is undefined: create a dummy ATA device representing a missing disk
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* */
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@ -159,22 +159,13 @@ function IDEDevice(adapter, adapter_config, channel_nr, channel_config) // T
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/** @type {number} */
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this.dma_command = 0;
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// Status Registers (across BAR0-BAR3)
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const cpu = adapter.cpu;
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cpu.io.register_read(this.ata_port | 7, this, function() {
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dbg_log("lower irq", LOG_DISK);
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this.cpu.device_lower_irq(this.irq);
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return this.read_status();
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});
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cpu.io.register_read(this.ata_port_high | 2, this, this.read_status);
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// Control Register (BAR1/3)
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cpu.io.register_write(this.ata_port_high | 2, this, this.write_control);
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// ATA/ATAPI Registers (BAR0/2)
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//
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// Command Block Registers: ata_port + 0...7 (BAR0: 1F0h, BAR2: 170h)
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//
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// read Data register
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cpu.io.register_read(this.ata_port | 0, this, function()
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{
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return this.current_interface.read_data(1);
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@ -186,40 +177,57 @@ function IDEDevice(adapter, adapter_config, channel_nr, channel_config) // T
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return this.current_interface.read_data(4);
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});
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// read Error register
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cpu.io.register_read(this.ata_port | 1, this, function()
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{
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dbg_log("Read error: " + h(this.current_interface.error & 0xFF) +
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" slave=" + (this.current_interface === this.slave), LOG_DISK);
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return this.current_interface.error & 0xFF;
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});
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// read Sector Count register
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cpu.io.register_read(this.ata_port | 2, this, function()
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{
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dbg_log("Read bytecount: " + h(this.current_interface.bytecount & 0xFF), LOG_DISK);
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return this.current_interface.bytecount & 0xFF;
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});
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// read LBA Low register
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cpu.io.register_read(this.ata_port | 3, this, function()
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{
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dbg_log("Read sector: " + h(this.current_interface.sector & 0xFF), LOG_DISK);
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return this.current_interface.sector & 0xFF;
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});
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// read LBA Mid register
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cpu.io.register_read(this.ata_port | 4, this, function()
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{
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dbg_log("Read 1F4: " + h(this.current_interface.cylinder_low & 0xFF), LOG_DISK);
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return this.current_interface.cylinder_low & 0xFF;
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});
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// read LBA High register
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cpu.io.register_read(this.ata_port | 5, this, function()
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{
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dbg_log("Read 1F5: " + h(this.current_interface.cylinder_high & 0xFF), LOG_DISK);
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return this.current_interface.cylinder_high & 0xFF;
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});
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// read Device register
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cpu.io.register_read(this.ata_port | 6, this, function()
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{
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dbg_log("Read 1F6", LOG_DISK);
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return this.current_interface.drive_head & 0xFF;
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});
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// NOTE: read-handler for Status Register (this.ata_port | 7) is already defined above
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// read Status register
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cpu.io.register_read(this.ata_port | 7, this, function() {
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dbg_log("lower irq", LOG_DISK);
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this.cpu.device_lower_irq(this.irq);
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return this.read_status();
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});
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// write Data register
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cpu.io.register_write(this.ata_port | 0, this, function(data)
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{
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this.current_interface.write_data_port8(data);
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@ -231,6 +239,7 @@ function IDEDevice(adapter, adapter_config, channel_nr, channel_config) // T
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this.current_interface.write_data_port32(data);
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});
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// write Features register
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cpu.io.register_write(this.ata_port | 1, this, function(data)
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{
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dbg_log("1F1/lba_count: " + h(data), LOG_DISK);
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@ -240,6 +249,8 @@ function IDEDevice(adapter, adapter_config, channel_nr, channel_config) // T
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***/
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this.current_interface.lba_count = (this.current_interface.lba_count << 8 | data) & 0xFFFF;
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});
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// write Sector Count register
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cpu.io.register_write(this.ata_port | 2, this, function(data)
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{
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dbg_log("1F2/bytecount: " + h(data), LOG_DISK);
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@ -252,6 +263,8 @@ function IDEDevice(adapter, adapter_config, channel_nr, channel_config) // T
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***/
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this.current_interface.bytecount = (this.current_interface.bytecount << 8 | data) & 0xFFFF;
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});
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// write LBA Low register
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cpu.io.register_write(this.ata_port | 3, this, function(data)
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{
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dbg_log("1F3/sector: " + h(data), LOG_DISK);
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@ -265,6 +278,7 @@ function IDEDevice(adapter, adapter_config, channel_nr, channel_config) // T
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this.current_interface.sector = (this.current_interface.sector << 8 | data) & 0xFFFF;
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});
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// write LBA Mid register
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cpu.io.register_write(this.ata_port | 4, this, function(data)
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{
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dbg_log("1F4/sector low: " + h(data), LOG_DISK);
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@ -277,6 +291,8 @@ function IDEDevice(adapter, adapter_config, channel_nr, channel_config) // T
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***/
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this.current_interface.cylinder_low = (this.current_interface.cylinder_low << 8 | data) & 0xFFFF;
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});
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// write LBA High register
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cpu.io.register_write(this.ata_port | 5, this, function(data)
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{
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dbg_log("1F5/sector high: " + h(data), LOG_DISK);
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@ -289,6 +305,8 @@ function IDEDevice(adapter, adapter_config, channel_nr, channel_config) // T
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***/
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this.current_interface.cylinder_high = (this.current_interface.cylinder_high << 8 | data) & 0xFFFF;
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});
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// write Device register
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cpu.io.register_write(this.ata_port | 6, this, function(data)
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{
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var slave = data & 0x10;
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@ -316,6 +334,7 @@ function IDEDevice(adapter, adapter_config, channel_nr, channel_config) // T
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this.current_interface.head = data & 0xF;
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});
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// write Command register
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cpu.io.register_write(this.ata_port | 7, this, function(data)
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{
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dbg_log("lower irq", LOG_DISK);
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@ -325,7 +344,20 @@ function IDEDevice(adapter, adapter_config, channel_nr, channel_config) // T
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this.current_interface.ata_command(data);
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});
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// Bus Master Registers (BAR4)
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//
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// Control Block Register: ata_port_high + 0...3 (BAR1: 3F4h, BAR3: 374h)
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//
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// read Alternate Status register
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cpu.io.register_read(this.ata_port_high | 2, this, this.read_status);
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// write Device Control register
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cpu.io.register_write(this.ata_port_high | 2, this, this.write_control);
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//
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// Bus Master Registers: bus_master_port + 0...16 (BAR4, lower 8 for primary and upper 8 for secondary channel)
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//
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const bus_master_port = channel_config.bus_master_port;
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cpu.io.register_read(bus_master_port, this,
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@ -512,6 +544,7 @@ IDEDevice.prototype.set_state = function(state)
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function IDEInterface(device, cpu, buffer, is_cd, device_nr, interface_nr, bus)
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{
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this.device = device;
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this.name = device.name + ":" + interface_nr;
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/** @const @type {BusConnector} */
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this.bus = bus;
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@ -522,6 +555,12 @@ function IDEInterface(device, cpu, buffer, is_cd, device_nr, interface_nr, bus)
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*/
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this.nr = device_nr;
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/**
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* @const
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* @type {number}
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*/
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this.interface_nr = interface_nr;
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/** @const @type {CPU} */
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this.cpu = cpu;
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@ -725,12 +764,9 @@ IDEInterface.prototype.ata_command = function(cmd)
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{
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dbg_log("ATA Command: " + h(cmd) + " slave=" + (this.drive_head >> 4 & 1), LOG_DISK);
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if((!this.buffer && cmd != 0xA1 && cmd != 0xEC && cmd != 0xA0))
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if(!this.drive_connected && cmd != 0x90)
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{
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dbg_log("abort: No buffer", LOG_DISK);
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this.error = 4;
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this.status = 0x41;
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this.push_irq();
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dbg_log("ignored: No slave drive connected", LOG_DISK);
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return;
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}
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@ -801,9 +837,26 @@ IDEInterface.prototype.ata_command = function(cmd)
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case 0x90:
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// execute device diagnostic
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this.push_irq();
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this.error = 0x101;
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// assign diagnostics code (used to be 0x101?) to error register
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if(this.interface_nr === 0) {
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// master drive is currently selected
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if(this.device.slave.drive_connected) {
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this.error = 0x01; // Master drive passed, slave passed or not present
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}
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else {
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this.error = 0x81; // Master drive passed, slave failed
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}
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}
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else {
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if(this.device.slave.drive_connected) {
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this.error = 0x01; // Slave drive passed
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}
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else {
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this.error = 0x00; // Slave drive failed
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}
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}
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this.status = 0x50;
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this.push_irq();
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break;
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case 0x91:
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