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// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT.
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(AbsInt8x16 ...) => (VPABSB128 ...)
(AbsInt8x32 ...) => (VPABSB256 ...)
(AbsInt8x64 ...) => (VPABSB512 ...)
(AbsInt16x8 ...) => (VPABSW128 ...)
(AbsInt16x16 ...) => (VPABSW256 ...)
(AbsInt16x32 ...) => (VPABSW512 ...)
(AbsInt32x4 ...) => (VPABSD128 ...)
(AbsInt32x8 ...) => (VPABSD256 ...)
(AbsInt32x16 ...) => (VPABSD512 ...)
(AbsInt64x2 ...) => (VPABSQ128 ...)
(AbsInt64x4 ...) => (VPABSQ256 ...)
(AbsInt64x8 ...) => (VPABSQ512 ...)
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(AddFloat32x4 ...) => (VADDPS128 ...)
(AddFloat32x8 ...) => (VADDPS256 ...)
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(AddFloat32x16 ...) => (VADDPS512 ...)
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(AddFloat64x2 ...) => (VADDPD128 ...)
(AddFloat64x4 ...) => (VADDPD256 ...)
(AddFloat64x8 ...) => (VADDPD512 ...)
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(AddInt8x16 ...) => (VPADDB128 ...)
(AddInt8x32 ...) => (VPADDB256 ...)
(AddInt8x64 ...) => (VPADDB512 ...)
(AddInt16x8 ...) => (VPADDW128 ...)
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(AddInt16x16 ...) => (VPADDW256 ...)
(AddInt16x32 ...) => (VPADDW512 ...)
(AddInt32x4 ...) => (VPADDD128 ...)
(AddInt32x8 ...) => (VPADDD256 ...)
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(AddInt32x16 ...) => (VPADDD512 ...)
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(AddInt64x2 ...) => (VPADDQ128 ...)
(AddInt64x4 ...) => (VPADDQ256 ...)
(AddInt64x8 ...) => (VPADDQ512 ...)
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(AddUint8x16 ...) => (VPADDB128 ...)
(AddUint8x32 ...) => (VPADDB256 ...)
(AddUint8x64 ...) => (VPADDB512 ...)
(AddUint16x8 ...) => (VPADDW128 ...)
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(AddUint16x16 ...) => (VPADDW256 ...)
(AddUint16x32 ...) => (VPADDW512 ...)
(AddUint32x4 ...) => (VPADDD128 ...)
(AddUint32x8 ...) => (VPADDD256 ...)
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(AddUint32x16 ...) => (VPADDD512 ...)
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(AddUint64x2 ...) => (VPADDQ128 ...)
(AddUint64x4 ...) => (VPADDQ256 ...)
(AddUint64x8 ...) => (VPADDQ512 ...)
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(AddDotProdPairsSaturatedInt32x4 ...) => (VPDPWSSDS128 ...)
(AddDotProdPairsSaturatedInt32x8 ...) => (VPDPWSSDS256 ...)
(AddDotProdPairsSaturatedInt32x16 ...) => (VPDPWSSDS512 ...)
(AddDotProdQuadrupleInt32x4 ...) => (VPDPBUSD128 ...)
(AddDotProdQuadrupleInt32x8 ...) => (VPDPBUSD256 ...)
(AddDotProdQuadrupleInt32x16 ...) => (VPDPBUSD512 ...)
(AddDotProdQuadrupleSaturatedInt32x4 ...) => (VPDPBUSDS128 ...)
(AddDotProdQuadrupleSaturatedInt32x8 ...) => (VPDPBUSDS256 ...)
(AddDotProdQuadrupleSaturatedInt32x16 ...) => (VPDPBUSDS512 ...)
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(AddPairsFloat32x4 ...) => (VHADDPS128 ...)
(AddPairsFloat32x8 ...) => (VHADDPS256 ...)
(AddPairsFloat64x2 ...) => (VHADDPD128 ...)
(AddPairsFloat64x4 ...) => (VHADDPD256 ...)
(AddPairsInt16x8 ...) => (VPHADDW128 ...)
(AddPairsInt16x16 ...) => (VPHADDW256 ...)
(AddPairsInt32x4 ...) => (VPHADDD128 ...)
(AddPairsInt32x8 ...) => (VPHADDD256 ...)
(AddPairsUint16x8 ...) => (VPHADDW128 ...)
(AddPairsUint16x16 ...) => (VPHADDW256 ...)
(AddPairsUint32x4 ...) => (VPHADDD128 ...)
(AddPairsUint32x8 ...) => (VPHADDD256 ...)
(AddPairsSaturatedInt16x8 ...) => (VPHADDSW128 ...)
(AddPairsSaturatedInt16x16 ...) => (VPHADDSW256 ...)
(AddSaturatedInt8x16 ...) => (VPADDSB128 ...)
(AddSaturatedInt8x32 ...) => (VPADDSB256 ...)
(AddSaturatedInt8x64 ...) => (VPADDSB512 ...)
(AddSaturatedInt16x8 ...) => (VPADDSW128 ...)
(AddSaturatedInt16x16 ...) => (VPADDSW256 ...)
(AddSaturatedInt16x32 ...) => (VPADDSW512 ...)
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(AddSaturatedUint8x16 ...) => (VPADDUSB128 ...)
(AddSaturatedUint8x32 ...) => (VPADDUSB256 ...)
(AddSaturatedUint8x64 ...) => (VPADDUSB512 ...)
(AddSaturatedUint16x8 ...) => (VPADDUSW128 ...)
(AddSaturatedUint16x16 ...) => (VPADDUSW256 ...)
(AddSaturatedUint16x32 ...) => (VPADDUSW512 ...)
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(AddSubFloat32x4 ...) => (VADDSUBPS128 ...)
(AddSubFloat32x8 ...) => (VADDSUBPS256 ...)
(AddSubFloat64x2 ...) => (VADDSUBPD128 ...)
(AddSubFloat64x4 ...) => (VADDSUBPD256 ...)
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(AndInt8x16 ...) => (VPAND128 ...)
(AndInt8x32 ...) => (VPAND256 ...)
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(AndInt8x64 ...) => (VPANDD512 ...)
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(AndInt16x8 ...) => (VPAND128 ...)
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(AndInt16x16 ...) => (VPAND256 ...)
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(AndInt16x32 ...) => (VPANDD512 ...)
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(AndInt32x4 ...) => (VPAND128 ...)
(AndInt32x8 ...) => (VPAND256 ...)
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(AndInt32x16 ...) => (VPANDD512 ...)
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(AndInt64x2 ...) => (VPAND128 ...)
(AndInt64x4 ...) => (VPAND256 ...)
(AndInt64x8 ...) => (VPANDQ512 ...)
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(AndUint8x16 ...) => (VPAND128 ...)
(AndUint8x32 ...) => (VPAND256 ...)
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(AndUint8x64 ...) => (VPANDD512 ...)
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(AndUint16x8 ...) => (VPAND128 ...)
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(AndUint16x16 ...) => (VPAND256 ...)
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(AndUint16x32 ...) => (VPANDD512 ...)
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(AndUint32x4 ...) => (VPAND128 ...)
(AndUint32x8 ...) => (VPAND256 ...)
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(AndUint32x16 ...) => (VPANDD512 ...)
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(AndUint64x2 ...) => (VPAND128 ...)
(AndUint64x4 ...) => (VPAND256 ...)
(AndUint64x8 ...) => (VPANDQ512 ...)
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(AndNotInt8x16 ...) => (VPANDN128 ...)
(AndNotInt8x32 ...) => (VPANDN256 ...)
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(AndNotInt8x64 ...) => (VPANDND512 ...)
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(AndNotInt16x8 ...) => (VPANDN128 ...)
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(AndNotInt16x16 ...) => (VPANDN256 ...)
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(AndNotInt16x32 ...) => (VPANDND512 ...)
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(AndNotInt32x4 ...) => (VPANDN128 ...)
(AndNotInt32x8 ...) => (VPANDN256 ...)
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(AndNotInt32x16 ...) => (VPANDND512 ...)
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(AndNotInt64x2 ...) => (VPANDN128 ...)
(AndNotInt64x4 ...) => (VPANDN256 ...)
(AndNotInt64x8 ...) => (VPANDNQ512 ...)
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(AndNotUint8x16 ...) => (VPANDN128 ...)
(AndNotUint8x32 ...) => (VPANDN256 ...)
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(AndNotUint8x64 ...) => (VPANDND512 ...)
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(AndNotUint16x8 ...) => (VPANDN128 ...)
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(AndNotUint16x16 ...) => (VPANDN256 ...)
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(AndNotUint16x32 ...) => (VPANDND512 ...)
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(AndNotUint32x4 ...) => (VPANDN128 ...)
(AndNotUint32x8 ...) => (VPANDN256 ...)
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(AndNotUint32x16 ...) => (VPANDND512 ...)
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(AndNotUint64x2 ...) => (VPANDN128 ...)
(AndNotUint64x4 ...) => (VPANDN256 ...)
(AndNotUint64x8 ...) => (VPANDNQ512 ...)
(AverageUint8x16 ...) => (VPAVGB128 ...)
(AverageUint8x32 ...) => (VPAVGB256 ...)
(AverageUint8x64 ...) => (VPAVGB512 ...)
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(AverageUint16x8 ...) => (VPAVGW128 ...)
(AverageUint16x16 ...) => (VPAVGW256 ...)
(AverageUint16x32 ...) => (VPAVGW512 ...)
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(Broadcast128Float32x4 ...) => (VBROADCASTSS128 ...)
(Broadcast128Float64x2 ...) => (VPBROADCASTQ128 ...)
(Broadcast128Int8x16 ...) => (VPBROADCASTB128 ...)
(Broadcast128Int16x8 ...) => (VPBROADCASTW128 ...)
(Broadcast128Int32x4 ...) => (VPBROADCASTD128 ...)
(Broadcast128Int64x2 ...) => (VPBROADCASTQ128 ...)
(Broadcast128Uint8x16 ...) => (VPBROADCASTB128 ...)
(Broadcast128Uint16x8 ...) => (VPBROADCASTW128 ...)
(Broadcast128Uint32x4 ...) => (VPBROADCASTD128 ...)
(Broadcast128Uint64x2 ...) => (VPBROADCASTQ128 ...)
(Broadcast256Float32x4 ...) => (VBROADCASTSS256 ...)
(Broadcast256Float64x2 ...) => (VBROADCASTSD256 ...)
(Broadcast256Int8x16 ...) => (VPBROADCASTB256 ...)
(Broadcast256Int16x8 ...) => (VPBROADCASTW256 ...)
(Broadcast256Int32x4 ...) => (VPBROADCASTD256 ...)
(Broadcast256Int64x2 ...) => (VPBROADCASTQ256 ...)
(Broadcast256Uint8x16 ...) => (VPBROADCASTB256 ...)
(Broadcast256Uint16x8 ...) => (VPBROADCASTW256 ...)
(Broadcast256Uint32x4 ...) => (VPBROADCASTD256 ...)
(Broadcast256Uint64x2 ...) => (VPBROADCASTQ256 ...)
(Broadcast512Float32x4 ...) => (VBROADCASTSS512 ...)
(Broadcast512Float64x2 ...) => (VBROADCASTSD512 ...)
(Broadcast512Int8x16 ...) => (VPBROADCASTB512 ...)
(Broadcast512Int16x8 ...) => (VPBROADCASTW512 ...)
(Broadcast512Int32x4 ...) => (VPBROADCASTD512 ...)
(Broadcast512Int64x2 ...) => (VPBROADCASTQ512 ...)
(Broadcast512Uint8x16 ...) => (VPBROADCASTB512 ...)
(Broadcast512Uint16x8 ...) => (VPBROADCASTW512 ...)
(Broadcast512Uint32x4 ...) => (VPBROADCASTD512 ...)
(Broadcast512Uint64x2 ...) => (VPBROADCASTQ512 ...)
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(CeilFloat32x4 x) => (VROUNDPS128 [2] x)
(CeilFloat32x8 x) => (VROUNDPS256 [2] x)
(CeilFloat64x2 x) => (VROUNDPD128 [2] x)
(CeilFloat64x4 x) => (VROUNDPD256 [2] x)
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(CeilScaledFloat32x4 [a] x) => (VRNDSCALEPS128 [a+2] x)
(CeilScaledFloat32x8 [a] x) => (VRNDSCALEPS256 [a+2] x)
(CeilScaledFloat32x16 [a] x) => (VRNDSCALEPS512 [a+2] x)
(CeilScaledFloat64x2 [a] x) => (VRNDSCALEPD128 [a+2] x)
(CeilScaledFloat64x4 [a] x) => (VRNDSCALEPD256 [a+2] x)
(CeilScaledFloat64x8 [a] x) => (VRNDSCALEPD512 [a+2] x)
(CeilScaledResidueFloat32x4 [a] x) => (VREDUCEPS128 [a+2] x)
(CeilScaledResidueFloat32x8 [a] x) => (VREDUCEPS256 [a+2] x)
(CeilScaledResidueFloat32x16 [a] x) => (VREDUCEPS512 [a+2] x)
(CeilScaledResidueFloat64x2 [a] x) => (VREDUCEPD128 [a+2] x)
(CeilScaledResidueFloat64x4 [a] x) => (VREDUCEPD256 [a+2] x)
(CeilScaledResidueFloat64x8 [a] x) => (VREDUCEPD512 [a+2] x)
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(CompressFloat32x4 x mask) => (VCOMPRESSPSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
(CompressFloat32x8 x mask) => (VCOMPRESSPSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
(CompressFloat32x16 x mask) => (VCOMPRESSPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
(CompressFloat64x2 x mask) => (VCOMPRESSPDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
(CompressFloat64x4 x mask) => (VCOMPRESSPDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
(CompressFloat64x8 x mask) => (VCOMPRESSPDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
(CompressInt8x16 x mask) => (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
(CompressInt8x32 x mask) => (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
(CompressInt8x64 x mask) => (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
(CompressInt16x8 x mask) => (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
(CompressInt16x16 x mask) => (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
(CompressInt16x32 x mask) => (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
(CompressInt32x4 x mask) => (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
(CompressInt32x8 x mask) => (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
(CompressInt32x16 x mask) => (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
(CompressInt64x2 x mask) => (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
(CompressInt64x4 x mask) => (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
(CompressInt64x8 x mask) => (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
(CompressUint8x16 x mask) => (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
(CompressUint8x32 x mask) => (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
(CompressUint8x64 x mask) => (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
(CompressUint16x8 x mask) => (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
(CompressUint16x16 x mask) => (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
(CompressUint16x32 x mask) => (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
(CompressUint32x4 x mask) => (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
(CompressUint32x8 x mask) => (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
(CompressUint32x16 x mask) => (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
(CompressUint64x2 x mask) => (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
(CompressUint64x4 x mask) => (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
(CompressUint64x8 x mask) => (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
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(ConvertToInt8Int16x8 ...) => (VPMOVWB128 ...)
(ConvertToInt8Int16x16 ...) => (VPMOVWB128 ...)
(ConvertToInt8Int16x32 ...) => (VPMOVWB256 ...)
(ConvertToInt8Int32x4 ...) => (VPMOVDB128 ...)
(ConvertToInt8Int32x8 ...) => (VPMOVDB128 ...)
(ConvertToInt8Int32x16 ...) => (VPMOVDB128 ...)
(ConvertToInt8Int64x2 ...) => (VPMOVQB128 ...)
(ConvertToInt8Int64x4 ...) => (VPMOVQB128 ...)
(ConvertToInt8Int64x8 ...) => (VPMOVQB128 ...)
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(ConvertToInt8SaturatedInt16x8 ...) => (VPMOVSWB128 ...)
(ConvertToInt8SaturatedInt16x16 ...) => (VPMOVSWB128 ...)
(ConvertToInt8SaturatedInt16x32 ...) => (VPMOVSWB256 ...)
(ConvertToInt8SaturatedInt32x4 ...) => (VPMOVSDB128 ...)
(ConvertToInt8SaturatedInt32x8 ...) => (VPMOVSDB128 ...)
(ConvertToInt8SaturatedInt32x16 ...) => (VPMOVSDB128 ...)
(ConvertToInt8SaturatedInt64x2 ...) => (VPMOVSQB128 ...)
(ConvertToInt8SaturatedInt64x4 ...) => (VPMOVSQB128 ...)
(ConvertToInt8SaturatedInt64x8 ...) => (VPMOVSQB128 ...)
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(ConvertToInt16Int8x16 ...) => (VPMOVSXBW256 ...)
(ConvertToInt16Int8x32 ...) => (VPMOVSXBW512 ...)
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(ConvertToInt16Int32x4 ...) => (VPMOVDW128 ...)
(ConvertToInt16Int32x8 ...) => (VPMOVDW128 ...)
(ConvertToInt16Int32x16 ...) => (VPMOVDW256 ...)
(ConvertToInt16Int64x2 ...) => (VPMOVQW128 ...)
(ConvertToInt16Int64x4 ...) => (VPMOVQW128 ...)
(ConvertToInt16Int64x8 ...) => (VPMOVQW128 ...)
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(ConvertToInt16SaturatedInt32x4 ...) => (VPMOVSDW128 ...)
(ConvertToInt16SaturatedInt32x8 ...) => (VPMOVSDW128 ...)
(ConvertToInt16SaturatedInt32x16 ...) => (VPMOVSDW256 ...)
(ConvertToInt16SaturatedInt64x2 ...) => (VPMOVSQW128 ...)
(ConvertToInt16SaturatedInt64x4 ...) => (VPMOVSQW128 ...)
(ConvertToInt16SaturatedInt64x8 ...) => (VPMOVSQW128 ...)
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(ConvertToInt16SaturatedPackedInt32x4 ...) => (VPACKSSDW128 ...)
(ConvertToInt16SaturatedPackedInt32x8 ...) => (VPACKSSDW256 ...)
(ConvertToInt16SaturatedPackedInt32x16 ...) => (VPACKSSDW512 ...)
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(ConvertToInt16x8Int8x16 ...) => (VPMOVSXBW128 ...)
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(ConvertToInt32Float32x4 ...) => (VCVTTPS2DQ128 ...)
(ConvertToInt32Float32x8 ...) => (VCVTTPS2DQ256 ...)
(ConvertToInt32Float32x16 ...) => (VCVTTPS2DQ512 ...)
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(ConvertToInt32Int8x16 ...) => (VPMOVSXBD512 ...)
(ConvertToInt32Int16x8 ...) => (VPMOVSXWD256 ...)
(ConvertToInt32Int16x16 ...) => (VPMOVSXWD512 ...)
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(ConvertToInt32Int64x2 ...) => (VPMOVQD128 ...)
(ConvertToInt32Int64x4 ...) => (VPMOVQD128 ...)
(ConvertToInt32Int64x8 ...) => (VPMOVQD256 ...)
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(ConvertToInt32SaturatedInt64x2 ...) => (VPMOVSQD128 ...)
(ConvertToInt32SaturatedInt64x4 ...) => (VPMOVSQD128 ...)
(ConvertToInt32SaturatedInt64x8 ...) => (VPMOVSQD256 ...)
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(ConvertToInt32x4Int8x16 ...) => (VPMOVSXBD128 ...)
(ConvertToInt32x4Int16x8 ...) => (VPMOVSXWD128 ...)
(ConvertToInt32x8Int8x16 ...) => (VPMOVSXBD256 ...)
(ConvertToInt64Int16x8 ...) => (VPMOVSXWQ512 ...)
(ConvertToInt64Int32x4 ...) => (VPMOVSXDQ256 ...)
(ConvertToInt64Int32x8 ...) => (VPMOVSXDQ512 ...)
(ConvertToInt64x2Int8x16 ...) => (VPMOVSXBQ128 ...)
(ConvertToInt64x2Int16x8 ...) => (VPMOVSXWQ128 ...)
(ConvertToInt64x2Int32x4 ...) => (VPMOVSXDQ128 ...)
(ConvertToInt64x4Int8x16 ...) => (VPMOVSXBQ256 ...)
(ConvertToInt64x8Int8x16 ...) => (VPMOVSXBQ512 ...)
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(ConvertToUint8Uint16x8 ...) => (VPMOVWB128 ...)
(ConvertToUint8Uint16x16 ...) => (VPMOVWB128 ...)
(ConvertToUint8Uint16x32 ...) => (VPMOVWB256 ...)
(ConvertToUint8Uint32x4 ...) => (VPMOVDB128 ...)
(ConvertToUint8Uint32x8 ...) => (VPMOVDB128 ...)
(ConvertToUint8Uint32x16 ...) => (VPMOVDB128 ...)
(ConvertToUint8Uint64x2 ...) => (VPMOVQB128 ...)
(ConvertToUint8Uint64x4 ...) => (VPMOVQB128 ...)
(ConvertToUint8Uint64x8 ...) => (VPMOVQB128 ...)
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(ConvertToUint8SaturatedUint16x8 ...) => (VPMOVUSWB128 ...)
(ConvertToUint8SaturatedUint16x16 ...) => (VPMOVUSWB128 ...)
(ConvertToUint8SaturatedUint16x32 ...) => (VPMOVUSWB256 ...)
(ConvertToUint8SaturatedUint32x4 ...) => (VPMOVUSDB128 ...)
(ConvertToUint8SaturatedUint32x8 ...) => (VPMOVUSDB128 ...)
(ConvertToUint8SaturatedUint32x16 ...) => (VPMOVUSDB128 ...)
(ConvertToUint8SaturatedUint64x2 ...) => (VPMOVUSQB128 ...)
(ConvertToUint8SaturatedUint64x4 ...) => (VPMOVUSQB128 ...)
(ConvertToUint8SaturatedUint64x8 ...) => (VPMOVUSQB128 ...)
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(ConvertToUint16Uint8x16 ...) => (VPMOVZXBW256 ...)
(ConvertToUint16Uint8x32 ...) => (VPMOVZXBW512 ...)
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(ConvertToUint16Uint32x4 ...) => (VPMOVDW128 ...)
(ConvertToUint16Uint32x8 ...) => (VPMOVDW128 ...)
(ConvertToUint16Uint32x16 ...) => (VPMOVDW256 ...)
(ConvertToUint16Uint64x2 ...) => (VPMOVQW128 ...)
(ConvertToUint16Uint64x4 ...) => (VPMOVQW128 ...)
(ConvertToUint16Uint64x8 ...) => (VPMOVQW128 ...)
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(ConvertToUint16SaturatedUint32x4 ...) => (VPMOVUSDW128 ...)
(ConvertToUint16SaturatedUint32x8 ...) => (VPMOVUSDW128 ...)
(ConvertToUint16SaturatedUint32x16 ...) => (VPMOVUSDW256 ...)
(ConvertToUint16SaturatedUint64x2 ...) => (VPMOVUSQW128 ...)
(ConvertToUint16SaturatedUint64x4 ...) => (VPMOVUSQW128 ...)
(ConvertToUint16SaturatedUint64x8 ...) => (VPMOVUSQW128 ...)
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(ConvertToUint16SaturatedPackedUint32x4 ...) => (VPACKUSDW128 ...)
(ConvertToUint16SaturatedPackedUint32x8 ...) => (VPACKUSDW256 ...)
(ConvertToUint16SaturatedPackedUint32x16 ...) => (VPACKUSDW512 ...)
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(ConvertToUint16x8Uint8x16 ...) => (VPMOVZXBW128 ...)
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(ConvertToUint32Float32x4 ...) => (VCVTPS2UDQ128 ...)
(ConvertToUint32Float32x8 ...) => (VCVTPS2UDQ256 ...)
(ConvertToUint32Float32x16 ...) => (VCVTPS2UDQ512 ...)
2025-08-21 02:47:53 +00:00
(ConvertToUint32Uint8x16 ...) => (VPMOVZXBD512 ...)
2025-08-15 17:05:05 -04:00
(ConvertToUint32Uint16x8 ...) => (VPMOVZXWD256 ...)
(ConvertToUint32Uint16x16 ...) => (VPMOVZXWD512 ...)
2025-08-21 04:33:46 +00:00
(ConvertToUint32Uint64x2 ...) => (VPMOVQD128 ...)
(ConvertToUint32Uint64x4 ...) => (VPMOVQD128 ...)
(ConvertToUint32Uint64x8 ...) => (VPMOVQD256 ...)
2025-08-21 17:33:50 +00:00
(ConvertToUint32SaturatedUint64x2 ...) => (VPMOVUSQD128 ...)
(ConvertToUint32SaturatedUint64x4 ...) => (VPMOVUSQD128 ...)
(ConvertToUint32SaturatedUint64x8 ...) => (VPMOVUSQD256 ...)
2025-08-21 02:47:53 +00:00
(ConvertToUint32x4Uint8x16 ...) => (VPMOVZXBD128 ...)
2025-08-15 17:05:05 -04:00
(ConvertToUint32x4Uint16x8 ...) => (VPMOVZXWD128 ...)
2025-08-21 02:47:53 +00:00
(ConvertToUint32x8Uint8x16 ...) => (VPMOVZXBD256 ...)
(ConvertToUint64Uint16x8 ...) => (VPMOVZXWQ512 ...)
(ConvertToUint64Uint32x4 ...) => (VPMOVZXDQ256 ...)
(ConvertToUint64Uint32x8 ...) => (VPMOVZXDQ512 ...)
(ConvertToUint64x2Uint8x16 ...) => (VPMOVZXBQ128 ...)
(ConvertToUint64x2Uint16x8 ...) => (VPMOVZXWQ128 ...)
(ConvertToUint64x2Uint32x4 ...) => (VPMOVZXDQ128 ...)
(ConvertToUint64x4Int16x8 ...) => (VPMOVSXWQ256 ...)
(ConvertToUint64x4Uint8x16 ...) => (VPMOVZXBQ256 ...)
(ConvertToUint64x4Uint16x8 ...) => (VPMOVZXWQ256 ...)
(ConvertToUint64x8Uint8x16 ...) => (VPMOVZXBQ512 ...)
2025-08-07 17:05:50 +00:00
(CopySignInt8x16 ...) => (VPSIGNB128 ...)
(CopySignInt8x32 ...) => (VPSIGNB256 ...)
(CopySignInt16x8 ...) => (VPSIGNW128 ...)
(CopySignInt16x16 ...) => (VPSIGNW256 ...)
(CopySignInt32x4 ...) => (VPSIGND128 ...)
(CopySignInt32x8 ...) => (VPSIGND256 ...)
2025-06-12 03:54:34 +00:00
(DivFloat32x4 ...) => (VDIVPS128 ...)
(DivFloat32x8 ...) => (VDIVPS256 ...)
2025-06-25 15:58:17 -04:00
(DivFloat32x16 ...) => (VDIVPS512 ...)
2025-06-12 03:54:34 +00:00
(DivFloat64x2 ...) => (VDIVPD128 ...)
(DivFloat64x4 ...) => (VDIVPD256 ...)
(DivFloat64x8 ...) => (VDIVPD512 ...)
2025-08-07 17:05:50 +00:00
(DotProdPairsInt16x8 ...) => (VPMADDWD128 ...)
(DotProdPairsInt16x16 ...) => (VPMADDWD256 ...)
(DotProdPairsInt16x32 ...) => (VPMADDWD512 ...)
(DotProdPairsSaturatedUint8x16 ...) => (VPMADDUBSW128 ...)
(DotProdPairsSaturatedUint8x32 ...) => (VPMADDUBSW256 ...)
(DotProdPairsSaturatedUint8x64 ...) => (VPMADDUBSW512 ...)
2025-06-12 03:54:34 +00:00
(EqualFloat32x4 x y) => (VCMPPS128 [0] x y)
(EqualFloat32x8 x y) => (VCMPPS256 [0] x y)
2025-06-25 15:58:17 -04:00
(EqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [0] x y))
2025-06-12 03:54:34 +00:00
(EqualFloat64x2 x y) => (VCMPPD128 [0] x y)
(EqualFloat64x4 x y) => (VCMPPD256 [0] x y)
(EqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [0] x y))
2025-06-25 15:58:17 -04:00
(EqualInt8x16 ...) => (VPCMPEQB128 ...)
(EqualInt8x32 ...) => (VPCMPEQB256 ...)
2025-07-23 07:37:14 +00:00
(EqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPEQB512 x y))
2025-06-25 15:58:17 -04:00
(EqualInt16x8 ...) => (VPCMPEQW128 ...)
2025-06-12 03:54:34 +00:00
(EqualInt16x16 ...) => (VPCMPEQW256 ...)
2025-07-23 07:37:14 +00:00
(EqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPEQW512 x y))
2025-06-12 03:54:34 +00:00
(EqualInt32x4 ...) => (VPCMPEQD128 ...)
(EqualInt32x8 ...) => (VPCMPEQD256 ...)
2025-07-23 07:37:14 +00:00
(EqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPEQD512 x y))
2025-06-12 03:54:34 +00:00
(EqualInt64x2 ...) => (VPCMPEQQ128 ...)
(EqualInt64x4 ...) => (VPCMPEQQ256 ...)
2025-07-23 07:37:14 +00:00
(EqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPEQQ512 x y))
2025-07-09 16:24:34 +00:00
(EqualUint8x16 ...) => (VPCMPEQB128 ...)
(EqualUint8x32 ...) => (VPCMPEQB256 ...)
2025-07-23 07:37:14 +00:00
(EqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPEQB512 x y))
2025-07-09 16:24:34 +00:00
(EqualUint16x8 ...) => (VPCMPEQW128 ...)
(EqualUint16x16 ...) => (VPCMPEQW256 ...)
2025-07-23 07:37:14 +00:00
(EqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPEQW512 x y))
2025-07-09 16:24:34 +00:00
(EqualUint32x4 ...) => (VPCMPEQD128 ...)
(EqualUint32x8 ...) => (VPCMPEQD256 ...)
2025-07-23 07:37:14 +00:00
(EqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPEQD512 x y))
2025-07-09 16:24:34 +00:00
(EqualUint64x2 ...) => (VPCMPEQQ128 ...)
(EqualUint64x4 ...) => (VPCMPEQQ256 ...)
2025-07-23 07:37:14 +00:00
(EqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPEQQ512 x y))
2025-08-05 19:42:12 +00:00
(ExpandFloat32x4 x mask) => (VEXPANDPSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
(ExpandFloat32x8 x mask) => (VEXPANDPSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
(ExpandFloat32x16 x mask) => (VEXPANDPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
(ExpandFloat64x2 x mask) => (VEXPANDPDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
(ExpandFloat64x4 x mask) => (VEXPANDPDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
(ExpandFloat64x8 x mask) => (VEXPANDPDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
(ExpandInt8x16 x mask) => (VPEXPANDBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
(ExpandInt8x32 x mask) => (VPEXPANDBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
(ExpandInt8x64 x mask) => (VPEXPANDBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
(ExpandInt16x8 x mask) => (VPEXPANDWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
(ExpandInt16x16 x mask) => (VPEXPANDWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
(ExpandInt16x32 x mask) => (VPEXPANDWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
(ExpandInt32x4 x mask) => (VPEXPANDDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
(ExpandInt32x8 x mask) => (VPEXPANDDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
(ExpandInt32x16 x mask) => (VPEXPANDDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
(ExpandInt64x2 x mask) => (VPEXPANDQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
(ExpandInt64x4 x mask) => (VPEXPANDQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
(ExpandInt64x8 x mask) => (VPEXPANDQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
(ExpandUint8x16 x mask) => (VPEXPANDBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
(ExpandUint8x32 x mask) => (VPEXPANDBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
(ExpandUint8x64 x mask) => (VPEXPANDBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
(ExpandUint16x8 x mask) => (VPEXPANDWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
(ExpandUint16x16 x mask) => (VPEXPANDWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
(ExpandUint16x32 x mask) => (VPEXPANDWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
(ExpandUint32x4 x mask) => (VPEXPANDDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
(ExpandUint32x8 x mask) => (VPEXPANDDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
(ExpandUint32x16 x mask) => (VPEXPANDDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
(ExpandUint64x2 x mask) => (VPEXPANDQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
(ExpandUint64x4 x mask) => (VPEXPANDQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
(ExpandUint64x8 x mask) => (VPEXPANDQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
2025-06-12 16:21:35 +00:00
(FloorFloat32x4 x) => (VROUNDPS128 [1] x)
(FloorFloat32x8 x) => (VROUNDPS256 [1] x)
(FloorFloat64x2 x) => (VROUNDPD128 [1] x)
(FloorFloat64x4 x) => (VROUNDPD256 [1] x)
2025-08-01 15:58:29 -04:00
(FloorScaledFloat32x4 [a] x) => (VRNDSCALEPS128 [a+1] x)
(FloorScaledFloat32x8 [a] x) => (VRNDSCALEPS256 [a+1] x)
(FloorScaledFloat32x16 [a] x) => (VRNDSCALEPS512 [a+1] x)
(FloorScaledFloat64x2 [a] x) => (VRNDSCALEPD128 [a+1] x)
(FloorScaledFloat64x4 [a] x) => (VRNDSCALEPD256 [a+1] x)
(FloorScaledFloat64x8 [a] x) => (VRNDSCALEPD512 [a+1] x)
(FloorScaledResidueFloat32x4 [a] x) => (VREDUCEPS128 [a+1] x)
(FloorScaledResidueFloat32x8 [a] x) => (VREDUCEPS256 [a+1] x)
(FloorScaledResidueFloat32x16 [a] x) => (VREDUCEPS512 [a+1] x)
(FloorScaledResidueFloat64x2 [a] x) => (VREDUCEPD128 [a+1] x)
(FloorScaledResidueFloat64x4 [a] x) => (VREDUCEPD256 [a+1] x)
(FloorScaledResidueFloat64x8 [a] x) => (VREDUCEPD512 [a+1] x)
2025-07-08 12:52:30 -04:00
(GaloisFieldAffineTransformUint8x16 ...) => (VGF2P8AFFINEQB128 ...)
(GaloisFieldAffineTransformUint8x32 ...) => (VGF2P8AFFINEQB256 ...)
(GaloisFieldAffineTransformUint8x64 ...) => (VGF2P8AFFINEQB512 ...)
2025-07-11 02:11:22 +00:00
(GaloisFieldAffineTransformInverseUint8x16 ...) => (VGF2P8AFFINEINVQB128 ...)
(GaloisFieldAffineTransformInverseUint8x32 ...) => (VGF2P8AFFINEINVQB256 ...)
(GaloisFieldAffineTransformInverseUint8x64 ...) => (VGF2P8AFFINEINVQB512 ...)
2025-06-26 04:07:48 +00:00
(GaloisFieldMulUint8x16 ...) => (VGF2P8MULB128 ...)
(GaloisFieldMulUint8x32 ...) => (VGF2P8MULB256 ...)
(GaloisFieldMulUint8x64 ...) => (VGF2P8MULB512 ...)
2025-08-14 17:26:15 -04:00
(GetElemFloat32x4 ...) => (VPEXTRD128 ...)
(GetElemFloat64x2 ...) => (VPEXTRQ128 ...)
2025-07-08 12:52:30 -04:00
(GetElemInt8x16 ...) => (VPEXTRB128 ...)
(GetElemInt16x8 ...) => (VPEXTRW128 ...)
(GetElemInt32x4 ...) => (VPEXTRD128 ...)
(GetElemInt64x2 ...) => (VPEXTRQ128 ...)
(GetElemUint8x16 ...) => (VPEXTRB128 ...)
(GetElemUint16x8 ...) => (VPEXTRW128 ...)
(GetElemUint32x4 ...) => (VPEXTRD128 ...)
(GetElemUint64x2 ...) => (VPEXTRQ128 ...)
2025-08-05 19:07:51 +00:00
(GetHiFloat32x8 x) => (VEXTRACTF128128 [1] x)
(GetHiFloat32x16 x) => (VEXTRACTF64X4256 [1] x)
(GetHiFloat64x4 x) => (VEXTRACTF128128 [1] x)
(GetHiFloat64x8 x) => (VEXTRACTF64X4256 [1] x)
(GetHiInt8x32 x) => (VEXTRACTI128128 [1] x)
(GetHiInt8x64 x) => (VEXTRACTI64X4256 [1] x)
(GetHiInt16x16 x) => (VEXTRACTI128128 [1] x)
(GetHiInt16x32 x) => (VEXTRACTI64X4256 [1] x)
(GetHiInt32x8 x) => (VEXTRACTI128128 [1] x)
(GetHiInt32x16 x) => (VEXTRACTI64X4256 [1] x)
(GetHiInt64x4 x) => (VEXTRACTI128128 [1] x)
(GetHiInt64x8 x) => (VEXTRACTI64X4256 [1] x)
(GetHiUint8x32 x) => (VEXTRACTI128128 [1] x)
(GetHiUint8x64 x) => (VEXTRACTI64X4256 [1] x)
(GetHiUint16x16 x) => (VEXTRACTI128128 [1] x)
(GetHiUint16x32 x) => (VEXTRACTI64X4256 [1] x)
(GetHiUint32x8 x) => (VEXTRACTI128128 [1] x)
(GetHiUint32x16 x) => (VEXTRACTI64X4256 [1] x)
(GetHiUint64x4 x) => (VEXTRACTI128128 [1] x)
(GetHiUint64x8 x) => (VEXTRACTI64X4256 [1] x)
(GetLoFloat32x8 x) => (VEXTRACTF128128 [0] x)
(GetLoFloat32x16 x) => (VEXTRACTF64X4256 [0] x)
(GetLoFloat64x4 x) => (VEXTRACTF128128 [0] x)
(GetLoFloat64x8 x) => (VEXTRACTF64X4256 [0] x)
(GetLoInt8x32 x) => (VEXTRACTI128128 [0] x)
(GetLoInt8x64 x) => (VEXTRACTI64X4256 [0] x)
(GetLoInt16x16 x) => (VEXTRACTI128128 [0] x)
(GetLoInt16x32 x) => (VEXTRACTI64X4256 [0] x)
(GetLoInt32x8 x) => (VEXTRACTI128128 [0] x)
(GetLoInt32x16 x) => (VEXTRACTI64X4256 [0] x)
(GetLoInt64x4 x) => (VEXTRACTI128128 [0] x)
(GetLoInt64x8 x) => (VEXTRACTI64X4256 [0] x)
(GetLoUint8x32 x) => (VEXTRACTI128128 [0] x)
(GetLoUint8x64 x) => (VEXTRACTI64X4256 [0] x)
(GetLoUint16x16 x) => (VEXTRACTI128128 [0] x)
(GetLoUint16x32 x) => (VEXTRACTI64X4256 [0] x)
(GetLoUint32x8 x) => (VEXTRACTI128128 [0] x)
(GetLoUint32x16 x) => (VEXTRACTI64X4256 [0] x)
(GetLoUint64x4 x) => (VEXTRACTI128128 [0] x)
(GetLoUint64x8 x) => (VEXTRACTI64X4256 [0] x)
2025-07-08 02:41:33 +00:00
(GreaterFloat32x4 x y) => (VCMPPS128 [14] x y)
(GreaterFloat32x8 x y) => (VCMPPS256 [14] x y)
(GreaterFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [14] x y))
(GreaterFloat64x2 x y) => (VCMPPD128 [14] x y)
(GreaterFloat64x4 x y) => (VCMPPD256 [14] x y)
(GreaterFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [14] x y))
2025-06-25 15:58:17 -04:00
(GreaterInt8x16 ...) => (VPCMPGTB128 ...)
(GreaterInt8x32 ...) => (VPCMPGTB256 ...)
2025-07-23 07:37:14 +00:00
(GreaterInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPGTB512 x y))
2025-06-25 15:58:17 -04:00
(GreaterInt16x8 ...) => (VPCMPGTW128 ...)
2025-06-12 03:54:34 +00:00
(GreaterInt16x16 ...) => (VPCMPGTW256 ...)
2025-07-23 07:37:14 +00:00
(GreaterInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPGTW512 x y))
2025-06-12 03:54:34 +00:00
(GreaterInt32x4 ...) => (VPCMPGTD128 ...)
(GreaterInt32x8 ...) => (VPCMPGTD256 ...)
2025-07-23 07:37:14 +00:00
(GreaterInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPGTD512 x y))
2025-07-09 16:24:34 +00:00
(GreaterInt64x2 ...) => (VPCMPGTQ128 ...)
2025-06-12 03:54:34 +00:00
(GreaterInt64x4 ...) => (VPCMPGTQ256 ...)
2025-07-23 07:37:14 +00:00
(GreaterInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPGTQ512 x y))
2025-07-08 02:41:33 +00:00
(GreaterUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [14] x y))
(GreaterUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [14] x y))
(GreaterUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [14] x y))
(GreaterUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [14] x y))
(GreaterEqualFloat32x4 x y) => (VCMPPS128 [13] x y)
(GreaterEqualFloat32x8 x y) => (VCMPPS256 [13] x y)
(GreaterEqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [13] x y))
(GreaterEqualFloat64x2 x y) => (VCMPPD128 [13] x y)
(GreaterEqualFloat64x4 x y) => (VCMPPD256 [13] x y)
(GreaterEqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [13] x y))
(GreaterEqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [13] x y))
(GreaterEqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [13] x y))
(GreaterEqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [13] x y))
(GreaterEqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [13] x y))
(GreaterEqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [13] x y))
(GreaterEqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [13] x y))
(GreaterEqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [13] x y))
(GreaterEqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [13] x y))
2025-08-20 16:58:55 -04:00
(InterleaveHiInt16x8 ...) => (VPUNPCKHWD128 ...)
(InterleaveHiInt32x4 ...) => (VPUNPCKHDQ128 ...)
(InterleaveHiInt64x2 ...) => (VPUNPCKHQDQ128 ...)
(InterleaveHiUint16x8 ...) => (VPUNPCKHWD128 ...)
(InterleaveHiUint32x4 ...) => (VPUNPCKHDQ128 ...)
(InterleaveHiUint64x2 ...) => (VPUNPCKHQDQ128 ...)
(InterleaveHiGroupedInt16x16 ...) => (VPUNPCKHWD256 ...)
(InterleaveHiGroupedInt16x32 ...) => (VPUNPCKHWD512 ...)
(InterleaveHiGroupedInt32x8 ...) => (VPUNPCKHDQ256 ...)
(InterleaveHiGroupedInt32x16 ...) => (VPUNPCKHDQ512 ...)
(InterleaveHiGroupedInt64x4 ...) => (VPUNPCKHQDQ256 ...)
(InterleaveHiGroupedInt64x8 ...) => (VPUNPCKHQDQ512 ...)
(InterleaveHiGroupedUint16x16 ...) => (VPUNPCKHWD256 ...)
(InterleaveHiGroupedUint16x32 ...) => (VPUNPCKHWD512 ...)
(InterleaveHiGroupedUint32x8 ...) => (VPUNPCKHDQ256 ...)
(InterleaveHiGroupedUint32x16 ...) => (VPUNPCKHDQ512 ...)
(InterleaveHiGroupedUint64x4 ...) => (VPUNPCKHQDQ256 ...)
(InterleaveHiGroupedUint64x8 ...) => (VPUNPCKHQDQ512 ...)
(InterleaveLoInt16x8 ...) => (VPUNPCKLWD128 ...)
(InterleaveLoInt32x4 ...) => (VPUNPCKLDQ128 ...)
(InterleaveLoInt64x2 ...) => (VPUNPCKLQDQ128 ...)
(InterleaveLoUint16x8 ...) => (VPUNPCKLWD128 ...)
(InterleaveLoUint32x4 ...) => (VPUNPCKLDQ128 ...)
(InterleaveLoUint64x2 ...) => (VPUNPCKLQDQ128 ...)
(InterleaveLoGroupedInt16x16 ...) => (VPUNPCKLWD256 ...)
(InterleaveLoGroupedInt16x32 ...) => (VPUNPCKLWD512 ...)
(InterleaveLoGroupedInt32x8 ...) => (VPUNPCKLDQ256 ...)
(InterleaveLoGroupedInt32x16 ...) => (VPUNPCKLDQ512 ...)
(InterleaveLoGroupedInt64x4 ...) => (VPUNPCKLQDQ256 ...)
(InterleaveLoGroupedInt64x8 ...) => (VPUNPCKLQDQ512 ...)
(InterleaveLoGroupedUint16x16 ...) => (VPUNPCKLWD256 ...)
(InterleaveLoGroupedUint16x32 ...) => (VPUNPCKLWD512 ...)
(InterleaveLoGroupedUint32x8 ...) => (VPUNPCKLDQ256 ...)
(InterleaveLoGroupedUint32x16 ...) => (VPUNPCKLDQ512 ...)
(InterleaveLoGroupedUint64x4 ...) => (VPUNPCKLQDQ256 ...)
(InterleaveLoGroupedUint64x8 ...) => (VPUNPCKLQDQ512 ...)
2025-06-12 03:54:34 +00:00
(IsNanFloat32x4 x y) => (VCMPPS128 [3] x y)
(IsNanFloat32x8 x y) => (VCMPPS256 [3] x y)
2025-06-25 15:58:17 -04:00
(IsNanFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [3] x y))
2025-06-12 03:54:34 +00:00
(IsNanFloat64x2 x y) => (VCMPPD128 [3] x y)
(IsNanFloat64x4 x y) => (VCMPPD256 [3] x y)
(IsNanFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [3] x y))
2025-09-08 19:38:56 +00:00
(LeadingZerosInt32x4 ...) => (VPLZCNTD128 ...)
(LeadingZerosInt32x8 ...) => (VPLZCNTD256 ...)
(LeadingZerosInt32x16 ...) => (VPLZCNTD512 ...)
(LeadingZerosInt64x2 ...) => (VPLZCNTQ128 ...)
(LeadingZerosInt64x4 ...) => (VPLZCNTQ256 ...)
(LeadingZerosInt64x8 ...) => (VPLZCNTQ512 ...)
(LeadingZerosUint32x4 ...) => (VPLZCNTD128 ...)
(LeadingZerosUint32x8 ...) => (VPLZCNTD256 ...)
(LeadingZerosUint32x16 ...) => (VPLZCNTD512 ...)
(LeadingZerosUint64x2 ...) => (VPLZCNTQ128 ...)
(LeadingZerosUint64x4 ...) => (VPLZCNTQ256 ...)
(LeadingZerosUint64x8 ...) => (VPLZCNTQ512 ...)
2025-06-12 03:54:34 +00:00
(LessFloat32x4 x y) => (VCMPPS128 [1] x y)
(LessFloat32x8 x y) => (VCMPPS256 [1] x y)
2025-06-25 15:58:17 -04:00
(LessFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [1] x y))
2025-06-12 03:54:34 +00:00
(LessFloat64x2 x y) => (VCMPPD128 [1] x y)
(LessFloat64x4 x y) => (VCMPPD256 [1] x y)
(LessFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [1] x y))
2025-06-25 15:58:17 -04:00
(LessInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [1] x y))
2025-06-12 03:54:34 +00:00
(LessInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [1] x y))
2025-06-25 15:58:17 -04:00
(LessInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [1] x y))
2025-06-12 03:54:34 +00:00
(LessInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [1] x y))
2025-06-25 15:58:17 -04:00
(LessUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [1] x y))
2025-06-12 03:54:34 +00:00
(LessUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [1] x y))
2025-06-25 15:58:17 -04:00
(LessUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [1] x y))
2025-06-12 03:54:34 +00:00
(LessUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [1] x y))
(LessEqualFloat32x4 x y) => (VCMPPS128 [2] x y)
(LessEqualFloat32x8 x y) => (VCMPPS256 [2] x y)
2025-06-25 15:58:17 -04:00
(LessEqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [2] x y))
2025-06-12 03:54:34 +00:00
(LessEqualFloat64x2 x y) => (VCMPPD128 [2] x y)
(LessEqualFloat64x4 x y) => (VCMPPD256 [2] x y)
(LessEqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [2] x y))
2025-06-25 15:58:17 -04:00
(LessEqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [2] x y))
2025-06-12 03:54:34 +00:00
(LessEqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [2] x y))
2025-06-25 15:58:17 -04:00
(LessEqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [2] x y))
2025-06-12 03:54:34 +00:00
(LessEqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [2] x y))
2025-06-25 15:58:17 -04:00
(LessEqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [2] x y))
2025-06-12 03:54:34 +00:00
(LessEqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [2] x y))
2025-06-25 15:58:17 -04:00
(LessEqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [2] x y))
2025-06-12 03:54:34 +00:00
(LessEqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [2] x y))
(MaxFloat32x4 ...) => (VMAXPS128 ...)
(MaxFloat32x8 ...) => (VMAXPS256 ...)
2025-06-25 15:58:17 -04:00
(MaxFloat32x16 ...) => (VMAXPS512 ...)
2025-06-12 03:54:34 +00:00
(MaxFloat64x2 ...) => (VMAXPD128 ...)
(MaxFloat64x4 ...) => (VMAXPD256 ...)
(MaxFloat64x8 ...) => (VMAXPD512 ...)
2025-06-25 15:58:17 -04:00
(MaxInt8x16 ...) => (VPMAXSB128 ...)
(MaxInt8x32 ...) => (VPMAXSB256 ...)
(MaxInt8x64 ...) => (VPMAXSB512 ...)
(MaxInt16x8 ...) => (VPMAXSW128 ...)
2025-06-12 03:54:34 +00:00
(MaxInt16x16 ...) => (VPMAXSW256 ...)
(MaxInt16x32 ...) => (VPMAXSW512 ...)
(MaxInt32x4 ...) => (VPMAXSD128 ...)
(MaxInt32x8 ...) => (VPMAXSD256 ...)
2025-06-25 15:58:17 -04:00
(MaxInt32x16 ...) => (VPMAXSD512 ...)
2025-06-12 03:54:34 +00:00
(MaxInt64x2 ...) => (VPMAXSQ128 ...)
(MaxInt64x4 ...) => (VPMAXSQ256 ...)
(MaxInt64x8 ...) => (VPMAXSQ512 ...)
2025-06-25 15:58:17 -04:00
(MaxUint8x16 ...) => (VPMAXUB128 ...)
(MaxUint8x32 ...) => (VPMAXUB256 ...)
(MaxUint8x64 ...) => (VPMAXUB512 ...)
(MaxUint16x8 ...) => (VPMAXUW128 ...)
2025-06-12 03:54:34 +00:00
(MaxUint16x16 ...) => (VPMAXUW256 ...)
(MaxUint16x32 ...) => (VPMAXUW512 ...)
(MaxUint32x4 ...) => (VPMAXUD128 ...)
(MaxUint32x8 ...) => (VPMAXUD256 ...)
2025-06-25 15:58:17 -04:00
(MaxUint32x16 ...) => (VPMAXUD512 ...)
2025-06-12 03:54:34 +00:00
(MaxUint64x2 ...) => (VPMAXUQ128 ...)
(MaxUint64x4 ...) => (VPMAXUQ256 ...)
(MaxUint64x8 ...) => (VPMAXUQ512 ...)
(MinFloat32x4 ...) => (VMINPS128 ...)
(MinFloat32x8 ...) => (VMINPS256 ...)
2025-06-25 15:58:17 -04:00
(MinFloat32x16 ...) => (VMINPS512 ...)
2025-06-12 03:54:34 +00:00
(MinFloat64x2 ...) => (VMINPD128 ...)
(MinFloat64x4 ...) => (VMINPD256 ...)
(MinFloat64x8 ...) => (VMINPD512 ...)
2025-06-25 15:58:17 -04:00
(MinInt8x16 ...) => (VPMINSB128 ...)
(MinInt8x32 ...) => (VPMINSB256 ...)
(MinInt8x64 ...) => (VPMINSB512 ...)
(MinInt16x8 ...) => (VPMINSW128 ...)
2025-06-12 03:54:34 +00:00
(MinInt16x16 ...) => (VPMINSW256 ...)
(MinInt16x32 ...) => (VPMINSW512 ...)
(MinInt32x4 ...) => (VPMINSD128 ...)
(MinInt32x8 ...) => (VPMINSD256 ...)
2025-06-25 15:58:17 -04:00
(MinInt32x16 ...) => (VPMINSD512 ...)
2025-06-12 03:54:34 +00:00
(MinInt64x2 ...) => (VPMINSQ128 ...)
(MinInt64x4 ...) => (VPMINSQ256 ...)
(MinInt64x8 ...) => (VPMINSQ512 ...)
2025-06-25 15:58:17 -04:00
(MinUint8x16 ...) => (VPMINUB128 ...)
(MinUint8x32 ...) => (VPMINUB256 ...)
(MinUint8x64 ...) => (VPMINUB512 ...)
(MinUint16x8 ...) => (VPMINUW128 ...)
2025-06-12 03:54:34 +00:00
(MinUint16x16 ...) => (VPMINUW256 ...)
(MinUint16x32 ...) => (VPMINUW512 ...)
(MinUint32x4 ...) => (VPMINUD128 ...)
(MinUint32x8 ...) => (VPMINUD256 ...)
2025-06-25 15:58:17 -04:00
(MinUint32x16 ...) => (VPMINUD512 ...)
2025-06-12 03:54:34 +00:00
(MinUint64x2 ...) => (VPMINUQ128 ...)
(MinUint64x4 ...) => (VPMINUQ256 ...)
(MinUint64x8 ...) => (VPMINUQ512 ...)
(MulFloat32x4 ...) => (VMULPS128 ...)
(MulFloat32x8 ...) => (VMULPS256 ...)
2025-06-25 15:58:17 -04:00
(MulFloat32x16 ...) => (VMULPS512 ...)
2025-06-12 03:54:34 +00:00
(MulFloat64x2 ...) => (VMULPD128 ...)
(MulFloat64x4 ...) => (VMULPD256 ...)
(MulFloat64x8 ...) => (VMULPD512 ...)
2025-08-01 15:58:29 -04:00
(MulInt16x8 ...) => (VPMULLW128 ...)
(MulInt16x16 ...) => (VPMULLW256 ...)
(MulInt16x32 ...) => (VPMULLW512 ...)
(MulInt32x4 ...) => (VPMULLD128 ...)
(MulInt32x8 ...) => (VPMULLD256 ...)
(MulInt32x16 ...) => (VPMULLD512 ...)
(MulInt64x2 ...) => (VPMULLQ128 ...)
(MulInt64x4 ...) => (VPMULLQ256 ...)
(MulInt64x8 ...) => (VPMULLQ512 ...)
2025-08-07 17:05:50 +00:00
(MulUint16x8 ...) => (VPMULLW128 ...)
(MulUint16x16 ...) => (VPMULLW256 ...)
(MulUint16x32 ...) => (VPMULLW512 ...)
(MulUint32x4 ...) => (VPMULLD128 ...)
(MulUint32x8 ...) => (VPMULLD256 ...)
(MulUint32x16 ...) => (VPMULLD512 ...)
(MulUint64x2 ...) => (VPMULLQ128 ...)
(MulUint64x4 ...) => (VPMULLQ256 ...)
(MulUint64x8 ...) => (VPMULLQ512 ...)
(MulAddFloat32x4 ...) => (VFMADD213PS128 ...)
(MulAddFloat32x8 ...) => (VFMADD213PS256 ...)
(MulAddFloat32x16 ...) => (VFMADD213PS512 ...)
(MulAddFloat64x2 ...) => (VFMADD213PD128 ...)
(MulAddFloat64x4 ...) => (VFMADD213PD256 ...)
(MulAddFloat64x8 ...) => (VFMADD213PD512 ...)
(MulAddSubFloat32x4 ...) => (VFMADDSUB213PS128 ...)
(MulAddSubFloat32x8 ...) => (VFMADDSUB213PS256 ...)
(MulAddSubFloat32x16 ...) => (VFMADDSUB213PS512 ...)
(MulAddSubFloat64x2 ...) => (VFMADDSUB213PD128 ...)
(MulAddSubFloat64x4 ...) => (VFMADDSUB213PD256 ...)
(MulAddSubFloat64x8 ...) => (VFMADDSUB213PD512 ...)
2025-06-12 03:54:34 +00:00
(MulEvenWidenInt32x4 ...) => (VPMULDQ128 ...)
(MulEvenWidenInt32x8 ...) => (VPMULDQ256 ...)
(MulEvenWidenUint32x4 ...) => (VPMULUDQ128 ...)
(MulEvenWidenUint32x8 ...) => (VPMULUDQ256 ...)
2025-08-11 15:58:31 -04:00
(MulHighInt16x8 ...) => (VPMULHW128 ...)
(MulHighInt16x16 ...) => (VPMULHW256 ...)
2025-06-12 03:54:34 +00:00
(MulHighInt16x32 ...) => (VPMULHW512 ...)
2025-08-11 15:58:31 -04:00
(MulHighUint16x8 ...) => (VPMULHUW128 ...)
(MulHighUint16x16 ...) => (VPMULHUW256 ...)
(MulHighUint16x32 ...) => (VPMULHUW512 ...)
2025-08-07 17:05:50 +00:00
(MulSubAddFloat32x4 ...) => (VFMSUBADD213PS128 ...)
(MulSubAddFloat32x8 ...) => (VFMSUBADD213PS256 ...)
(MulSubAddFloat32x16 ...) => (VFMSUBADD213PS512 ...)
(MulSubAddFloat64x2 ...) => (VFMSUBADD213PD128 ...)
(MulSubAddFloat64x4 ...) => (VFMSUBADD213PD256 ...)
(MulSubAddFloat64x8 ...) => (VFMSUBADD213PD512 ...)
2025-06-12 03:54:34 +00:00
(NotEqualFloat32x4 x y) => (VCMPPS128 [4] x y)
(NotEqualFloat32x8 x y) => (VCMPPS256 [4] x y)
2025-06-25 15:58:17 -04:00
(NotEqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [4] x y))
2025-06-12 03:54:34 +00:00
(NotEqualFloat64x2 x y) => (VCMPPD128 [4] x y)
(NotEqualFloat64x4 x y) => (VCMPPD256 [4] x y)
(NotEqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [4] x y))
2025-06-25 15:58:17 -04:00
(NotEqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [4] x y))
2025-06-12 03:54:34 +00:00
(NotEqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [4] x y))
2025-06-25 15:58:17 -04:00
(NotEqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [4] x y))
2025-06-12 03:54:34 +00:00
(NotEqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [4] x y))
2025-06-25 15:58:17 -04:00
(NotEqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [4] x y))
2025-06-12 03:54:34 +00:00
(NotEqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [4] x y))
2025-06-25 15:58:17 -04:00
(NotEqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [4] x y))
2025-06-12 03:54:34 +00:00
(NotEqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [4] x y))
2025-08-07 17:05:50 +00:00
(OnesCountInt8x16 ...) => (VPOPCNTB128 ...)
(OnesCountInt8x32 ...) => (VPOPCNTB256 ...)
(OnesCountInt8x64 ...) => (VPOPCNTB512 ...)
(OnesCountInt16x8 ...) => (VPOPCNTW128 ...)
(OnesCountInt16x16 ...) => (VPOPCNTW256 ...)
(OnesCountInt16x32 ...) => (VPOPCNTW512 ...)
(OnesCountInt32x4 ...) => (VPOPCNTD128 ...)
(OnesCountInt32x8 ...) => (VPOPCNTD256 ...)
(OnesCountInt32x16 ...) => (VPOPCNTD512 ...)
(OnesCountInt64x2 ...) => (VPOPCNTQ128 ...)
(OnesCountInt64x4 ...) => (VPOPCNTQ256 ...)
(OnesCountInt64x8 ...) => (VPOPCNTQ512 ...)
(OnesCountUint8x16 ...) => (VPOPCNTB128 ...)
(OnesCountUint8x32 ...) => (VPOPCNTB256 ...)
(OnesCountUint8x64 ...) => (VPOPCNTB512 ...)
(OnesCountUint16x8 ...) => (VPOPCNTW128 ...)
(OnesCountUint16x16 ...) => (VPOPCNTW256 ...)
(OnesCountUint16x32 ...) => (VPOPCNTW512 ...)
(OnesCountUint32x4 ...) => (VPOPCNTD128 ...)
(OnesCountUint32x8 ...) => (VPOPCNTD256 ...)
(OnesCountUint32x16 ...) => (VPOPCNTD512 ...)
(OnesCountUint64x2 ...) => (VPOPCNTQ128 ...)
(OnesCountUint64x4 ...) => (VPOPCNTQ256 ...)
(OnesCountUint64x8 ...) => (VPOPCNTQ512 ...)
2025-06-25 15:58:17 -04:00
(OrInt8x16 ...) => (VPOR128 ...)
(OrInt8x32 ...) => (VPOR256 ...)
2025-08-01 19:13:13 +00:00
(OrInt8x64 ...) => (VPORD512 ...)
2025-06-12 03:54:34 +00:00
(OrInt16x8 ...) => (VPOR128 ...)
2025-06-25 15:58:17 -04:00
(OrInt16x16 ...) => (VPOR256 ...)
2025-08-01 19:13:13 +00:00
(OrInt16x32 ...) => (VPORD512 ...)
2025-06-12 03:54:34 +00:00
(OrInt32x4 ...) => (VPOR128 ...)
(OrInt32x8 ...) => (VPOR256 ...)
2025-06-25 15:58:17 -04:00
(OrInt32x16 ...) => (VPORD512 ...)
2025-06-12 03:54:34 +00:00
(OrInt64x2 ...) => (VPOR128 ...)
(OrInt64x4 ...) => (VPOR256 ...)
(OrInt64x8 ...) => (VPORQ512 ...)
2025-06-25 15:58:17 -04:00
(OrUint8x16 ...) => (VPOR128 ...)
(OrUint8x32 ...) => (VPOR256 ...)
2025-08-01 19:13:13 +00:00
(OrUint8x64 ...) => (VPORD512 ...)
2025-06-12 03:54:34 +00:00
(OrUint16x8 ...) => (VPOR128 ...)
2025-06-25 15:58:17 -04:00
(OrUint16x16 ...) => (VPOR256 ...)
2025-08-01 19:13:13 +00:00
(OrUint16x32 ...) => (VPORD512 ...)
2025-06-12 03:54:34 +00:00
(OrUint32x4 ...) => (VPOR128 ...)
(OrUint32x8 ...) => (VPOR256 ...)
2025-06-25 15:58:17 -04:00
(OrUint32x16 ...) => (VPORD512 ...)
2025-06-12 03:54:34 +00:00
(OrUint64x2 ...) => (VPOR128 ...)
(OrUint64x4 ...) => (VPOR256 ...)
(OrUint64x8 ...) => (VPORQ512 ...)
2025-07-14 19:39:44 +00:00
(PermuteFloat32x8 ...) => (VPERMPS256 ...)
(PermuteFloat32x16 ...) => (VPERMPS512 ...)
(PermuteFloat64x4 ...) => (VPERMPD256 ...)
(PermuteFloat64x8 ...) => (VPERMPD512 ...)
2025-08-21 19:11:30 +00:00
(PermuteInt8x16 ...) => (VPSHUFB128 ...)
2025-07-14 19:39:44 +00:00
(PermuteInt8x32 ...) => (VPERMB256 ...)
(PermuteInt8x64 ...) => (VPERMB512 ...)
(PermuteInt16x8 ...) => (VPERMW128 ...)
(PermuteInt16x16 ...) => (VPERMW256 ...)
(PermuteInt16x32 ...) => (VPERMW512 ...)
(PermuteInt32x8 ...) => (VPERMD256 ...)
(PermuteInt32x16 ...) => (VPERMD512 ...)
(PermuteInt64x4 ...) => (VPERMQ256 ...)
(PermuteInt64x8 ...) => (VPERMQ512 ...)
2025-08-21 19:11:30 +00:00
(PermuteUint8x16 ...) => (VPSHUFB128 ...)
2025-07-14 19:39:44 +00:00
(PermuteUint8x32 ...) => (VPERMB256 ...)
(PermuteUint8x64 ...) => (VPERMB512 ...)
(PermuteUint16x8 ...) => (VPERMW128 ...)
(PermuteUint16x16 ...) => (VPERMW256 ...)
(PermuteUint16x32 ...) => (VPERMW512 ...)
(PermuteUint32x8 ...) => (VPERMD256 ...)
(PermuteUint32x16 ...) => (VPERMD512 ...)
(PermuteUint64x4 ...) => (VPERMQ256 ...)
(PermuteUint64x8 ...) => (VPERMQ512 ...)
(Permute2Float32x4 ...) => (VPERMI2PS128 ...)
(Permute2Float32x8 ...) => (VPERMI2PS256 ...)
(Permute2Float32x16 ...) => (VPERMI2PS512 ...)
(Permute2Float64x2 ...) => (VPERMI2PD128 ...)
(Permute2Float64x4 ...) => (VPERMI2PD256 ...)
(Permute2Float64x8 ...) => (VPERMI2PD512 ...)
(Permute2Int8x16 ...) => (VPERMI2B128 ...)
(Permute2Int8x32 ...) => (VPERMI2B256 ...)
(Permute2Int8x64 ...) => (VPERMI2B512 ...)
(Permute2Int16x8 ...) => (VPERMI2W128 ...)
(Permute2Int16x16 ...) => (VPERMI2W256 ...)
(Permute2Int16x32 ...) => (VPERMI2W512 ...)
(Permute2Int32x4 ...) => (VPERMI2D128 ...)
(Permute2Int32x8 ...) => (VPERMI2D256 ...)
(Permute2Int32x16 ...) => (VPERMI2D512 ...)
(Permute2Int64x2 ...) => (VPERMI2Q128 ...)
(Permute2Int64x4 ...) => (VPERMI2Q256 ...)
(Permute2Int64x8 ...) => (VPERMI2Q512 ...)
(Permute2Uint8x16 ...) => (VPERMI2B128 ...)
(Permute2Uint8x32 ...) => (VPERMI2B256 ...)
(Permute2Uint8x64 ...) => (VPERMI2B512 ...)
(Permute2Uint16x8 ...) => (VPERMI2W128 ...)
(Permute2Uint16x16 ...) => (VPERMI2W256 ...)
(Permute2Uint16x32 ...) => (VPERMI2W512 ...)
(Permute2Uint32x4 ...) => (VPERMI2D128 ...)
(Permute2Uint32x8 ...) => (VPERMI2D256 ...)
(Permute2Uint32x16 ...) => (VPERMI2D512 ...)
(Permute2Uint64x2 ...) => (VPERMI2Q128 ...)
(Permute2Uint64x4 ...) => (VPERMI2Q256 ...)
(Permute2Uint64x8 ...) => (VPERMI2Q512 ...)
2025-08-21 20:37:57 +00:00
(PermuteConstantInt32x4 ...) => (VPSHUFD128 ...)
(PermuteConstantUint32x4 ...) => (VPSHUFD128 ...)
(PermuteConstantGroupedInt32x8 ...) => (VPSHUFD256 ...)
(PermuteConstantGroupedInt32x16 ...) => (VPSHUFD512 ...)
(PermuteConstantGroupedUint32x8 ...) => (VPSHUFD256 ...)
(PermuteConstantGroupedUint32x16 ...) => (VPSHUFD512 ...)
(PermuteConstantHiInt16x8 ...) => (VPSHUFHW128 ...)
(PermuteConstantHiInt32x4 ...) => (VPSHUFHW128 ...)
(PermuteConstantHiUint16x8 ...) => (VPSHUFHW128 ...)
(PermuteConstantHiUint32x4 ...) => (VPSHUFHW128 ...)
(PermuteConstantHiGroupedInt16x16 ...) => (VPSHUFHW256 ...)
(PermuteConstantHiGroupedInt16x32 ...) => (VPSHUFHW512 ...)
(PermuteConstantHiGroupedUint16x16 ...) => (VPSHUFHW256 ...)
(PermuteConstantHiGroupedUint16x32 ...) => (VPSHUFHW512 ...)
(PermuteConstantLoInt16x8 ...) => (VPSHUFHW128 ...)
(PermuteConstantLoInt32x4 ...) => (VPSHUFHW128 ...)
(PermuteConstantLoUint16x8 ...) => (VPSHUFHW128 ...)
(PermuteConstantLoUint32x4 ...) => (VPSHUFHW128 ...)
(PermuteConstantLoGroupedInt16x16 ...) => (VPSHUFHW256 ...)
(PermuteConstantLoGroupedInt16x32 ...) => (VPSHUFHW512 ...)
(PermuteConstantLoGroupedUint16x16 ...) => (VPSHUFHW256 ...)
(PermuteConstantLoGroupedUint16x32 ...) => (VPSHUFHW512 ...)
(PermuteGroupedInt8x32 ...) => (VPSHUFB256 ...)
(PermuteGroupedInt8x64 ...) => (VPSHUFB512 ...)
(PermuteGroupedUint8x32 ...) => (VPSHUFB256 ...)
(PermuteGroupedUint8x64 ...) => (VPSHUFB512 ...)
2025-08-07 17:05:50 +00:00
(ReciprocalFloat32x4 ...) => (VRCPPS128 ...)
(ReciprocalFloat32x8 ...) => (VRCPPS256 ...)
(ReciprocalFloat32x16 ...) => (VRCP14PS512 ...)
(ReciprocalFloat64x2 ...) => (VRCP14PD128 ...)
(ReciprocalFloat64x4 ...) => (VRCP14PD256 ...)
(ReciprocalFloat64x8 ...) => (VRCP14PD512 ...)
(ReciprocalSqrtFloat32x4 ...) => (VRSQRTPS128 ...)
(ReciprocalSqrtFloat32x8 ...) => (VRSQRTPS256 ...)
(ReciprocalSqrtFloat32x16 ...) => (VRSQRT14PS512 ...)
(ReciprocalSqrtFloat64x2 ...) => (VRSQRT14PD128 ...)
(ReciprocalSqrtFloat64x4 ...) => (VRSQRT14PD256 ...)
(ReciprocalSqrtFloat64x8 ...) => (VRSQRT14PD512 ...)
2025-07-08 12:52:30 -04:00
(RotateAllLeftInt32x4 ...) => (VPROLD128 ...)
(RotateAllLeftInt32x8 ...) => (VPROLD256 ...)
(RotateAllLeftInt32x16 ...) => (VPROLD512 ...)
(RotateAllLeftInt64x2 ...) => (VPROLQ128 ...)
(RotateAllLeftInt64x4 ...) => (VPROLQ256 ...)
(RotateAllLeftInt64x8 ...) => (VPROLQ512 ...)
(RotateAllLeftUint32x4 ...) => (VPROLD128 ...)
(RotateAllLeftUint32x8 ...) => (VPROLD256 ...)
(RotateAllLeftUint32x16 ...) => (VPROLD512 ...)
(RotateAllLeftUint64x2 ...) => (VPROLQ128 ...)
(RotateAllLeftUint64x4 ...) => (VPROLQ256 ...)
(RotateAllLeftUint64x8 ...) => (VPROLQ512 ...)
(RotateAllRightInt32x4 ...) => (VPRORD128 ...)
(RotateAllRightInt32x8 ...) => (VPRORD256 ...)
(RotateAllRightInt32x16 ...) => (VPRORD512 ...)
(RotateAllRightInt64x2 ...) => (VPRORQ128 ...)
(RotateAllRightInt64x4 ...) => (VPRORQ256 ...)
(RotateAllRightInt64x8 ...) => (VPRORQ512 ...)
(RotateAllRightUint32x4 ...) => (VPRORD128 ...)
(RotateAllRightUint32x8 ...) => (VPRORD256 ...)
(RotateAllRightUint32x16 ...) => (VPRORD512 ...)
(RotateAllRightUint64x2 ...) => (VPRORQ128 ...)
(RotateAllRightUint64x4 ...) => (VPRORQ256 ...)
(RotateAllRightUint64x8 ...) => (VPRORQ512 ...)
2025-06-24 15:21:29 +00:00
(RotateLeftInt32x4 ...) => (VPROLVD128 ...)
(RotateLeftInt32x8 ...) => (VPROLVD256 ...)
(RotateLeftInt32x16 ...) => (VPROLVD512 ...)
(RotateLeftInt64x2 ...) => (VPROLVQ128 ...)
(RotateLeftInt64x4 ...) => (VPROLVQ256 ...)
(RotateLeftInt64x8 ...) => (VPROLVQ512 ...)
(RotateLeftUint32x4 ...) => (VPROLVD128 ...)
(RotateLeftUint32x8 ...) => (VPROLVD256 ...)
(RotateLeftUint32x16 ...) => (VPROLVD512 ...)
(RotateLeftUint64x2 ...) => (VPROLVQ128 ...)
(RotateLeftUint64x4 ...) => (VPROLVQ256 ...)
(RotateLeftUint64x8 ...) => (VPROLVQ512 ...)
(RotateRightInt32x4 ...) => (VPRORVD128 ...)
(RotateRightInt32x8 ...) => (VPRORVD256 ...)
(RotateRightInt32x16 ...) => (VPRORVD512 ...)
(RotateRightInt64x2 ...) => (VPRORVQ128 ...)
(RotateRightInt64x4 ...) => (VPRORVQ256 ...)
(RotateRightInt64x8 ...) => (VPRORVQ512 ...)
(RotateRightUint32x4 ...) => (VPRORVD128 ...)
(RotateRightUint32x8 ...) => (VPRORVD256 ...)
(RotateRightUint32x16 ...) => (VPRORVD512 ...)
(RotateRightUint64x2 ...) => (VPRORVQ128 ...)
(RotateRightUint64x4 ...) => (VPRORVQ256 ...)
(RotateRightUint64x8 ...) => (VPRORVQ512 ...)
2025-08-07 17:05:50 +00:00
(RoundToEvenFloat32x4 x) => (VROUNDPS128 [0] x)
(RoundToEvenFloat32x8 x) => (VROUNDPS256 [0] x)
(RoundToEvenFloat64x2 x) => (VROUNDPD128 [0] x)
(RoundToEvenFloat64x4 x) => (VROUNDPD256 [0] x)
(RoundToEvenScaledFloat32x4 [a] x) => (VRNDSCALEPS128 [a+0] x)
(RoundToEvenScaledFloat32x8 [a] x) => (VRNDSCALEPS256 [a+0] x)
(RoundToEvenScaledFloat32x16 [a] x) => (VRNDSCALEPS512 [a+0] x)
(RoundToEvenScaledFloat64x2 [a] x) => (VRNDSCALEPD128 [a+0] x)
(RoundToEvenScaledFloat64x4 [a] x) => (VRNDSCALEPD256 [a+0] x)
(RoundToEvenScaledFloat64x8 [a] x) => (VRNDSCALEPD512 [a+0] x)
(RoundToEvenScaledResidueFloat32x4 [a] x) => (VREDUCEPS128 [a+0] x)
(RoundToEvenScaledResidueFloat32x8 [a] x) => (VREDUCEPS256 [a+0] x)
(RoundToEvenScaledResidueFloat32x16 [a] x) => (VREDUCEPS512 [a+0] x)
(RoundToEvenScaledResidueFloat64x2 [a] x) => (VREDUCEPD128 [a+0] x)
(RoundToEvenScaledResidueFloat64x4 [a] x) => (VREDUCEPD256 [a+0] x)
(RoundToEvenScaledResidueFloat64x8 [a] x) => (VREDUCEPD512 [a+0] x)
2025-08-01 15:58:29 -04:00
(ScaleFloat32x4 ...) => (VSCALEFPS128 ...)
(ScaleFloat32x8 ...) => (VSCALEFPS256 ...)
(ScaleFloat32x16 ...) => (VSCALEFPS512 ...)
(ScaleFloat64x2 ...) => (VSCALEFPD128 ...)
(ScaleFloat64x4 ...) => (VSCALEFPD256 ...)
(ScaleFloat64x8 ...) => (VSCALEFPD512 ...)
2025-08-05 17:34:05 -04:00
(SetElemFloat32x4 ...) => (VPINSRD128 ...)
(SetElemFloat64x2 ...) => (VPINSRQ128 ...)
2025-07-08 12:52:30 -04:00
(SetElemInt8x16 ...) => (VPINSRB128 ...)
(SetElemInt16x8 ...) => (VPINSRW128 ...)
(SetElemInt32x4 ...) => (VPINSRD128 ...)
(SetElemInt64x2 ...) => (VPINSRQ128 ...)
(SetElemUint8x16 ...) => (VPINSRB128 ...)
(SetElemUint16x8 ...) => (VPINSRW128 ...)
(SetElemUint32x4 ...) => (VPINSRD128 ...)
(SetElemUint64x2 ...) => (VPINSRQ128 ...)
2025-08-05 19:07:51 +00:00
(SetHiFloat32x8 x y) => (VINSERTF128256 [1] x y)
(SetHiFloat32x16 x y) => (VINSERTF64X4512 [1] x y)
(SetHiFloat64x4 x y) => (VINSERTF128256 [1] x y)
(SetHiFloat64x8 x y) => (VINSERTF64X4512 [1] x y)
(SetHiInt8x32 x y) => (VINSERTI128256 [1] x y)
(SetHiInt8x64 x y) => (VINSERTI64X4512 [1] x y)
(SetHiInt16x16 x y) => (VINSERTI128256 [1] x y)
(SetHiInt16x32 x y) => (VINSERTI64X4512 [1] x y)
(SetHiInt32x8 x y) => (VINSERTI128256 [1] x y)
(SetHiInt32x16 x y) => (VINSERTI64X4512 [1] x y)
(SetHiInt64x4 x y) => (VINSERTI128256 [1] x y)
(SetHiInt64x8 x y) => (VINSERTI64X4512 [1] x y)
(SetHiUint8x32 x y) => (VINSERTI128256 [1] x y)
(SetHiUint8x64 x y) => (VINSERTI64X4512 [1] x y)
(SetHiUint16x16 x y) => (VINSERTI128256 [1] x y)
(SetHiUint16x32 x y) => (VINSERTI64X4512 [1] x y)
(SetHiUint32x8 x y) => (VINSERTI128256 [1] x y)
(SetHiUint32x16 x y) => (VINSERTI64X4512 [1] x y)
(SetHiUint64x4 x y) => (VINSERTI128256 [1] x y)
(SetHiUint64x8 x y) => (VINSERTI64X4512 [1] x y)
(SetLoFloat32x8 x y) => (VINSERTF128256 [0] x y)
(SetLoFloat32x16 x y) => (VINSERTF64X4512 [0] x y)
(SetLoFloat64x4 x y) => (VINSERTF128256 [0] x y)
(SetLoFloat64x8 x y) => (VINSERTF64X4512 [0] x y)
(SetLoInt8x32 x y) => (VINSERTI128256 [0] x y)
(SetLoInt8x64 x y) => (VINSERTI64X4512 [0] x y)
(SetLoInt16x16 x y) => (VINSERTI128256 [0] x y)
(SetLoInt16x32 x y) => (VINSERTI64X4512 [0] x y)
(SetLoInt32x8 x y) => (VINSERTI128256 [0] x y)
(SetLoInt32x16 x y) => (VINSERTI64X4512 [0] x y)
(SetLoInt64x4 x y) => (VINSERTI128256 [0] x y)
(SetLoInt64x8 x y) => (VINSERTI64X4512 [0] x y)
(SetLoUint8x32 x y) => (VINSERTI128256 [0] x y)
(SetLoUint8x64 x y) => (VINSERTI64X4512 [0] x y)
(SetLoUint16x16 x y) => (VINSERTI128256 [0] x y)
(SetLoUint16x32 x y) => (VINSERTI64X4512 [0] x y)
(SetLoUint32x8 x y) => (VINSERTI128256 [0] x y)
(SetLoUint32x16 x y) => (VINSERTI64X4512 [0] x y)
(SetLoUint64x4 x y) => (VINSERTI128256 [0] x y)
(SetLoUint64x8 x y) => (VINSERTI64X4512 [0] x y)
2025-08-12 17:01:55 -04:00
(ShiftAllLeftInt16x8 ...) => (VPSLLW128 ...)
(VPSLLW128 x (MOVQconst [c])) => (VPSLLW128const [uint8(c)] x)
(ShiftAllLeftInt16x16 ...) => (VPSLLW256 ...)
(VPSLLW256 x (MOVQconst [c])) => (VPSLLW256const [uint8(c)] x)
(ShiftAllLeftInt16x32 ...) => (VPSLLW512 ...)
(VPSLLW512 x (MOVQconst [c])) => (VPSLLW512const [uint8(c)] x)
(ShiftAllLeftInt32x4 ...) => (VPSLLD128 ...)
(VPSLLD128 x (MOVQconst [c])) => (VPSLLD128const [uint8(c)] x)
(ShiftAllLeftInt32x8 ...) => (VPSLLD256 ...)
(VPSLLD256 x (MOVQconst [c])) => (VPSLLD256const [uint8(c)] x)
(ShiftAllLeftInt32x16 ...) => (VPSLLD512 ...)
(VPSLLD512 x (MOVQconst [c])) => (VPSLLD512const [uint8(c)] x)
(ShiftAllLeftInt64x2 ...) => (VPSLLQ128 ...)
(VPSLLQ128 x (MOVQconst [c])) => (VPSLLQ128const [uint8(c)] x)
(ShiftAllLeftInt64x4 ...) => (VPSLLQ256 ...)
(VPSLLQ256 x (MOVQconst [c])) => (VPSLLQ256const [uint8(c)] x)
(ShiftAllLeftInt64x8 ...) => (VPSLLQ512 ...)
(VPSLLQ512 x (MOVQconst [c])) => (VPSLLQ512const [uint8(c)] x)
(ShiftAllLeftUint16x8 ...) => (VPSLLW128 ...)
(ShiftAllLeftUint16x16 ...) => (VPSLLW256 ...)
(ShiftAllLeftUint16x32 ...) => (VPSLLW512 ...)
(ShiftAllLeftUint32x4 ...) => (VPSLLD128 ...)
(ShiftAllLeftUint32x8 ...) => (VPSLLD256 ...)
(ShiftAllLeftUint32x16 ...) => (VPSLLD512 ...)
(ShiftAllLeftUint64x2 ...) => (VPSLLQ128 ...)
(ShiftAllLeftUint64x4 ...) => (VPSLLQ256 ...)
(ShiftAllLeftUint64x8 ...) => (VPSLLQ512 ...)
2025-07-31 23:45:09 +00:00
(ShiftAllLeftConcatInt16x8 ...) => (VPSHLDW128 ...)
(ShiftAllLeftConcatInt16x16 ...) => (VPSHLDW256 ...)
(ShiftAllLeftConcatInt16x32 ...) => (VPSHLDW512 ...)
(ShiftAllLeftConcatInt32x4 ...) => (VPSHLDD128 ...)
(ShiftAllLeftConcatInt32x8 ...) => (VPSHLDD256 ...)
(ShiftAllLeftConcatInt32x16 ...) => (VPSHLDD512 ...)
(ShiftAllLeftConcatInt64x2 ...) => (VPSHLDQ128 ...)
(ShiftAllLeftConcatInt64x4 ...) => (VPSHLDQ256 ...)
(ShiftAllLeftConcatInt64x8 ...) => (VPSHLDQ512 ...)
(ShiftAllLeftConcatUint16x8 ...) => (VPSHLDW128 ...)
(ShiftAllLeftConcatUint16x16 ...) => (VPSHLDW256 ...)
(ShiftAllLeftConcatUint16x32 ...) => (VPSHLDW512 ...)
(ShiftAllLeftConcatUint32x4 ...) => (VPSHLDD128 ...)
(ShiftAllLeftConcatUint32x8 ...) => (VPSHLDD256 ...)
(ShiftAllLeftConcatUint32x16 ...) => (VPSHLDD512 ...)
(ShiftAllLeftConcatUint64x2 ...) => (VPSHLDQ128 ...)
(ShiftAllLeftConcatUint64x4 ...) => (VPSHLDQ256 ...)
(ShiftAllLeftConcatUint64x8 ...) => (VPSHLDQ512 ...)
2025-08-19 17:54:38 -04:00
(VPSLLWMasked128 x (MOVQconst [c]) mask) => (VPSLLWMasked128const [uint8(c)] x mask)
(VPSLLWMasked256 x (MOVQconst [c]) mask) => (VPSLLWMasked256const [uint8(c)] x mask)
(VPSLLWMasked512 x (MOVQconst [c]) mask) => (VPSLLWMasked512const [uint8(c)] x mask)
(VPSLLDMasked128 x (MOVQconst [c]) mask) => (VPSLLDMasked128const [uint8(c)] x mask)
(VPSLLDMasked256 x (MOVQconst [c]) mask) => (VPSLLDMasked256const [uint8(c)] x mask)
(VPSLLDMasked512 x (MOVQconst [c]) mask) => (VPSLLDMasked512const [uint8(c)] x mask)
(VPSLLQMasked128 x (MOVQconst [c]) mask) => (VPSLLQMasked128const [uint8(c)] x mask)
(VPSLLQMasked256 x (MOVQconst [c]) mask) => (VPSLLQMasked256const [uint8(c)] x mask)
(VPSLLQMasked512 x (MOVQconst [c]) mask) => (VPSLLQMasked512const [uint8(c)] x mask)
2025-08-12 17:01:55 -04:00
(ShiftAllRightInt16x8 ...) => (VPSRAW128 ...)
(VPSRAW128 x (MOVQconst [c])) => (VPSRAW128const [uint8(c)] x)
(ShiftAllRightInt16x16 ...) => (VPSRAW256 ...)
(VPSRAW256 x (MOVQconst [c])) => (VPSRAW256const [uint8(c)] x)
(ShiftAllRightInt16x32 ...) => (VPSRAW512 ...)
(VPSRAW512 x (MOVQconst [c])) => (VPSRAW512const [uint8(c)] x)
(ShiftAllRightInt32x4 ...) => (VPSRAD128 ...)
(VPSRAD128 x (MOVQconst [c])) => (VPSRAD128const [uint8(c)] x)
(ShiftAllRightInt32x8 ...) => (VPSRAD256 ...)
(VPSRAD256 x (MOVQconst [c])) => (VPSRAD256const [uint8(c)] x)
(ShiftAllRightInt32x16 ...) => (VPSRAD512 ...)
(VPSRAD512 x (MOVQconst [c])) => (VPSRAD512const [uint8(c)] x)
(ShiftAllRightInt64x2 ...) => (VPSRAQ128 ...)
(VPSRAQ128 x (MOVQconst [c])) => (VPSRAQ128const [uint8(c)] x)
(ShiftAllRightInt64x4 ...) => (VPSRAQ256 ...)
(VPSRAQ256 x (MOVQconst [c])) => (VPSRAQ256const [uint8(c)] x)
(ShiftAllRightInt64x8 ...) => (VPSRAQ512 ...)
(VPSRAQ512 x (MOVQconst [c])) => (VPSRAQ512const [uint8(c)] x)
(ShiftAllRightUint16x8 ...) => (VPSRLW128 ...)
(ShiftAllRightUint16x16 ...) => (VPSRLW256 ...)
(ShiftAllRightUint16x32 ...) => (VPSRLW512 ...)
(ShiftAllRightUint32x4 ...) => (VPSRLD128 ...)
(ShiftAllRightUint32x8 ...) => (VPSRLD256 ...)
(ShiftAllRightUint32x16 ...) => (VPSRLD512 ...)
(ShiftAllRightUint64x2 ...) => (VPSRLQ128 ...)
(ShiftAllRightUint64x4 ...) => (VPSRLQ256 ...)
(ShiftAllRightUint64x8 ...) => (VPSRLQ512 ...)
2025-07-31 23:45:09 +00:00
(ShiftAllRightConcatInt16x8 ...) => (VPSHRDW128 ...)
(ShiftAllRightConcatInt16x16 ...) => (VPSHRDW256 ...)
(ShiftAllRightConcatInt16x32 ...) => (VPSHRDW512 ...)
(ShiftAllRightConcatInt32x4 ...) => (VPSHRDD128 ...)
(ShiftAllRightConcatInt32x8 ...) => (VPSHRDD256 ...)
(ShiftAllRightConcatInt32x16 ...) => (VPSHRDD512 ...)
(ShiftAllRightConcatInt64x2 ...) => (VPSHRDQ128 ...)
(ShiftAllRightConcatInt64x4 ...) => (VPSHRDQ256 ...)
(ShiftAllRightConcatInt64x8 ...) => (VPSHRDQ512 ...)
(ShiftAllRightConcatUint16x8 ...) => (VPSHRDW128 ...)
(ShiftAllRightConcatUint16x16 ...) => (VPSHRDW256 ...)
(ShiftAllRightConcatUint16x32 ...) => (VPSHRDW512 ...)
(ShiftAllRightConcatUint32x4 ...) => (VPSHRDD128 ...)
(ShiftAllRightConcatUint32x8 ...) => (VPSHRDD256 ...)
(ShiftAllRightConcatUint32x16 ...) => (VPSHRDD512 ...)
(ShiftAllRightConcatUint64x2 ...) => (VPSHRDQ128 ...)
(ShiftAllRightConcatUint64x4 ...) => (VPSHRDQ256 ...)
(ShiftAllRightConcatUint64x8 ...) => (VPSHRDQ512 ...)
2025-08-19 17:54:38 -04:00
(VPSRAWMasked128 x (MOVQconst [c]) mask) => (VPSRAWMasked128const [uint8(c)] x mask)
(VPSRAWMasked256 x (MOVQconst [c]) mask) => (VPSRAWMasked256const [uint8(c)] x mask)
(VPSRAWMasked512 x (MOVQconst [c]) mask) => (VPSRAWMasked512const [uint8(c)] x mask)
(VPSRADMasked128 x (MOVQconst [c]) mask) => (VPSRADMasked128const [uint8(c)] x mask)
(VPSRADMasked256 x (MOVQconst [c]) mask) => (VPSRADMasked256const [uint8(c)] x mask)
(VPSRADMasked512 x (MOVQconst [c]) mask) => (VPSRADMasked512const [uint8(c)] x mask)
(VPSRAQMasked128 x (MOVQconst [c]) mask) => (VPSRAQMasked128const [uint8(c)] x mask)
(VPSRAQMasked256 x (MOVQconst [c]) mask) => (VPSRAQMasked256const [uint8(c)] x mask)
(VPSRAQMasked512 x (MOVQconst [c]) mask) => (VPSRAQMasked512const [uint8(c)] x mask)
2025-06-24 15:21:29 +00:00
(ShiftLeftInt16x8 ...) => (VPSLLVW128 ...)
(ShiftLeftInt16x16 ...) => (VPSLLVW256 ...)
(ShiftLeftInt16x32 ...) => (VPSLLVW512 ...)
(ShiftLeftInt32x4 ...) => (VPSLLVD128 ...)
(ShiftLeftInt32x8 ...) => (VPSLLVD256 ...)
(ShiftLeftInt32x16 ...) => (VPSLLVD512 ...)
(ShiftLeftInt64x2 ...) => (VPSLLVQ128 ...)
(ShiftLeftInt64x4 ...) => (VPSLLVQ256 ...)
(ShiftLeftInt64x8 ...) => (VPSLLVQ512 ...)
(ShiftLeftUint16x8 ...) => (VPSLLVW128 ...)
(ShiftLeftUint16x16 ...) => (VPSLLVW256 ...)
(ShiftLeftUint16x32 ...) => (VPSLLVW512 ...)
(ShiftLeftUint32x4 ...) => (VPSLLVD128 ...)
(ShiftLeftUint32x8 ...) => (VPSLLVD256 ...)
(ShiftLeftUint32x16 ...) => (VPSLLVD512 ...)
(ShiftLeftUint64x2 ...) => (VPSLLVQ128 ...)
(ShiftLeftUint64x4 ...) => (VPSLLVQ256 ...)
(ShiftLeftUint64x8 ...) => (VPSLLVQ512 ...)
2025-07-31 23:45:09 +00:00
(ShiftLeftConcatInt16x8 ...) => (VPSHLDVW128 ...)
(ShiftLeftConcatInt16x16 ...) => (VPSHLDVW256 ...)
(ShiftLeftConcatInt16x32 ...) => (VPSHLDVW512 ...)
(ShiftLeftConcatInt32x4 ...) => (VPSHLDVD128 ...)
(ShiftLeftConcatInt32x8 ...) => (VPSHLDVD256 ...)
(ShiftLeftConcatInt32x16 ...) => (VPSHLDVD512 ...)
(ShiftLeftConcatInt64x2 ...) => (VPSHLDVQ128 ...)
(ShiftLeftConcatInt64x4 ...) => (VPSHLDVQ256 ...)
(ShiftLeftConcatInt64x8 ...) => (VPSHLDVQ512 ...)
(ShiftLeftConcatUint16x8 ...) => (VPSHLDVW128 ...)
(ShiftLeftConcatUint16x16 ...) => (VPSHLDVW256 ...)
(ShiftLeftConcatUint16x32 ...) => (VPSHLDVW512 ...)
(ShiftLeftConcatUint32x4 ...) => (VPSHLDVD128 ...)
(ShiftLeftConcatUint32x8 ...) => (VPSHLDVD256 ...)
(ShiftLeftConcatUint32x16 ...) => (VPSHLDVD512 ...)
(ShiftLeftConcatUint64x2 ...) => (VPSHLDVQ128 ...)
(ShiftLeftConcatUint64x4 ...) => (VPSHLDVQ256 ...)
(ShiftLeftConcatUint64x8 ...) => (VPSHLDVQ512 ...)
2025-07-11 17:56:22 +00:00
(ShiftRightInt16x8 ...) => (VPSRAVW128 ...)
(ShiftRightInt16x16 ...) => (VPSRAVW256 ...)
(ShiftRightInt16x32 ...) => (VPSRAVW512 ...)
(ShiftRightInt32x4 ...) => (VPSRAVD128 ...)
(ShiftRightInt32x8 ...) => (VPSRAVD256 ...)
(ShiftRightInt32x16 ...) => (VPSRAVD512 ...)
(ShiftRightInt64x2 ...) => (VPSRAVQ128 ...)
(ShiftRightInt64x4 ...) => (VPSRAVQ256 ...)
(ShiftRightInt64x8 ...) => (VPSRAVQ512 ...)
2025-06-24 15:21:29 +00:00
(ShiftRightUint16x8 ...) => (VPSRLVW128 ...)
(ShiftRightUint16x16 ...) => (VPSRLVW256 ...)
(ShiftRightUint16x32 ...) => (VPSRLVW512 ...)
(ShiftRightUint32x4 ...) => (VPSRLVD128 ...)
(ShiftRightUint32x8 ...) => (VPSRLVD256 ...)
(ShiftRightUint32x16 ...) => (VPSRLVD512 ...)
(ShiftRightUint64x2 ...) => (VPSRLVQ128 ...)
(ShiftRightUint64x4 ...) => (VPSRLVQ256 ...)
(ShiftRightUint64x8 ...) => (VPSRLVQ512 ...)
2025-07-31 23:45:09 +00:00
(ShiftRightConcatInt16x8 ...) => (VPSHRDVW128 ...)
(ShiftRightConcatInt16x16 ...) => (VPSHRDVW256 ...)
(ShiftRightConcatInt16x32 ...) => (VPSHRDVW512 ...)
(ShiftRightConcatInt32x4 ...) => (VPSHRDVD128 ...)
(ShiftRightConcatInt32x8 ...) => (VPSHRDVD256 ...)
(ShiftRightConcatInt32x16 ...) => (VPSHRDVD512 ...)
(ShiftRightConcatInt64x2 ...) => (VPSHRDVQ128 ...)
(ShiftRightConcatInt64x4 ...) => (VPSHRDVQ256 ...)
(ShiftRightConcatInt64x8 ...) => (VPSHRDVQ512 ...)
(ShiftRightConcatUint16x8 ...) => (VPSHRDVW128 ...)
(ShiftRightConcatUint16x16 ...) => (VPSHRDVW256 ...)
(ShiftRightConcatUint16x32 ...) => (VPSHRDVW512 ...)
(ShiftRightConcatUint32x4 ...) => (VPSHRDVD128 ...)
(ShiftRightConcatUint32x8 ...) => (VPSHRDVD256 ...)
(ShiftRightConcatUint32x16 ...) => (VPSHRDVD512 ...)
(ShiftRightConcatUint64x2 ...) => (VPSHRDVQ128 ...)
(ShiftRightConcatUint64x4 ...) => (VPSHRDVQ256 ...)
(ShiftRightConcatUint64x8 ...) => (VPSHRDVQ512 ...)
2025-06-12 03:54:34 +00:00
(SqrtFloat32x4 ...) => (VSQRTPS128 ...)
(SqrtFloat32x8 ...) => (VSQRTPS256 ...)
2025-06-25 15:58:17 -04:00
(SqrtFloat32x16 ...) => (VSQRTPS512 ...)
2025-06-12 03:54:34 +00:00
(SqrtFloat64x2 ...) => (VSQRTPD128 ...)
(SqrtFloat64x4 ...) => (VSQRTPD256 ...)
(SqrtFloat64x8 ...) => (VSQRTPD512 ...)
2025-06-16 20:11:27 +00:00
(SubFloat32x4 ...) => (VSUBPS128 ...)
(SubFloat32x8 ...) => (VSUBPS256 ...)
2025-06-25 15:58:17 -04:00
(SubFloat32x16 ...) => (VSUBPS512 ...)
2025-06-16 20:11:27 +00:00
(SubFloat64x2 ...) => (VSUBPD128 ...)
(SubFloat64x4 ...) => (VSUBPD256 ...)
(SubFloat64x8 ...) => (VSUBPD512 ...)
2025-06-25 15:58:17 -04:00
(SubInt8x16 ...) => (VPSUBB128 ...)
(SubInt8x32 ...) => (VPSUBB256 ...)
(SubInt8x64 ...) => (VPSUBB512 ...)
(SubInt16x8 ...) => (VPSUBW128 ...)
2025-06-12 03:54:34 +00:00
(SubInt16x16 ...) => (VPSUBW256 ...)
(SubInt16x32 ...) => (VPSUBW512 ...)
(SubInt32x4 ...) => (VPSUBD128 ...)
(SubInt32x8 ...) => (VPSUBD256 ...)
2025-06-25 15:58:17 -04:00
(SubInt32x16 ...) => (VPSUBD512 ...)
2025-06-12 03:54:34 +00:00
(SubInt64x2 ...) => (VPSUBQ128 ...)
(SubInt64x4 ...) => (VPSUBQ256 ...)
(SubInt64x8 ...) => (VPSUBQ512 ...)
2025-06-25 15:58:17 -04:00
(SubUint8x16 ...) => (VPSUBB128 ...)
(SubUint8x32 ...) => (VPSUBB256 ...)
(SubUint8x64 ...) => (VPSUBB512 ...)
(SubUint16x8 ...) => (VPSUBW128 ...)
2025-06-12 03:54:34 +00:00
(SubUint16x16 ...) => (VPSUBW256 ...)
(SubUint16x32 ...) => (VPSUBW512 ...)
(SubUint32x4 ...) => (VPSUBD128 ...)
(SubUint32x8 ...) => (VPSUBD256 ...)
2025-06-25 15:58:17 -04:00
(SubUint32x16 ...) => (VPSUBD512 ...)
2025-06-12 03:54:34 +00:00
(SubUint64x2 ...) => (VPSUBQ128 ...)
(SubUint64x4 ...) => (VPSUBQ256 ...)
(SubUint64x8 ...) => (VPSUBQ512 ...)
2025-08-01 15:58:29 -04:00
(SubPairsFloat32x4 ...) => (VHSUBPS128 ...)
(SubPairsFloat32x8 ...) => (VHSUBPS256 ...)
(SubPairsFloat64x2 ...) => (VHSUBPD128 ...)
(SubPairsFloat64x4 ...) => (VHSUBPD256 ...)
(SubPairsInt16x8 ...) => (VPHSUBW128 ...)
(SubPairsInt16x16 ...) => (VPHSUBW256 ...)
(SubPairsInt32x4 ...) => (VPHSUBD128 ...)
(SubPairsInt32x8 ...) => (VPHSUBD256 ...)
(SubPairsUint16x8 ...) => (VPHSUBW128 ...)
(SubPairsUint16x16 ...) => (VPHSUBW256 ...)
(SubPairsUint32x4 ...) => (VPHSUBD128 ...)
(SubPairsUint32x8 ...) => (VPHSUBD256 ...)
(SubPairsSaturatedInt16x8 ...) => (VPHSUBSW128 ...)
(SubPairsSaturatedInt16x16 ...) => (VPHSUBSW256 ...)
(SubSaturatedInt8x16 ...) => (VPSUBSB128 ...)
(SubSaturatedInt8x32 ...) => (VPSUBSB256 ...)
(SubSaturatedInt8x64 ...) => (VPSUBSB512 ...)
(SubSaturatedInt16x8 ...) => (VPSUBSW128 ...)
(SubSaturatedInt16x16 ...) => (VPSUBSW256 ...)
(SubSaturatedInt16x32 ...) => (VPSUBSW512 ...)
2025-08-07 17:05:50 +00:00
(SubSaturatedUint8x16 ...) => (VPSUBUSB128 ...)
(SubSaturatedUint8x32 ...) => (VPSUBUSB256 ...)
(SubSaturatedUint8x64 ...) => (VPSUBUSB512 ...)
(SubSaturatedUint16x8 ...) => (VPSUBUSW128 ...)
(SubSaturatedUint16x16 ...) => (VPSUBUSW256 ...)
(SubSaturatedUint16x32 ...) => (VPSUBUSW512 ...)
2025-08-20 18:42:52 +00:00
(SumAbsDiffUint8x16 ...) => (VPSADBW128 ...)
(SumAbsDiffUint8x32 ...) => (VPSADBW256 ...)
(SumAbsDiffUint8x64 ...) => (VPSADBW512 ...)
2025-06-12 16:21:35 +00:00
(TruncFloat32x4 x) => (VROUNDPS128 [3] x)
(TruncFloat32x8 x) => (VROUNDPS256 [3] x)
(TruncFloat64x2 x) => (VROUNDPD128 [3] x)
(TruncFloat64x4 x) => (VROUNDPD256 [3] x)
2025-08-01 15:58:29 -04:00
(TruncScaledFloat32x4 [a] x) => (VRNDSCALEPS128 [a+3] x)
(TruncScaledFloat32x8 [a] x) => (VRNDSCALEPS256 [a+3] x)
(TruncScaledFloat32x16 [a] x) => (VRNDSCALEPS512 [a+3] x)
(TruncScaledFloat64x2 [a] x) => (VRNDSCALEPD128 [a+3] x)
(TruncScaledFloat64x4 [a] x) => (VRNDSCALEPD256 [a+3] x)
(TruncScaledFloat64x8 [a] x) => (VRNDSCALEPD512 [a+3] x)
(TruncScaledResidueFloat32x4 [a] x) => (VREDUCEPS128 [a+3] x)
(TruncScaledResidueFloat32x8 [a] x) => (VREDUCEPS256 [a+3] x)
(TruncScaledResidueFloat32x16 [a] x) => (VREDUCEPS512 [a+3] x)
(TruncScaledResidueFloat64x2 [a] x) => (VREDUCEPD128 [a+3] x)
(TruncScaledResidueFloat64x4 [a] x) => (VREDUCEPD256 [a+3] x)
(TruncScaledResidueFloat64x8 [a] x) => (VREDUCEPD512 [a+3] x)
2025-06-25 15:58:17 -04:00
(XorInt8x16 ...) => (VPXOR128 ...)
(XorInt8x32 ...) => (VPXOR256 ...)
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(XorInt8x64 ...) => (VPXORD512 ...)
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(XorInt16x8 ...) => (VPXOR128 ...)
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(XorInt16x16 ...) => (VPXOR256 ...)
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(XorInt16x32 ...) => (VPXORD512 ...)
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(XorInt32x4 ...) => (VPXOR128 ...)
(XorInt32x8 ...) => (VPXOR256 ...)
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(XorInt32x16 ...) => (VPXORD512 ...)
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(XorInt64x2 ...) => (VPXOR128 ...)
(XorInt64x4 ...) => (VPXOR256 ...)
(XorInt64x8 ...) => (VPXORQ512 ...)
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(XorUint8x16 ...) => (VPXOR128 ...)
(XorUint8x32 ...) => (VPXOR256 ...)
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(XorUint8x64 ...) => (VPXORD512 ...)
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(XorUint16x8 ...) => (VPXOR128 ...)
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(XorUint16x16 ...) => (VPXOR256 ...)
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(XorUint16x32 ...) => (VPXORD512 ...)
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(XorUint32x4 ...) => (VPXOR128 ...)
(XorUint32x8 ...) => (VPXOR256 ...)
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(XorUint32x16 ...) => (VPXORD512 ...)
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(XorUint64x2 ...) => (VPXOR128 ...)
(XorUint64x4 ...) => (VPXOR256 ...)
(XorUint64x8 ...) => (VPXORQ512 ...)
[dev.simd] simd, cmd/compile: generated files to add 'blend' and 'blendMasked'
Generated by arch/internal/simdgen CL 693175
These methods are not public because of simdgen-induced name/signature
issues, and because their addition was motivated by the need for
emulation tools.
The specific name signature problems are:
1) one set of instructions has the "Masked" suffix (because of how
that is incorporated into names) and the other set does not (though I
suppose the operation could be renamed).
2) because the AVX2 instruction is bytes-only, to get the signature
right, requires "OverwriteBase" but OverwriteBase also requires
OverwriteClass and "simdgen does not support [OverwriteClass] in
inputs".
3) the default operation order is false, true, but we want this in a
"x.Merged(y, mask)" that pairs with "x.Masked(mask)" where the true
case is x and the false case is y/zero, but the default ordering for
VPBLENDVB and VPBLENDMB is false->x and true->y.
4) VPBLENDVB only comes in byte width, which causes problems
for floats.
All this may get fixed in the future, for now it is just an
implementation detail.
Change-Id: I61b655c7011e2c33f8644f704f886133c89d2f15
Reviewed-on: https://go-review.googlesource.com/c/go/+/693155
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Junyang Shao <shaojunyang@google.com>
2025-08-04 15:19:54 -04:00
(blendInt8x16 ...) => (VPBLENDVB128 ...)
(blendInt8x32 ...) => (VPBLENDVB256 ...)
(blendMaskedInt8x64 x y mask) => (VPBLENDMBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
(blendMaskedInt16x32 x y mask) => (VPBLENDMWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
(blendMaskedInt32x16 x y mask) => (VPBLENDMDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
(blendMaskedInt64x8 x y mask) => (VPBLENDMQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
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(moveMaskedFloat32x16 x mask) => (VMOVUPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
(moveMaskedFloat64x8 x mask) => (VMOVUPDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
(moveMaskedInt8x64 x mask) => (VMOVDQU8Masked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
(moveMaskedInt16x32 x mask) => (VMOVDQU16Masked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
(moveMaskedInt32x16 x mask) => (VMOVDQU32Masked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
(moveMaskedInt64x8 x mask) => (VMOVDQU64Masked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
(moveMaskedUint8x64 x mask) => (VMOVDQU8Masked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
(moveMaskedUint16x32 x mask) => (VMOVDQU16Masked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
(moveMaskedUint32x16 x mask) => (VMOVDQU32Masked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
(moveMaskedUint64x8 x mask) => (VMOVDQU64Masked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
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(VMOVDQU8Masked512 (VPABSB512 x) mask) => (VPABSBMasked512 x mask)
(VMOVDQU16Masked512 (VPABSW512 x) mask) => (VPABSWMasked512 x mask)
(VMOVDQU32Masked512 (VPABSD512 x) mask) => (VPABSDMasked512 x mask)
(VMOVDQU64Masked512 (VPABSQ512 x) mask) => (VPABSQMasked512 x mask)
(VMOVDQU32Masked512 (VPDPWSSD512 x y z) mask) => (VPDPWSSDMasked512 x y z mask)
(VMOVDQU32Masked512 (VPDPWSSDS512 x y z) mask) => (VPDPWSSDSMasked512 x y z mask)
(VMOVDQU32Masked512 (VPDPBUSD512 x y z) mask) => (VPDPBUSDMasked512 x y z mask)
(VMOVDQU32Masked512 (VPDPBUSDS512 x y z) mask) => (VPDPBUSDSMasked512 x y z mask)
(VMOVDQU32Masked512 (VADDPS512 x y) mask) => (VADDPSMasked512 x y mask)
(VMOVDQU64Masked512 (VADDPD512 x y) mask) => (VADDPDMasked512 x y mask)
(VMOVDQU8Masked512 (VPADDB512 x y) mask) => (VPADDBMasked512 x y mask)
(VMOVDQU16Masked512 (VPADDW512 x y) mask) => (VPADDWMasked512 x y mask)
(VMOVDQU32Masked512 (VPADDD512 x y) mask) => (VPADDDMasked512 x y mask)
(VMOVDQU64Masked512 (VPADDQ512 x y) mask) => (VPADDQMasked512 x y mask)
(VMOVDQU8Masked512 (VPADDSB512 x y) mask) => (VPADDSBMasked512 x y mask)
(VMOVDQU16Masked512 (VPADDSW512 x y) mask) => (VPADDSWMasked512 x y mask)
(VMOVDQU8Masked512 (VPADDUSB512 x y) mask) => (VPADDUSBMasked512 x y mask)
(VMOVDQU16Masked512 (VPADDUSW512 x y) mask) => (VPADDUSWMasked512 x y mask)
(VMOVDQU32Masked512 (VPANDD512 x y) mask) => (VPANDDMasked512 x y mask)
(VMOVDQU64Masked512 (VPANDQ512 x y) mask) => (VPANDQMasked512 x y mask)
(VMOVDQU32Masked512 (VPANDND512 x y) mask) => (VPANDNDMasked512 x y mask)
(VMOVDQU64Masked512 (VPANDNQ512 x y) mask) => (VPANDNQMasked512 x y mask)
(VMOVDQU8Masked512 (VPAVGB512 x y) mask) => (VPAVGBMasked512 x y mask)
(VMOVDQU16Masked512 (VPAVGW512 x y) mask) => (VPAVGWMasked512 x y mask)
(VMOVDQU32Masked512 (VBROADCASTSS512 x) mask) => (VBROADCASTSSMasked512 x mask)
(VMOVDQU64Masked512 (VBROADCASTSD512 x) mask) => (VBROADCASTSDMasked512 x mask)
(VMOVDQU8Masked512 (VPBROADCASTB512 x) mask) => (VPBROADCASTBMasked512 x mask)
(VMOVDQU16Masked512 (VPBROADCASTW512 x) mask) => (VPBROADCASTWMasked512 x mask)
(VMOVDQU32Masked512 (VPBROADCASTD512 x) mask) => (VPBROADCASTDMasked512 x mask)
(VMOVDQU64Masked512 (VPBROADCASTQ512 x) mask) => (VPBROADCASTQMasked512 x mask)
(VMOVDQU32Masked512 (VRNDSCALEPS512 [a] x) mask) => (VRNDSCALEPSMasked512 [a] x mask)
(VMOVDQU64Masked512 (VRNDSCALEPD512 [a] x) mask) => (VRNDSCALEPDMasked512 [a] x mask)
(VMOVDQU32Masked512 (VREDUCEPS512 [a] x) mask) => (VREDUCEPSMasked512 [a] x mask)
(VMOVDQU64Masked512 (VREDUCEPD512 [a] x) mask) => (VREDUCEPDMasked512 [a] x mask)
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(VMOVDQU8Masked512 (VPMOVSXBW512 x) mask) => (VPMOVSXBWMasked512 x mask)
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(VMOVDQU32Masked512 (VPACKSSDW512 x y) mask) => (VPACKSSDWMasked512 x y mask)
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(VMOVDQU32Masked512 (VCVTTPS2DQ512 x) mask) => (VCVTTPS2DQMasked512 x mask)
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(VMOVDQU8Masked512 (VPMOVSXBD512 x) mask) => (VPMOVSXBDMasked512 x mask)
(VMOVDQU16Masked512 (VPMOVSXWD512 x) mask) => (VPMOVSXWDMasked512 x mask)
(VMOVDQU16Masked512 (VPMOVSXWQ512 x) mask) => (VPMOVSXWQMasked512 x mask)
(VMOVDQU32Masked512 (VPMOVSXDQ512 x) mask) => (VPMOVSXDQMasked512 x mask)
(VMOVDQU8Masked512 (VPMOVSXBQ512 x) mask) => (VPMOVSXBQMasked512 x mask)
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(VMOVDQU8Masked512 (VPMOVZXBW512 x) mask) => (VPMOVZXBWMasked512 x mask)
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(VMOVDQU32Masked512 (VPACKUSDW512 x y) mask) => (VPACKUSDWMasked512 x y mask)
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(VMOVDQU32Masked512 (VCVTPS2UDQ512 x) mask) => (VCVTPS2UDQMasked512 x mask)
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(VMOVDQU8Masked512 (VPMOVZXBD512 x) mask) => (VPMOVZXBDMasked512 x mask)
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(VMOVDQU16Masked512 (VPMOVZXWD512 x) mask) => (VPMOVZXWDMasked512 x mask)
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(VMOVDQU16Masked512 (VPMOVZXWQ512 x) mask) => (VPMOVZXWQMasked512 x mask)
(VMOVDQU32Masked512 (VPMOVZXDQ512 x) mask) => (VPMOVZXDQMasked512 x mask)
(VMOVDQU8Masked512 (VPMOVZXBQ512 x) mask) => (VPMOVZXBQMasked512 x mask)
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(VMOVDQU32Masked512 (VDIVPS512 x y) mask) => (VDIVPSMasked512 x y mask)
(VMOVDQU64Masked512 (VDIVPD512 x y) mask) => (VDIVPDMasked512 x y mask)
(VMOVDQU16Masked512 (VPMADDWD512 x y) mask) => (VPMADDWDMasked512 x y mask)
(VMOVDQU16Masked512 (VPMADDUBSW512 x y) mask) => (VPMADDUBSWMasked512 x y mask)
(VMOVDQU8Masked512 (VGF2P8AFFINEINVQB512 [a] x y) mask) => (VGF2P8AFFINEINVQBMasked512 [a] x y mask)
(VMOVDQU8Masked512 (VGF2P8AFFINEQB512 [a] x y) mask) => (VGF2P8AFFINEQBMasked512 [a] x y mask)
(VMOVDQU8Masked512 (VGF2P8MULB512 x y) mask) => (VGF2P8MULBMasked512 x y mask)
2025-09-08 19:38:56 +00:00
(VMOVDQU32Masked512 (VPLZCNTD512 x) mask) => (VPLZCNTDMasked512 x mask)
(VMOVDQU64Masked512 (VPLZCNTQ512 x) mask) => (VPLZCNTQMasked512 x mask)
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(VMOVDQU32Masked512 (VMAXPS512 x y) mask) => (VMAXPSMasked512 x y mask)
(VMOVDQU64Masked512 (VMAXPD512 x y) mask) => (VMAXPDMasked512 x y mask)
(VMOVDQU8Masked512 (VPMAXSB512 x y) mask) => (VPMAXSBMasked512 x y mask)
(VMOVDQU16Masked512 (VPMAXSW512 x y) mask) => (VPMAXSWMasked512 x y mask)
(VMOVDQU32Masked512 (VPMAXSD512 x y) mask) => (VPMAXSDMasked512 x y mask)
(VMOVDQU64Masked512 (VPMAXSQ512 x y) mask) => (VPMAXSQMasked512 x y mask)
(VMOVDQU8Masked512 (VPMAXUB512 x y) mask) => (VPMAXUBMasked512 x y mask)
(VMOVDQU16Masked512 (VPMAXUW512 x y) mask) => (VPMAXUWMasked512 x y mask)
(VMOVDQU32Masked512 (VPMAXUD512 x y) mask) => (VPMAXUDMasked512 x y mask)
(VMOVDQU64Masked512 (VPMAXUQ512 x y) mask) => (VPMAXUQMasked512 x y mask)
(VMOVDQU32Masked512 (VMINPS512 x y) mask) => (VMINPSMasked512 x y mask)
(VMOVDQU64Masked512 (VMINPD512 x y) mask) => (VMINPDMasked512 x y mask)
(VMOVDQU8Masked512 (VPMINSB512 x y) mask) => (VPMINSBMasked512 x y mask)
(VMOVDQU16Masked512 (VPMINSW512 x y) mask) => (VPMINSWMasked512 x y mask)
(VMOVDQU32Masked512 (VPMINSD512 x y) mask) => (VPMINSDMasked512 x y mask)
(VMOVDQU64Masked512 (VPMINSQ512 x y) mask) => (VPMINSQMasked512 x y mask)
(VMOVDQU8Masked512 (VPMINUB512 x y) mask) => (VPMINUBMasked512 x y mask)
(VMOVDQU16Masked512 (VPMINUW512 x y) mask) => (VPMINUWMasked512 x y mask)
(VMOVDQU32Masked512 (VPMINUD512 x y) mask) => (VPMINUDMasked512 x y mask)
(VMOVDQU64Masked512 (VPMINUQ512 x y) mask) => (VPMINUQMasked512 x y mask)
(VMOVDQU32Masked512 (VFMADD213PS512 x y z) mask) => (VFMADD213PSMasked512 x y z mask)
(VMOVDQU64Masked512 (VFMADD213PD512 x y z) mask) => (VFMADD213PDMasked512 x y z mask)
(VMOVDQU32Masked512 (VFMADDSUB213PS512 x y z) mask) => (VFMADDSUB213PSMasked512 x y z mask)
(VMOVDQU64Masked512 (VFMADDSUB213PD512 x y z) mask) => (VFMADDSUB213PDMasked512 x y z mask)
(VMOVDQU16Masked512 (VPMULHW512 x y) mask) => (VPMULHWMasked512 x y mask)
(VMOVDQU16Masked512 (VPMULHUW512 x y) mask) => (VPMULHUWMasked512 x y mask)
(VMOVDQU32Masked512 (VMULPS512 x y) mask) => (VMULPSMasked512 x y mask)
(VMOVDQU64Masked512 (VMULPD512 x y) mask) => (VMULPDMasked512 x y mask)
(VMOVDQU16Masked512 (VPMULLW512 x y) mask) => (VPMULLWMasked512 x y mask)
(VMOVDQU32Masked512 (VPMULLD512 x y) mask) => (VPMULLDMasked512 x y mask)
(VMOVDQU64Masked512 (VPMULLQ512 x y) mask) => (VPMULLQMasked512 x y mask)
(VMOVDQU32Masked512 (VFMSUBADD213PS512 x y z) mask) => (VFMSUBADD213PSMasked512 x y z mask)
(VMOVDQU64Masked512 (VFMSUBADD213PD512 x y z) mask) => (VFMSUBADD213PDMasked512 x y z mask)
(VMOVDQU8Masked512 (VPOPCNTB512 x) mask) => (VPOPCNTBMasked512 x mask)
(VMOVDQU16Masked512 (VPOPCNTW512 x) mask) => (VPOPCNTWMasked512 x mask)
(VMOVDQU32Masked512 (VPOPCNTD512 x) mask) => (VPOPCNTDMasked512 x mask)
(VMOVDQU64Masked512 (VPOPCNTQ512 x) mask) => (VPOPCNTQMasked512 x mask)
(VMOVDQU32Masked512 (VPORD512 x y) mask) => (VPORDMasked512 x y mask)
(VMOVDQU64Masked512 (VPORQ512 x y) mask) => (VPORQMasked512 x y mask)
(VMOVDQU8Masked512 (VPERMI2B512 x y z) mask) => (VPERMI2BMasked512 x y z mask)
(VMOVDQU16Masked512 (VPERMI2W512 x y z) mask) => (VPERMI2WMasked512 x y z mask)
(VMOVDQU32Masked512 (VPERMI2PS512 x y z) mask) => (VPERMI2PSMasked512 x y z mask)
(VMOVDQU32Masked512 (VPERMI2D512 x y z) mask) => (VPERMI2DMasked512 x y z mask)
(VMOVDQU64Masked512 (VPERMI2PD512 x y z) mask) => (VPERMI2PDMasked512 x y z mask)
(VMOVDQU64Masked512 (VPERMI2Q512 x y z) mask) => (VPERMI2QMasked512 x y z mask)
2025-08-21 20:37:57 +00:00
(VMOVDQU32Masked512 (VPSHUFD512 [a] x) mask) => (VPSHUFDMasked512 [a] x mask)
(VMOVDQU16Masked512 (VPSHUFHW512 [a] x) mask) => (VPSHUFHWMasked512 [a] x mask)
(VMOVDQU8Masked512 (VPSHUFB512 x y) mask) => (VPSHUFBMasked512 x y mask)
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(VMOVDQU8Masked512 (VPERMB512 x y) mask) => (VPERMBMasked512 x y mask)
(VMOVDQU16Masked512 (VPERMW512 x y) mask) => (VPERMWMasked512 x y mask)
(VMOVDQU32Masked512 (VPERMPS512 x y) mask) => (VPERMPSMasked512 x y mask)
(VMOVDQU32Masked512 (VPERMD512 x y) mask) => (VPERMDMasked512 x y mask)
(VMOVDQU64Masked512 (VPERMPD512 x y) mask) => (VPERMPDMasked512 x y mask)
(VMOVDQU64Masked512 (VPERMQ512 x y) mask) => (VPERMQMasked512 x y mask)
(VMOVDQU32Masked512 (VRCP14PS512 x) mask) => (VRCP14PSMasked512 x mask)
(VMOVDQU64Masked512 (VRCP14PD512 x) mask) => (VRCP14PDMasked512 x mask)
(VMOVDQU32Masked512 (VRSQRT14PS512 x) mask) => (VRSQRT14PSMasked512 x mask)
(VMOVDQU64Masked512 (VRSQRT14PD512 x) mask) => (VRSQRT14PDMasked512 x mask)
(VMOVDQU32Masked512 (VPROLD512 [a] x) mask) => (VPROLDMasked512 [a] x mask)
(VMOVDQU64Masked512 (VPROLQ512 [a] x) mask) => (VPROLQMasked512 [a] x mask)
(VMOVDQU32Masked512 (VPRORD512 [a] x) mask) => (VPRORDMasked512 [a] x mask)
(VMOVDQU64Masked512 (VPRORQ512 [a] x) mask) => (VPRORQMasked512 [a] x mask)
(VMOVDQU32Masked512 (VPROLVD512 x y) mask) => (VPROLVDMasked512 x y mask)
(VMOVDQU64Masked512 (VPROLVQ512 x y) mask) => (VPROLVQMasked512 x y mask)
(VMOVDQU32Masked512 (VPRORVD512 x y) mask) => (VPRORVDMasked512 x y mask)
(VMOVDQU64Masked512 (VPRORVQ512 x y) mask) => (VPRORVQMasked512 x y mask)
(VMOVDQU32Masked512 (VSCALEFPS512 x y) mask) => (VSCALEFPSMasked512 x y mask)
(VMOVDQU64Masked512 (VSCALEFPD512 x y) mask) => (VSCALEFPDMasked512 x y mask)
(VMOVDQU16Masked512 (VPSHLDW512 [a] x y) mask) => (VPSHLDWMasked512 [a] x y mask)
(VMOVDQU32Masked512 (VPSHLDD512 [a] x y) mask) => (VPSHLDDMasked512 [a] x y mask)
(VMOVDQU64Masked512 (VPSHLDQ512 [a] x y) mask) => (VPSHLDQMasked512 [a] x y mask)
(VMOVDQU16Masked512 (VPSLLW512 x y) mask) => (VPSLLWMasked512 x y mask)
(VMOVDQU32Masked512 (VPSLLD512 x y) mask) => (VPSLLDMasked512 x y mask)
(VMOVDQU64Masked512 (VPSLLQ512 x y) mask) => (VPSLLQMasked512 x y mask)
(VMOVDQU16Masked512 (VPSHRDW512 [a] x y) mask) => (VPSHRDWMasked512 [a] x y mask)
(VMOVDQU32Masked512 (VPSHRDD512 [a] x y) mask) => (VPSHRDDMasked512 [a] x y mask)
(VMOVDQU64Masked512 (VPSHRDQ512 [a] x y) mask) => (VPSHRDQMasked512 [a] x y mask)
(VMOVDQU16Masked512 (VPSRAW512 x y) mask) => (VPSRAWMasked512 x y mask)
(VMOVDQU32Masked512 (VPSRAD512 x y) mask) => (VPSRADMasked512 x y mask)
(VMOVDQU64Masked512 (VPSRAQ512 x y) mask) => (VPSRAQMasked512 x y mask)
(VMOVDQU16Masked512 (VPSRLW512 x y) mask) => (VPSRLWMasked512 x y mask)
(VMOVDQU32Masked512 (VPSRLD512 x y) mask) => (VPSRLDMasked512 x y mask)
(VMOVDQU64Masked512 (VPSRLQ512 x y) mask) => (VPSRLQMasked512 x y mask)
(VMOVDQU16Masked512 (VPSHLDVW512 x y z) mask) => (VPSHLDVWMasked512 x y z mask)
(VMOVDQU32Masked512 (VPSHLDVD512 x y z) mask) => (VPSHLDVDMasked512 x y z mask)
(VMOVDQU64Masked512 (VPSHLDVQ512 x y z) mask) => (VPSHLDVQMasked512 x y z mask)
(VMOVDQU16Masked512 (VPSLLVW512 x y) mask) => (VPSLLVWMasked512 x y mask)
(VMOVDQU32Masked512 (VPSLLVD512 x y) mask) => (VPSLLVDMasked512 x y mask)
(VMOVDQU64Masked512 (VPSLLVQ512 x y) mask) => (VPSLLVQMasked512 x y mask)
(VMOVDQU16Masked512 (VPSHRDVW512 x y z) mask) => (VPSHRDVWMasked512 x y z mask)
(VMOVDQU32Masked512 (VPSHRDVD512 x y z) mask) => (VPSHRDVDMasked512 x y z mask)
(VMOVDQU64Masked512 (VPSHRDVQ512 x y z) mask) => (VPSHRDVQMasked512 x y z mask)
(VMOVDQU16Masked512 (VPSRAVW512 x y) mask) => (VPSRAVWMasked512 x y mask)
(VMOVDQU32Masked512 (VPSRAVD512 x y) mask) => (VPSRAVDMasked512 x y mask)
(VMOVDQU64Masked512 (VPSRAVQ512 x y) mask) => (VPSRAVQMasked512 x y mask)
(VMOVDQU16Masked512 (VPSRLVW512 x y) mask) => (VPSRLVWMasked512 x y mask)
(VMOVDQU32Masked512 (VPSRLVD512 x y) mask) => (VPSRLVDMasked512 x y mask)
(VMOVDQU64Masked512 (VPSRLVQ512 x y) mask) => (VPSRLVQMasked512 x y mask)
(VMOVDQU32Masked512 (VSQRTPS512 x) mask) => (VSQRTPSMasked512 x mask)
(VMOVDQU64Masked512 (VSQRTPD512 x) mask) => (VSQRTPDMasked512 x mask)
(VMOVDQU32Masked512 (VSUBPS512 x y) mask) => (VSUBPSMasked512 x y mask)
(VMOVDQU64Masked512 (VSUBPD512 x y) mask) => (VSUBPDMasked512 x y mask)
(VMOVDQU8Masked512 (VPSUBB512 x y) mask) => (VPSUBBMasked512 x y mask)
(VMOVDQU16Masked512 (VPSUBW512 x y) mask) => (VPSUBWMasked512 x y mask)
(VMOVDQU32Masked512 (VPSUBD512 x y) mask) => (VPSUBDMasked512 x y mask)
(VMOVDQU64Masked512 (VPSUBQ512 x y) mask) => (VPSUBQMasked512 x y mask)
(VMOVDQU8Masked512 (VPSUBSB512 x y) mask) => (VPSUBSBMasked512 x y mask)
(VMOVDQU16Masked512 (VPSUBSW512 x y) mask) => (VPSUBSWMasked512 x y mask)
(VMOVDQU8Masked512 (VPSUBUSB512 x y) mask) => (VPSUBUSBMasked512 x y mask)
(VMOVDQU16Masked512 (VPSUBUSW512 x y) mask) => (VPSUBUSWMasked512 x y mask)
(VMOVDQU32Masked512 (VPXORD512 x y) mask) => (VPXORDMasked512 x y mask)
(VMOVDQU64Masked512 (VPXORQ512 x y) mask) => (VPXORQMasked512 x y mask)
(VMOVDQU16Masked512 (VPSLLW512const [a] x) mask) => (VPSLLWMasked512const [a] x mask)
(VMOVDQU32Masked512 (VPSLLD512const [a] x) mask) => (VPSLLDMasked512const [a] x mask)
(VMOVDQU64Masked512 (VPSLLQ512const [a] x) mask) => (VPSLLQMasked512const [a] x mask)
(VMOVDQU16Masked512 (VPSRLW512const [a] x) mask) => (VPSRLWMasked512const [a] x mask)
(VMOVDQU32Masked512 (VPSRLD512const [a] x) mask) => (VPSRLDMasked512const [a] x mask)
(VMOVDQU64Masked512 (VPSRLQ512const [a] x) mask) => (VPSRLQMasked512const [a] x mask)
(VMOVDQU16Masked512 (VPSRAW512const [a] x) mask) => (VPSRAWMasked512const [a] x mask)
(VMOVDQU32Masked512 (VPSRAD512const [a] x) mask) => (VPSRADMasked512const [a] x mask)
(VMOVDQU64Masked512 (VPSRAQ512const [a] x) mask) => (VPSRAQMasked512const [a] x mask)
2025-09-08 14:29:35 +00:00
(VPABSD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSD128load {sym} [off] ptr mem)
(VPABSD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSD256load {sym} [off] ptr mem)
(VPABSD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSD512load {sym} [off] ptr mem)
(VPABSQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSQ128load {sym} [off] ptr mem)
(VPABSQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSQ256load {sym} [off] ptr mem)
(VPABSQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSQ512load {sym} [off] ptr mem)
(VPABSDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSDMasked128load {sym} [off] ptr mask mem)
(VPABSDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSDMasked256load {sym} [off] ptr mask mem)
(VPABSDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSDMasked512load {sym} [off] ptr mask mem)
(VPABSQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSQMasked128load {sym} [off] ptr mask mem)
(VPABSQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSQMasked256load {sym} [off] ptr mask mem)
(VPABSQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSQMasked512load {sym} [off] ptr mask mem)
(VADDPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPS128load {sym} [off] x ptr mem)
(VADDPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPS256load {sym} [off] x ptr mem)
(VADDPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPS512load {sym} [off] x ptr mem)
(VADDPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPD128load {sym} [off] x ptr mem)
(VADDPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPD256load {sym} [off] x ptr mem)
(VADDPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPD512load {sym} [off] x ptr mem)
(VPADDD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDD128load {sym} [off] x ptr mem)
(VPADDD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDD256load {sym} [off] x ptr mem)
(VPADDD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDD512load {sym} [off] x ptr mem)
(VPADDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDQ128load {sym} [off] x ptr mem)
(VPADDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDQ256load {sym} [off] x ptr mem)
(VPADDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDQ512load {sym} [off] x ptr mem)
(VPDPWSSD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSD128load {sym} [off] x y ptr mem)
(VPDPWSSD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSD256load {sym} [off] x y ptr mem)
(VPDPWSSD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSD512load {sym} [off] x y ptr mem)
(VPDPWSSDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDMasked128load {sym} [off] x y ptr mask mem)
(VPDPWSSDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDMasked256load {sym} [off] x y ptr mask mem)
(VPDPWSSDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDMasked512load {sym} [off] x y ptr mask mem)
(VPDPWSSDS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDS128load {sym} [off] x y ptr mem)
(VPDPWSSDS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDS256load {sym} [off] x y ptr mem)
(VPDPWSSDS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDS512load {sym} [off] x y ptr mem)
(VPDPWSSDSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDSMasked128load {sym} [off] x y ptr mask mem)
(VPDPWSSDSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDSMasked256load {sym} [off] x y ptr mask mem)
(VPDPWSSDSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDSMasked512load {sym} [off] x y ptr mask mem)
(VPDPBUSD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSD128load {sym} [off] x y ptr mem)
(VPDPBUSD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSD256load {sym} [off] x y ptr mem)
(VPDPBUSD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSD512load {sym} [off] x y ptr mem)
(VPDPBUSDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDMasked128load {sym} [off] x y ptr mask mem)
(VPDPBUSDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDMasked256load {sym} [off] x y ptr mask mem)
(VPDPBUSDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDMasked512load {sym} [off] x y ptr mask mem)
(VPDPBUSDS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDS128load {sym} [off] x y ptr mem)
(VPDPBUSDS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDS256load {sym} [off] x y ptr mem)
(VPDPBUSDS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDS512load {sym} [off] x y ptr mem)
(VPDPBUSDSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDSMasked128load {sym} [off] x y ptr mask mem)
(VPDPBUSDSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDSMasked256load {sym} [off] x y ptr mask mem)
(VPDPBUSDSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDSMasked512load {sym} [off] x y ptr mask mem)
(VADDPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VADDPSMasked128load {sym} [off] x ptr mask mem)
(VADDPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VADDPSMasked256load {sym} [off] x ptr mask mem)
(VADDPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VADDPSMasked512load {sym} [off] x ptr mask mem)
(VADDPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VADDPDMasked128load {sym} [off] x ptr mask mem)
(VADDPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VADDPDMasked256load {sym} [off] x ptr mask mem)
(VADDPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VADDPDMasked512load {sym} [off] x ptr mask mem)
(VPADDDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDDMasked128load {sym} [off] x ptr mask mem)
(VPADDDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDDMasked256load {sym} [off] x ptr mask mem)
(VPADDDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDDMasked512load {sym} [off] x ptr mask mem)
(VPADDQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDQMasked128load {sym} [off] x ptr mask mem)
(VPADDQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDQMasked256load {sym} [off] x ptr mask mem)
(VPADDQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPADDQMasked512load {sym} [off] x ptr mask mem)
(VPANDD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPANDD512load {sym} [off] x ptr mem)
(VPANDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPANDQ512load {sym} [off] x ptr mem)
(VPANDDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDDMasked128load {sym} [off] x ptr mask mem)
(VPANDDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDDMasked256load {sym} [off] x ptr mask mem)
(VPANDDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDDMasked512load {sym} [off] x ptr mask mem)
(VPANDQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDQMasked128load {sym} [off] x ptr mask mem)
(VPANDQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDQMasked256load {sym} [off] x ptr mask mem)
(VPANDQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDQMasked512load {sym} [off] x ptr mask mem)
(VPANDND512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPANDND512load {sym} [off] x ptr mem)
(VPANDNQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPANDNQ512load {sym} [off] x ptr mem)
(VPANDNDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNDMasked128load {sym} [off] x ptr mask mem)
(VPANDNDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNDMasked256load {sym} [off] x ptr mask mem)
(VPANDNDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNDMasked512load {sym} [off] x ptr mask mem)
(VPANDNQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNQMasked128load {sym} [off] x ptr mask mem)
(VPANDNQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNQMasked256load {sym} [off] x ptr mask mem)
(VPANDNQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNQMasked512load {sym} [off] x ptr mask mem)
(VPACKSSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW128load {sym} [off] x ptr mem)
(VPACKSSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW256load {sym} [off] x ptr mem)
(VPACKSSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW512load {sym} [off] x ptr mem)
(VPACKSSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked128load {sym} [off] x ptr mask mem)
(VPACKSSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked256load {sym} [off] x ptr mask mem)
(VPACKSSDWMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked512load {sym} [off] x ptr mask mem)
(VCVTTPS2DQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ128load {sym} [off] ptr mem)
(VCVTTPS2DQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ256load {sym} [off] ptr mem)
(VCVTTPS2DQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ512load {sym} [off] ptr mem)
(VCVTTPS2DQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked128load {sym} [off] ptr mask mem)
(VCVTTPS2DQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked256load {sym} [off] ptr mask mem)
(VCVTTPS2DQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked512load {sym} [off] ptr mask mem)
(VPACKUSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW128load {sym} [off] x ptr mem)
(VPACKUSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW256load {sym} [off] x ptr mem)
(VPACKUSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW512load {sym} [off] x ptr mem)
(VPACKUSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked128load {sym} [off] x ptr mask mem)
(VPACKUSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked256load {sym} [off] x ptr mask mem)
(VPACKUSDWMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked512load {sym} [off] x ptr mask mem)
(VCVTPS2UDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQ128load {sym} [off] ptr mem)
(VCVTPS2UDQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQ256load {sym} [off] ptr mem)
(VCVTPS2UDQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQ512load {sym} [off] ptr mem)
(VCVTPS2UDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked128load {sym} [off] ptr mask mem)
(VCVTPS2UDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked256load {sym} [off] ptr mask mem)
(VCVTPS2UDQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked512load {sym} [off] ptr mask mem)
(VDIVPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPS128load {sym} [off] x ptr mem)
(VDIVPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPS256load {sym} [off] x ptr mem)
(VDIVPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPS512load {sym} [off] x ptr mem)
(VDIVPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPD128load {sym} [off] x ptr mem)
(VDIVPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPD256load {sym} [off] x ptr mem)
(VDIVPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPD512load {sym} [off] x ptr mem)
(VDIVPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPSMasked128load {sym} [off] x ptr mask mem)
(VDIVPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPSMasked256load {sym} [off] x ptr mask mem)
(VDIVPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPSMasked512load {sym} [off] x ptr mask mem)
(VDIVPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPDMasked128load {sym} [off] x ptr mask mem)
(VDIVPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPDMasked256load {sym} [off] x ptr mask mem)
(VDIVPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPDMasked512load {sym} [off] x ptr mask mem)
(VPCMPEQD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQD128load {sym} [off] x ptr mem)
(VPCMPEQD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQD256load {sym} [off] x ptr mem)
(VPCMPEQD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQD512load {sym} [off] x ptr mem)
(VPCMPEQQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQQ128load {sym} [off] x ptr mem)
(VPCMPEQQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQQ256load {sym} [off] x ptr mem)
(VPCMPEQQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQQ512load {sym} [off] x ptr mem)
(VPCMPGTD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTD128load {sym} [off] x ptr mem)
(VPCMPGTD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTD256load {sym} [off] x ptr mem)
(VPCMPGTD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTD512load {sym} [off] x ptr mem)
(VPCMPGTQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTQ128load {sym} [off] x ptr mem)
(VPCMPGTQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTQ256load {sym} [off] x ptr mem)
(VPCMPGTQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTQ512load {sym} [off] x ptr mem)
(VPUNPCKHDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHDQ128load {sym} [off] x ptr mem)
(VPUNPCKHQDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHQDQ128load {sym} [off] x ptr mem)
(VPUNPCKHDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHDQ256load {sym} [off] x ptr mem)
(VPUNPCKHDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHDQ512load {sym} [off] x ptr mem)
(VPUNPCKHQDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHQDQ256load {sym} [off] x ptr mem)
(VPUNPCKHQDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHQDQ512load {sym} [off] x ptr mem)
(VPUNPCKLDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLDQ128load {sym} [off] x ptr mem)
(VPUNPCKLQDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLQDQ128load {sym} [off] x ptr mem)
(VPUNPCKLDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLDQ256load {sym} [off] x ptr mem)
(VPUNPCKLDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLDQ512load {sym} [off] x ptr mem)
(VPUNPCKLQDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLQDQ256load {sym} [off] x ptr mem)
(VPUNPCKLQDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLQDQ512load {sym} [off] x ptr mem)
(VMAXPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPS128load {sym} [off] x ptr mem)
(VMAXPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPS256load {sym} [off] x ptr mem)
(VMAXPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPS512load {sym} [off] x ptr mem)
(VMAXPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPD128load {sym} [off] x ptr mem)
(VMAXPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPD256load {sym} [off] x ptr mem)
(VMAXPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPD512load {sym} [off] x ptr mem)
(VPMAXSD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSD128load {sym} [off] x ptr mem)
(VPMAXSD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSD256load {sym} [off] x ptr mem)
(VPMAXSD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSD512load {sym} [off] x ptr mem)
(VPMAXSQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQ128load {sym} [off] x ptr mem)
(VPMAXSQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQ256load {sym} [off] x ptr mem)
(VPMAXSQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQ512load {sym} [off] x ptr mem)
(VPMAXUD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUD128load {sym} [off] x ptr mem)
(VPMAXUD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUD256load {sym} [off] x ptr mem)
(VPMAXUD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUD512load {sym} [off] x ptr mem)
(VPMAXUQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQ128load {sym} [off] x ptr mem)
(VPMAXUQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQ256load {sym} [off] x ptr mem)
(VPMAXUQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQ512load {sym} [off] x ptr mem)
(VMAXPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMAXPSMasked128load {sym} [off] x ptr mask mem)
(VMAXPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMAXPSMasked256load {sym} [off] x ptr mask mem)
(VMAXPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMAXPSMasked512load {sym} [off] x ptr mask mem)
(VMAXPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMAXPDMasked128load {sym} [off] x ptr mask mem)
(VMAXPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMAXPDMasked256load {sym} [off] x ptr mask mem)
(VMAXPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMAXPDMasked512load {sym} [off] x ptr mask mem)
(VPMAXSDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSDMasked128load {sym} [off] x ptr mask mem)
(VPMAXSDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSDMasked256load {sym} [off] x ptr mask mem)
(VPMAXSDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSDMasked512load {sym} [off] x ptr mask mem)
(VPMAXSQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQMasked128load {sym} [off] x ptr mask mem)
(VPMAXSQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQMasked256load {sym} [off] x ptr mask mem)
(VPMAXSQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQMasked512load {sym} [off] x ptr mask mem)
(VPMAXUDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUDMasked128load {sym} [off] x ptr mask mem)
(VPMAXUDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUDMasked256load {sym} [off] x ptr mask mem)
(VPMAXUDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUDMasked512load {sym} [off] x ptr mask mem)
(VPMAXUQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQMasked128load {sym} [off] x ptr mask mem)
(VPMAXUQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQMasked256load {sym} [off] x ptr mask mem)
(VPMAXUQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQMasked512load {sym} [off] x ptr mask mem)
(VMINPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPS128load {sym} [off] x ptr mem)
(VMINPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPS256load {sym} [off] x ptr mem)
(VMINPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPS512load {sym} [off] x ptr mem)
(VMINPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPD128load {sym} [off] x ptr mem)
(VMINPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPD256load {sym} [off] x ptr mem)
(VMINPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPD512load {sym} [off] x ptr mem)
(VPMINSD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSD128load {sym} [off] x ptr mem)
(VPMINSD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSD256load {sym} [off] x ptr mem)
(VPMINSD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSD512load {sym} [off] x ptr mem)
(VPMINSQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSQ128load {sym} [off] x ptr mem)
(VPMINSQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSQ256load {sym} [off] x ptr mem)
(VPMINSQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSQ512load {sym} [off] x ptr mem)
(VPMINUD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUD128load {sym} [off] x ptr mem)
(VPMINUD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUD256load {sym} [off] x ptr mem)
(VPMINUD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUD512load {sym} [off] x ptr mem)
(VPMINUQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUQ128load {sym} [off] x ptr mem)
(VPMINUQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUQ256load {sym} [off] x ptr mem)
(VPMINUQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUQ512load {sym} [off] x ptr mem)
(VMINPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMINPSMasked128load {sym} [off] x ptr mask mem)
(VMINPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMINPSMasked256load {sym} [off] x ptr mask mem)
(VMINPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMINPSMasked512load {sym} [off] x ptr mask mem)
(VMINPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMINPDMasked128load {sym} [off] x ptr mask mem)
(VMINPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMINPDMasked256load {sym} [off] x ptr mask mem)
(VMINPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMINPDMasked512load {sym} [off] x ptr mask mem)
(VPMINSDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSDMasked128load {sym} [off] x ptr mask mem)
(VPMINSDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSDMasked256load {sym} [off] x ptr mask mem)
(VPMINSDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSDMasked512load {sym} [off] x ptr mask mem)
(VPMINSQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSQMasked128load {sym} [off] x ptr mask mem)
(VPMINSQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSQMasked256load {sym} [off] x ptr mask mem)
(VPMINSQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINSQMasked512load {sym} [off] x ptr mask mem)
(VPMINUDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUDMasked128load {sym} [off] x ptr mask mem)
(VPMINUDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUDMasked256load {sym} [off] x ptr mask mem)
(VPMINUDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUDMasked512load {sym} [off] x ptr mask mem)
(VPMINUQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUQMasked128load {sym} [off] x ptr mask mem)
(VPMINUQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUQMasked256load {sym} [off] x ptr mask mem)
(VPMINUQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUQMasked512load {sym} [off] x ptr mask mem)
(VMULPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPS128load {sym} [off] x ptr mem)
(VMULPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPS256load {sym} [off] x ptr mem)
(VMULPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPS512load {sym} [off] x ptr mem)
(VMULPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPD128load {sym} [off] x ptr mem)
(VMULPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPD256load {sym} [off] x ptr mem)
(VMULPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPD512load {sym} [off] x ptr mem)
(VPMULLD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLD128load {sym} [off] x ptr mem)
(VPMULLD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLD256load {sym} [off] x ptr mem)
(VPMULLD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLD512load {sym} [off] x ptr mem)
(VPMULLQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLQ128load {sym} [off] x ptr mem)
(VPMULLQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLQ256load {sym} [off] x ptr mem)
(VPMULLQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLQ512load {sym} [off] x ptr mem)
(VFMADD213PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PS128load {sym} [off] x y ptr mem)
(VFMADD213PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PS256load {sym} [off] x y ptr mem)
(VFMADD213PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PS512load {sym} [off] x y ptr mem)
(VFMADD213PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PD128load {sym} [off] x y ptr mem)
(VFMADD213PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PD256load {sym} [off] x y ptr mem)
(VFMADD213PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PD512load {sym} [off] x y ptr mem)
(VFMADD213PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PSMasked128load {sym} [off] x y ptr mask mem)
(VFMADD213PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PSMasked256load {sym} [off] x y ptr mask mem)
(VFMADD213PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PSMasked512load {sym} [off] x y ptr mask mem)
(VFMADD213PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PDMasked128load {sym} [off] x y ptr mask mem)
(VFMADD213PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PDMasked256load {sym} [off] x y ptr mask mem)
(VFMADD213PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADD213PDMasked512load {sym} [off] x y ptr mask mem)
(VFMADDSUB213PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PS128load {sym} [off] x y ptr mem)
(VFMADDSUB213PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PS256load {sym} [off] x y ptr mem)
(VFMADDSUB213PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PS512load {sym} [off] x y ptr mem)
(VFMADDSUB213PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PD128load {sym} [off] x y ptr mem)
(VFMADDSUB213PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PD256load {sym} [off] x y ptr mem)
(VFMADDSUB213PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PD512load {sym} [off] x y ptr mem)
(VFMADDSUB213PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PSMasked128load {sym} [off] x y ptr mask mem)
(VFMADDSUB213PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PSMasked256load {sym} [off] x y ptr mask mem)
(VFMADDSUB213PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PSMasked512load {sym} [off] x y ptr mask mem)
(VFMADDSUB213PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PDMasked128load {sym} [off] x y ptr mask mem)
(VFMADDSUB213PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PDMasked256load {sym} [off] x y ptr mask mem)
(VFMADDSUB213PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PDMasked512load {sym} [off] x y ptr mask mem)
(VPMULDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULDQ128load {sym} [off] x ptr mem)
(VPMULDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULDQ256load {sym} [off] x ptr mem)
(VPMULUDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULUDQ128load {sym} [off] x ptr mem)
(VPMULUDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULUDQ256load {sym} [off] x ptr mem)
(VMULPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPSMasked128load {sym} [off] x ptr mask mem)
(VMULPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPSMasked256load {sym} [off] x ptr mask mem)
(VMULPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPSMasked512load {sym} [off] x ptr mask mem)
(VMULPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPDMasked128load {sym} [off] x ptr mask mem)
(VMULPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPDMasked256load {sym} [off] x ptr mask mem)
(VMULPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPDMasked512load {sym} [off] x ptr mask mem)
(VPMULLDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLDMasked128load {sym} [off] x ptr mask mem)
(VPMULLDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLDMasked256load {sym} [off] x ptr mask mem)
(VPMULLDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLDMasked512load {sym} [off] x ptr mask mem)
(VPMULLQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLQMasked128load {sym} [off] x ptr mask mem)
(VPMULLQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLQMasked256load {sym} [off] x ptr mask mem)
(VPMULLQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMULLQMasked512load {sym} [off] x ptr mask mem)
(VFMSUBADD213PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PS128load {sym} [off] x y ptr mem)
(VFMSUBADD213PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PS256load {sym} [off] x y ptr mem)
(VFMSUBADD213PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PS512load {sym} [off] x y ptr mem)
(VFMSUBADD213PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PD128load {sym} [off] x y ptr mem)
(VFMSUBADD213PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PD256load {sym} [off] x y ptr mem)
(VFMSUBADD213PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PD512load {sym} [off] x y ptr mem)
(VFMSUBADD213PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PSMasked128load {sym} [off] x y ptr mask mem)
(VFMSUBADD213PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PSMasked256load {sym} [off] x y ptr mask mem)
(VFMSUBADD213PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PSMasked512load {sym} [off] x y ptr mask mem)
(VFMSUBADD213PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PDMasked128load {sym} [off] x y ptr mask mem)
(VFMSUBADD213PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PDMasked256load {sym} [off] x y ptr mask mem)
(VFMSUBADD213PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMSUBADD213PDMasked512load {sym} [off] x y ptr mask mem)
(VPOPCNTD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTD128load {sym} [off] ptr mem)
(VPOPCNTD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTD256load {sym} [off] ptr mem)
(VPOPCNTD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTD512load {sym} [off] ptr mem)
(VPOPCNTQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTQ128load {sym} [off] ptr mem)
(VPOPCNTQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTQ256load {sym} [off] ptr mem)
(VPOPCNTQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTQ512load {sym} [off] ptr mem)
(VPOPCNTDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTDMasked128load {sym} [off] ptr mask mem)
(VPOPCNTDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTDMasked256load {sym} [off] ptr mask mem)
(VPOPCNTDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTDMasked512load {sym} [off] ptr mask mem)
(VPOPCNTQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTQMasked128load {sym} [off] ptr mask mem)
(VPOPCNTQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTQMasked256load {sym} [off] ptr mask mem)
(VPOPCNTQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPOPCNTQMasked512load {sym} [off] ptr mask mem)
(VPORD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPORD512load {sym} [off] x ptr mem)
(VPORQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPORQ512load {sym} [off] x ptr mem)
(VPORDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORDMasked128load {sym} [off] x ptr mask mem)
(VPORDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORDMasked256load {sym} [off] x ptr mask mem)
(VPORDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORDMasked512load {sym} [off] x ptr mask mem)
(VPORQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORQMasked128load {sym} [off] x ptr mask mem)
(VPORQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORQMasked256load {sym} [off] x ptr mask mem)
(VPORQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORQMasked512load {sym} [off] x ptr mask mem)
(VPERMPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMPS256load {sym} [off] x ptr mem)
(VPERMD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMD256load {sym} [off] x ptr mem)
(VPERMPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMPS512load {sym} [off] x ptr mem)
(VPERMD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMD512load {sym} [off] x ptr mem)
(VPERMPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMPD256load {sym} [off] x ptr mem)
(VPERMQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMQ256load {sym} [off] x ptr mem)
(VPERMPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMPD512load {sym} [off] x ptr mem)
(VPERMQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMQ512load {sym} [off] x ptr mem)
(VPERMI2PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PS128load {sym} [off] x y ptr mem)
(VPERMI2D128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2D128load {sym} [off] x y ptr mem)
(VPERMI2PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PS256load {sym} [off] x y ptr mem)
(VPERMI2D256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2D256load {sym} [off] x y ptr mem)
(VPERMI2PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PS512load {sym} [off] x y ptr mem)
(VPERMI2D512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2D512load {sym} [off] x y ptr mem)
(VPERMI2PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PD128load {sym} [off] x y ptr mem)
(VPERMI2Q128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2Q128load {sym} [off] x y ptr mem)
(VPERMI2PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PD256load {sym} [off] x y ptr mem)
(VPERMI2Q256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2Q256load {sym} [off] x y ptr mem)
(VPERMI2PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PD512load {sym} [off] x y ptr mem)
(VPERMI2Q512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMI2Q512load {sym} [off] x y ptr mem)
(VPERMI2PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PSMasked128load {sym} [off] x y ptr mask mem)
(VPERMI2DMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2DMasked128load {sym} [off] x y ptr mask mem)
(VPERMI2PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PSMasked256load {sym} [off] x y ptr mask mem)
(VPERMI2DMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2DMasked256load {sym} [off] x y ptr mask mem)
(VPERMI2PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PSMasked512load {sym} [off] x y ptr mask mem)
(VPERMI2DMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2DMasked512load {sym} [off] x y ptr mask mem)
(VPERMI2PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PDMasked128load {sym} [off] x y ptr mask mem)
(VPERMI2QMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked128load {sym} [off] x y ptr mask mem)
(VPERMI2PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PDMasked256load {sym} [off] x y ptr mask mem)
(VPERMI2QMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked256load {sym} [off] x y ptr mask mem)
(VPERMI2PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PDMasked512load {sym} [off] x y ptr mask mem)
(VPERMI2QMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked512load {sym} [off] x y ptr mask mem)
(VPERMPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMPSMasked256load {sym} [off] x ptr mask mem)
(VPERMDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMDMasked256load {sym} [off] x ptr mask mem)
(VPERMPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMPSMasked512load {sym} [off] x ptr mask mem)
(VPERMDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMDMasked512load {sym} [off] x ptr mask mem)
(VPERMPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMPDMasked256load {sym} [off] x ptr mask mem)
(VPERMQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMQMasked256load {sym} [off] x ptr mask mem)
(VPERMPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMPDMasked512load {sym} [off] x ptr mask mem)
(VPERMQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMQMasked512load {sym} [off] x ptr mask mem)
(VRCP14PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRCP14PS512load {sym} [off] ptr mem)
(VRCP14PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRCP14PD128load {sym} [off] ptr mem)
(VRCP14PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRCP14PD256load {sym} [off] ptr mem)
(VRCP14PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRCP14PD512load {sym} [off] ptr mem)
(VRCP14PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRCP14PSMasked128load {sym} [off] ptr mask mem)
(VRCP14PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRCP14PSMasked256load {sym} [off] ptr mask mem)
(VRCP14PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRCP14PSMasked512load {sym} [off] ptr mask mem)
(VRCP14PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRCP14PDMasked128load {sym} [off] ptr mask mem)
(VRCP14PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRCP14PDMasked256load {sym} [off] ptr mask mem)
(VRCP14PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRCP14PDMasked512load {sym} [off] ptr mask mem)
(VRSQRT14PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PS512load {sym} [off] ptr mem)
(VRSQRT14PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PD128load {sym} [off] ptr mem)
(VRSQRT14PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PD256load {sym} [off] ptr mem)
(VRSQRT14PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PD512load {sym} [off] ptr mem)
(VRSQRT14PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PSMasked128load {sym} [off] ptr mask mem)
(VRSQRT14PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PSMasked256load {sym} [off] ptr mask mem)
(VRSQRT14PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PSMasked512load {sym} [off] ptr mask mem)
(VRSQRT14PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PDMasked128load {sym} [off] ptr mask mem)
(VRSQRT14PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PDMasked256load {sym} [off] ptr mask mem)
(VRSQRT14PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VRSQRT14PDMasked512load {sym} [off] ptr mask mem)
(VPROLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLVD128load {sym} [off] x ptr mem)
(VPROLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLVD256load {sym} [off] x ptr mem)
(VPROLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLVD512load {sym} [off] x ptr mem)
(VPROLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLVQ128load {sym} [off] x ptr mem)
(VPROLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLVQ256load {sym} [off] x ptr mem)
(VPROLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPROLVQ512load {sym} [off] x ptr mem)
(VPROLVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLVDMasked128load {sym} [off] x ptr mask mem)
(VPROLVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLVDMasked256load {sym} [off] x ptr mask mem)
(VPROLVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLVDMasked512load {sym} [off] x ptr mask mem)
(VPROLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLVQMasked128load {sym} [off] x ptr mask mem)
(VPROLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLVQMasked256load {sym} [off] x ptr mask mem)
(VPROLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPROLVQMasked512load {sym} [off] x ptr mask mem)
(VPRORVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORVD128load {sym} [off] x ptr mem)
(VPRORVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORVD256load {sym} [off] x ptr mem)
(VPRORVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORVD512load {sym} [off] x ptr mem)
(VPRORVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORVQ128load {sym} [off] x ptr mem)
(VPRORVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORVQ256load {sym} [off] x ptr mem)
(VPRORVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPRORVQ512load {sym} [off] x ptr mem)
(VPRORVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVDMasked128load {sym} [off] x ptr mask mem)
(VPRORVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVDMasked256load {sym} [off] x ptr mask mem)
(VPRORVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVDMasked512load {sym} [off] x ptr mask mem)
(VPRORVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVQMasked128load {sym} [off] x ptr mask mem)
(VPRORVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVQMasked256load {sym} [off] x ptr mask mem)
(VPRORVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPRORVQMasked512load {sym} [off] x ptr mask mem)
(VSCALEFPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPS128load {sym} [off] x ptr mem)
(VSCALEFPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPS256load {sym} [off] x ptr mem)
(VSCALEFPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPS512load {sym} [off] x ptr mem)
(VSCALEFPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPD128load {sym} [off] x ptr mem)
(VSCALEFPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPD256load {sym} [off] x ptr mem)
(VSCALEFPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPD512load {sym} [off] x ptr mem)
(VSCALEFPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPSMasked128load {sym} [off] x ptr mask mem)
(VSCALEFPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPSMasked256load {sym} [off] x ptr mask mem)
(VSCALEFPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPSMasked512load {sym} [off] x ptr mask mem)
(VSCALEFPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPDMasked128load {sym} [off] x ptr mask mem)
(VSCALEFPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPDMasked256load {sym} [off] x ptr mask mem)
(VSCALEFPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPDMasked512load {sym} [off] x ptr mask mem)
(VPSLLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVD128load {sym} [off] x ptr mem)
(VPSLLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVD256load {sym} [off] x ptr mem)
(VPSLLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVD512load {sym} [off] x ptr mem)
(VPSLLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQ128load {sym} [off] x ptr mem)
(VPSLLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQ256load {sym} [off] x ptr mem)
(VPSLLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQ512load {sym} [off] x ptr mem)
(VPSHLDVD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVD128load {sym} [off] x y ptr mem)
(VPSHLDVD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVD256load {sym} [off] x y ptr mem)
(VPSHLDVD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVD512load {sym} [off] x y ptr mem)
(VPSHLDVQ128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVQ128load {sym} [off] x y ptr mem)
(VPSHLDVQ256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVQ256load {sym} [off] x y ptr mem)
(VPSHLDVQ512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVQ512load {sym} [off] x y ptr mem)
(VPSHLDVDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVDMasked128load {sym} [off] x y ptr mask mem)
(VPSHLDVDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVDMasked256load {sym} [off] x y ptr mask mem)
(VPSHLDVDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVDMasked512load {sym} [off] x y ptr mask mem)
(VPSHLDVQMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVQMasked128load {sym} [off] x y ptr mask mem)
(VPSHLDVQMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVQMasked256load {sym} [off] x y ptr mask mem)
(VPSHLDVQMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVQMasked512load {sym} [off] x y ptr mask mem)
(VPSLLVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVDMasked128load {sym} [off] x ptr mask mem)
(VPSLLVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVDMasked256load {sym} [off] x ptr mask mem)
(VPSLLVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVDMasked512load {sym} [off] x ptr mask mem)
(VPSLLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQMasked128load {sym} [off] x ptr mask mem)
(VPSLLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQMasked256load {sym} [off] x ptr mask mem)
(VPSLLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQMasked512load {sym} [off] x ptr mask mem)
(VPSRAVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVD128load {sym} [off] x ptr mem)
(VPSRAVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVD256load {sym} [off] x ptr mem)
(VPSRAVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVD512load {sym} [off] x ptr mem)
(VPSRAVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQ128load {sym} [off] x ptr mem)
(VPSRAVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQ256load {sym} [off] x ptr mem)
(VPSRAVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQ512load {sym} [off] x ptr mem)
(VPSRLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVD128load {sym} [off] x ptr mem)
(VPSRLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVD256load {sym} [off] x ptr mem)
(VPSRLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVD512load {sym} [off] x ptr mem)
(VPSRLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQ128load {sym} [off] x ptr mem)
(VPSRLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQ256load {sym} [off] x ptr mem)
(VPSRLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQ512load {sym} [off] x ptr mem)
(VPSHRDVD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVD128load {sym} [off] x y ptr mem)
(VPSHRDVD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVD256load {sym} [off] x y ptr mem)
(VPSHRDVD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVD512load {sym} [off] x y ptr mem)
(VPSHRDVQ128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVQ128load {sym} [off] x y ptr mem)
(VPSHRDVQ256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVQ256load {sym} [off] x y ptr mem)
(VPSHRDVQ512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVQ512load {sym} [off] x y ptr mem)
(VPSHRDVDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVDMasked128load {sym} [off] x y ptr mask mem)
(VPSHRDVDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVDMasked256load {sym} [off] x y ptr mask mem)
(VPSHRDVDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVDMasked512load {sym} [off] x y ptr mask mem)
(VPSHRDVQMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVQMasked128load {sym} [off] x y ptr mask mem)
(VPSHRDVQMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVQMasked256load {sym} [off] x y ptr mask mem)
(VPSHRDVQMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVQMasked512load {sym} [off] x y ptr mask mem)
(VPSRAVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVDMasked128load {sym} [off] x ptr mask mem)
(VPSRAVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVDMasked256load {sym} [off] x ptr mask mem)
(VPSRAVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVDMasked512load {sym} [off] x ptr mask mem)
(VPSRAVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQMasked128load {sym} [off] x ptr mask mem)
(VPSRAVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQMasked256load {sym} [off] x ptr mask mem)
(VPSRAVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQMasked512load {sym} [off] x ptr mask mem)
(VPSRLVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVDMasked128load {sym} [off] x ptr mask mem)
(VPSRLVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVDMasked256load {sym} [off] x ptr mask mem)
(VPSRLVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVDMasked512load {sym} [off] x ptr mask mem)
(VPSRLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQMasked128load {sym} [off] x ptr mask mem)
(VPSRLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQMasked256load {sym} [off] x ptr mask mem)
(VPSRLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQMasked512load {sym} [off] x ptr mask mem)
(VSQRTPS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPS128load {sym} [off] ptr mem)
(VSQRTPS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPS256load {sym} [off] ptr mem)
(VSQRTPS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPS512load {sym} [off] ptr mem)
(VSQRTPD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPD128load {sym} [off] ptr mem)
(VSQRTPD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPD256load {sym} [off] ptr mem)
(VSQRTPD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPD512load {sym} [off] ptr mem)
(VSQRTPSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPSMasked128load {sym} [off] ptr mask mem)
(VSQRTPSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPSMasked256load {sym} [off] ptr mask mem)
(VSQRTPSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPSMasked512load {sym} [off] ptr mask mem)
(VSQRTPDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPDMasked128load {sym} [off] ptr mask mem)
(VSQRTPDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPDMasked256load {sym} [off] ptr mask mem)
(VSQRTPDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPDMasked512load {sym} [off] ptr mask mem)
(VSUBPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPS128load {sym} [off] x ptr mem)
(VSUBPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPS256load {sym} [off] x ptr mem)
(VSUBPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPS512load {sym} [off] x ptr mem)
(VSUBPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPD128load {sym} [off] x ptr mem)
(VSUBPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPD256load {sym} [off] x ptr mem)
(VSUBPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPD512load {sym} [off] x ptr mem)
(VPSUBD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBD128load {sym} [off] x ptr mem)
(VPSUBD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBD256load {sym} [off] x ptr mem)
(VPSUBD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBD512load {sym} [off] x ptr mem)
(VPSUBQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBQ128load {sym} [off] x ptr mem)
(VPSUBQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBQ256load {sym} [off] x ptr mem)
(VPSUBQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBQ512load {sym} [off] x ptr mem)
(VSUBPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPSMasked128load {sym} [off] x ptr mask mem)
(VSUBPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPSMasked256load {sym} [off] x ptr mask mem)
(VSUBPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPSMasked512load {sym} [off] x ptr mask mem)
(VSUBPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPDMasked128load {sym} [off] x ptr mask mem)
(VSUBPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPDMasked256load {sym} [off] x ptr mask mem)
(VSUBPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPDMasked512load {sym} [off] x ptr mask mem)
(VPSUBDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBDMasked128load {sym} [off] x ptr mask mem)
(VPSUBDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBDMasked256load {sym} [off] x ptr mask mem)
(VPSUBDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBDMasked512load {sym} [off] x ptr mask mem)
(VPSUBQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBQMasked128load {sym} [off] x ptr mask mem)
(VPSUBQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBQMasked256load {sym} [off] x ptr mask mem)
(VPSUBQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSUBQMasked512load {sym} [off] x ptr mask mem)
(VPXORD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPXORD512load {sym} [off] x ptr mem)
(VPXORQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPXORQ512load {sym} [off] x ptr mem)
(VPXORDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPXORDMasked128load {sym} [off] x ptr mask mem)
(VPXORDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPXORDMasked256load {sym} [off] x ptr mask mem)
(VPXORDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPXORDMasked512load {sym} [off] x ptr mask mem)
(VPXORQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPXORQMasked128load {sym} [off] x ptr mask mem)
(VPXORQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPXORQMasked256load {sym} [off] x ptr mask mem)
(VPXORQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPXORQMasked512load {sym} [off] x ptr mask mem)
(VPBLENDMDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPBLENDMDMasked512load {sym} [off] x ptr mask mem)
(VPBLENDMQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPBLENDMQMasked512load {sym} [off] x ptr mask mem)