2015-06-06 16:03:33 -07:00
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// autogenerated: do not edit!
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// generated from gen/*Ops.go
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package ssa
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2015-06-16 11:11:16 -07:00
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import "cmd/internal/obj/x86"
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2015-06-06 16:03:33 -07:00
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const (
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blockInvalid BlockKind = iota
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BlockAMD64EQ
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BlockAMD64NE
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BlockAMD64LT
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BlockAMD64LE
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BlockAMD64GT
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BlockAMD64GE
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BlockAMD64ULT
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BlockAMD64ULE
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BlockAMD64UGT
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BlockAMD64UGE
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BlockExit
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2015-07-09 21:24:12 -06:00
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BlockDead
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2015-06-06 16:03:33 -07:00
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BlockPlain
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BlockIf
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BlockCall
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)
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var blockString = [...]string{
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blockInvalid: "BlockInvalid",
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BlockAMD64EQ: "EQ",
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BlockAMD64NE: "NE",
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BlockAMD64LT: "LT",
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BlockAMD64LE: "LE",
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BlockAMD64GT: "GT",
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BlockAMD64GE: "GE",
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BlockAMD64ULT: "ULT",
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BlockAMD64ULE: "ULE",
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BlockAMD64UGT: "UGT",
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BlockAMD64UGE: "UGE",
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BlockExit: "Exit",
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2015-07-09 21:24:12 -06:00
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BlockDead: "Dead",
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2015-06-06 16:03:33 -07:00
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BlockPlain: "Plain",
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BlockIf: "If",
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BlockCall: "Call",
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}
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func (k BlockKind) String() string { return blockString[k] }
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const (
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OpInvalid Op = iota
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OpAMD64MULQ
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OpAMD64MULQconst
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OpAMD64SHLQ
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OpAMD64SHLQconst
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2015-06-10 10:39:57 -07:00
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OpAMD64SHRQ
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OpAMD64SHRQconst
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OpAMD64SARQ
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OpAMD64SARQconst
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2015-07-10 11:25:48 -06:00
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OpAMD64XORQconst
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2015-06-06 16:03:33 -07:00
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OpAMD64CMPQ
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OpAMD64CMPQconst
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2015-07-21 18:06:15 +02:00
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OpAMD64CMPL
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OpAMD64CMPW
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OpAMD64CMPB
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2015-06-06 16:03:33 -07:00
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OpAMD64TESTQ
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OpAMD64TESTB
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2015-06-10 10:39:57 -07:00
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OpAMD64SBBQcarrymask
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2015-06-06 16:03:33 -07:00
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OpAMD64SETEQ
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OpAMD64SETNE
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OpAMD64SETL
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2015-06-24 17:48:22 -07:00
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OpAMD64SETLE
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2015-06-06 16:03:33 -07:00
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OpAMD64SETG
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OpAMD64SETGE
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OpAMD64SETB
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2015-07-24 12:47:00 -07:00
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OpAMD64SETBE
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OpAMD64SETA
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OpAMD64SETAE
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2015-06-10 10:39:57 -07:00
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OpAMD64CMOVQCC
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2015-06-14 11:38:46 -07:00
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OpAMD64MOVBQSX
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2015-07-22 13:46:15 -07:00
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OpAMD64MOVBQZX
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OpAMD64MOVWQSX
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OpAMD64MOVWQZX
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OpAMD64MOVLQSX
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OpAMD64MOVLQZX
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2015-06-06 16:03:33 -07:00
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OpAMD64MOVQconst
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OpAMD64LEAQ
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2015-06-19 21:02:28 -07:00
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OpAMD64LEAQ1
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2015-06-06 16:03:33 -07:00
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OpAMD64LEAQ2
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OpAMD64LEAQ4
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OpAMD64LEAQ8
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OpAMD64MOVBload
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OpAMD64MOVBQSXload
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[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
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OpAMD64MOVBQZXload
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2015-06-14 11:38:46 -07:00
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OpAMD64MOVWload
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OpAMD64MOVLload
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2015-06-06 16:03:33 -07:00
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OpAMD64MOVQload
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OpAMD64MOVQloadidx8
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OpAMD64MOVBstore
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2015-06-14 11:38:46 -07:00
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OpAMD64MOVWstore
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OpAMD64MOVLstore
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2015-06-06 16:03:33 -07:00
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OpAMD64MOVQstore
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OpAMD64MOVQstoreidx8
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2015-06-27 15:45:20 +01:00
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OpAMD64MOVXzero
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OpAMD64REPSTOSQ
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2015-06-06 16:03:33 -07:00
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OpAMD64MOVQloadglobal
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OpAMD64MOVQstoreglobal
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2015-06-10 15:03:06 -07:00
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OpAMD64CALLstatic
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OpAMD64CALLclosure
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2015-06-06 16:03:33 -07:00
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OpAMD64REPMOVSB
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2015-07-21 16:58:18 +02:00
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OpAMD64ADDQ
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OpAMD64ADDQconst
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2015-06-06 16:03:33 -07:00
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OpAMD64ADDL
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2015-06-14 11:38:46 -07:00
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OpAMD64ADDW
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OpAMD64ADDB
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2015-07-21 16:58:18 +02:00
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OpAMD64SUBQ
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OpAMD64SUBQconst
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2015-07-19 15:48:20 -07:00
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OpAMD64SUBL
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OpAMD64SUBW
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OpAMD64SUBB
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2015-07-21 16:58:18 +02:00
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OpAMD64NEGQ
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OpAMD64NEGL
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OpAMD64NEGW
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OpAMD64NEGB
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2015-07-22 13:46:15 -07:00
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OpAMD64MULL
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OpAMD64MULW
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2015-07-28 14:58:49 +02:00
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OpAMD64ANDQ
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OpAMD64ANDQconst
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OpAMD64ANDL
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OpAMD64ANDW
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OpAMD64ANDB
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2015-06-06 16:03:33 -07:00
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OpAMD64InvertFlags
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2015-07-19 15:48:20 -07:00
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OpAdd8
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OpAdd16
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OpAdd32
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OpAdd64
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OpAddPtr
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OpSub8
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OpSub16
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OpSub32
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OpSub64
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2015-07-22 13:46:15 -07:00
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OpMul8
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OpMul16
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OpMul32
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OpMul64
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OpMulPtr
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2015-07-28 14:58:49 +02:00
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OpAnd8
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OpAnd16
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OpAnd32
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OpAnd64
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2015-07-19 15:48:20 -07:00
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OpLsh8
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OpLsh16
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OpLsh32
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OpLsh64
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OpRsh8
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OpRsh8U
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OpRsh16
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OpRsh16U
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OpRsh32
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OpRsh32U
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OpRsh64
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OpRsh64U
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OpEq8
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OpEq16
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OpEq32
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OpEq64
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2015-07-27 13:17:45 -07:00
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OpEqPtr
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OpEqFat
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2015-07-19 15:48:20 -07:00
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OpNeq8
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OpNeq16
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OpNeq32
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OpNeq64
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2015-07-27 13:17:45 -07:00
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OpNeqPtr
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OpNeqFat
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2015-07-19 15:48:20 -07:00
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OpLess8
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OpLess8U
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OpLess16
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OpLess16U
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OpLess32
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OpLess32U
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OpLess64
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OpLess64U
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OpLeq8
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OpLeq8U
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OpLeq16
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OpLeq16U
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OpLeq32
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OpLeq32U
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OpLeq64
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OpLeq64U
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OpGreater8
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OpGreater8U
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OpGreater16
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OpGreater16U
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OpGreater32
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OpGreater32U
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OpGreater64
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OpGreater64U
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OpGeq8
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OpGeq8U
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OpGeq16
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OpGeq16U
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OpGeq32
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OpGeq32U
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OpGeq64
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OpGeq64U
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2015-07-10 11:25:48 -06:00
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OpNot
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2015-07-21 16:58:18 +02:00
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OpNeg8
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OpNeg16
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OpNeg32
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OpNeg64
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2015-06-06 16:03:33 -07:00
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OpPhi
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OpCopy
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OpConst
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OpArg
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2015-06-19 21:02:28 -07:00
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OpAddr
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2015-06-06 16:03:33 -07:00
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OpSP
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2015-06-19 21:02:28 -07:00
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OpSB
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2015-06-06 16:03:33 -07:00
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OpFunc
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OpLoad
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OpStore
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OpMove
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2015-06-27 15:45:20 +01:00
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OpZero
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2015-06-10 15:03:06 -07:00
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OpClosureCall
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2015-06-06 16:03:33 -07:00
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OpStaticCall
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[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
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OpSignExt8to16
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OpSignExt8to32
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OpSignExt8to64
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OpSignExt16to32
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OpSignExt16to64
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OpSignExt32to64
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OpZeroExt8to16
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OpZeroExt8to32
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OpZeroExt8to64
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OpZeroExt16to32
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OpZeroExt16to64
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OpZeroExt32to64
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OpTrunc16to8
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OpTrunc32to8
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OpTrunc32to16
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OpTrunc64to8
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OpTrunc64to16
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OpTrunc64to32
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2015-06-06 16:03:33 -07:00
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OpConvNop
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OpIsNonNil
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OpIsInBounds
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OpArrayIndex
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OpPtrIndex
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OpOffPtr
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2015-07-15 21:33:49 -07:00
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OpStructSelect
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2015-06-06 16:03:33 -07:00
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OpSliceMake
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OpSlicePtr
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OpSliceLen
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OpSliceCap
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OpStringMake
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OpStringPtr
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OpStringLen
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2015-07-24 14:51:51 -07:00
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OpStoreReg
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OpLoadReg
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2015-06-06 16:03:33 -07:00
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OpFwdRef
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)
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var opcodeTable = [...]opInfo{
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{name: "OpInvalid"},
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{
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name: "MULQ",
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2015-06-16 11:11:16 -07:00
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asm: x86.AIMULQ,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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},
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},
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{
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name: "MULQconst",
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2015-06-16 11:11:16 -07:00
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asm: x86.AIMULQ,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SHLQ",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ASHLQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
2, // .CX
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SHLQconst",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ASHLQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
|
|
|
|
name: "SHRQ",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ASHRQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
2, // .CX
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SHRQconst",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ASHRQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SARQ",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ASARQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
2, // .CX
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SARQconst",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ASARQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-10 11:25:48 -06:00
|
|
|
{
|
|
|
|
|
name: "XORQconst",
|
|
|
|
|
asm: x86.AXORQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
|
|
|
|
name: "CMPQ",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ACMPQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMPQconst",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ACMPQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 18:06:15 +02:00
|
|
|
{
|
|
|
|
|
name: "CMPL",
|
|
|
|
|
asm: x86.ACMPL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMPW",
|
|
|
|
|
asm: x86.ACMPW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMPB",
|
|
|
|
|
asm: x86.ACMPB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
|
|
|
|
name: "TESTQ",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ATESTQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "TESTB",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ATESTB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
|
|
|
|
name: "SBBQcarrymask",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ASBBQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
|
|
|
|
name: "SETEQ",
|
2015-07-20 15:21:49 -07:00
|
|
|
asm: x86.ASETEQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SETNE",
|
2015-07-20 15:21:49 -07:00
|
|
|
asm: x86.ASETNE,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SETL",
|
2015-07-20 15:21:49 -07:00
|
|
|
asm: x86.ASETLT,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-24 17:48:22 -07:00
|
|
|
{
|
|
|
|
|
name: "SETLE",
|
2015-07-20 15:21:49 -07:00
|
|
|
asm: x86.ASETLE,
|
2015-06-24 17:48:22 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
|
|
|
|
name: "SETG",
|
2015-07-20 15:21:49 -07:00
|
|
|
asm: x86.ASETGT,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SETGE",
|
2015-07-20 15:21:49 -07:00
|
|
|
asm: x86.ASETGE,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SETB",
|
2015-07-20 15:21:49 -07:00
|
|
|
asm: x86.ASETCS,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-24 12:47:00 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SETBE",
|
|
|
|
|
asm: x86.ASETLS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SETA",
|
|
|
|
|
asm: x86.ASETHI,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SETAE",
|
|
|
|
|
asm: x86.ASETCC,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
|
|
|
|
name: "CMOVQCC",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-14 11:38:46 -07:00
|
|
|
{
|
2015-07-22 13:46:15 -07:00
|
|
|
name: "MOVBQSX",
|
|
|
|
|
asm: x86.AMOVBQSX,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBQZX",
|
|
|
|
|
asm: x86.AMOVBQZX,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWQSX",
|
|
|
|
|
asm: x86.AMOVWQSX,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-22 13:46:15 -07:00
|
|
|
name: "MOVWQZX",
|
|
|
|
|
asm: x86.AMOVWQZX,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVLQSX",
|
|
|
|
|
asm: x86.AMOVLQSX,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVLQZX",
|
|
|
|
|
asm: x86.AMOVLQZX,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVQconst",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "LEAQ",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-06-19 21:02:28 -07:00
|
|
|
name: "LEAQ1",
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-06-19 21:02:28 -07:00
|
|
|
name: "LEAQ2",
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-06-19 21:02:28 -07:00
|
|
|
name: "LEAQ4",
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-06-19 21:02:28 -07:00
|
|
|
name: "LEAQ8",
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-06-19 21:02:28 -07:00
|
|
|
inputs: []regMask{
|
|
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBload",
|
2015-06-16 13:33:32 -07:00
|
|
|
asm: x86.AMOVB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-06-06 16:03:33 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
name: "MOVBQSXload",
|
|
|
|
|
asm: x86.AMOVBQSX,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-06-06 16:03:33 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
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name: "MOVBQZXload",
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asm: x86.AMOVBQZX,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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2015-06-06 16:03:33 -07:00
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0,
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},
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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},
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},
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2015-06-14 11:38:46 -07:00
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{
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name: "MOVWload",
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asm: x86.AMOVW,
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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2015-06-14 11:38:46 -07:00
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0,
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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{
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name: "MOVLload",
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asm: x86.AMOVL,
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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2015-06-14 11:38:46 -07:00
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0,
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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2015-06-06 16:03:33 -07:00
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{
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name: "MOVQload",
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2015-06-16 13:33:32 -07:00
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asm: x86.AMOVQ,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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2015-06-06 16:03:33 -07:00
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0,
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},
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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},
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},
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{
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name: "MOVQloadidx8",
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2015-06-14 11:38:46 -07:00
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asm: x86.AMOVQ,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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0,
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},
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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},
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},
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{
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name: "MOVBstore",
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2015-06-16 11:11:16 -07:00
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asm: x86.AMOVB,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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0,
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},
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},
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},
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2015-06-14 11:38:46 -07:00
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{
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name: "MOVWstore",
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asm: x86.AMOVW,
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-14 11:38:46 -07:00
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0,
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},
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},
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},
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{
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name: "MOVLstore",
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asm: x86.AMOVL,
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-14 11:38:46 -07:00
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0,
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},
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},
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},
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2015-06-06 16:03:33 -07:00
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{
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name: "MOVQstore",
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2015-06-16 11:11:16 -07:00
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asm: x86.AMOVQ,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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0,
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},
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},
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},
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{
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name: "MOVQstoreidx8",
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2015-07-27 16:36:36 -07:00
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asm: x86.AMOVQ,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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0,
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},
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},
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},
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2015-06-27 15:45:20 +01:00
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{
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name: "MOVXzero",
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reg: regInfo{
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inputs: []regMask{
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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0,
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},
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},
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},
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{
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name: "REPSTOSQ",
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reg: regInfo{
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inputs: []regMask{
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128, // .DI
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2, // .CX
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},
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clobbers: 131, // .AX .CX .DI
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},
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},
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2015-06-06 16:03:33 -07:00
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{
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name: "MOVQloadglobal",
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2015-07-21 07:10:56 -07:00
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reg: regInfo{},
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2015-06-06 16:03:33 -07:00
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},
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{
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name: "MOVQstoreglobal",
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2015-07-21 07:10:56 -07:00
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reg: regInfo{},
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2015-06-06 16:03:33 -07:00
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},
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2015-06-10 15:03:06 -07:00
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{
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name: "CALLstatic",
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2015-07-21 07:10:56 -07:00
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reg: regInfo{},
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2015-06-10 15:03:06 -07:00
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},
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{
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name: "CALLclosure",
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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4, // .DX
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2015-06-10 15:03:06 -07:00
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0,
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},
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},
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},
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2015-06-06 16:03:33 -07:00
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{
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name: "REPMOVSB",
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reg: regInfo{
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inputs: []regMask{
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2015-06-11 15:52:08 -07:00
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128, // .DI
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64, // .SI
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2, // .CX
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2015-06-06 16:03:33 -07:00
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},
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2015-06-11 15:52:08 -07:00
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clobbers: 194, // .CX .SI .DI
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2015-06-06 16:03:33 -07:00
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},
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},
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2015-07-21 16:58:18 +02:00
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{
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name: "ADDQ",
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reg: regInfo{
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inputs: []regMask{
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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{
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name: "ADDQconst",
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reg: regInfo{
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inputs: []regMask{
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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2015-06-06 16:03:33 -07:00
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{
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name: "ADDL",
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2015-06-16 11:11:16 -07:00
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asm: x86.AADDL,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-14 11:38:46 -07:00
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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{
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name: "ADDW",
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asm: x86.AADDW,
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-14 11:38:46 -07:00
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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{
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name: "ADDB",
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asm: x86.AADDB,
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reg: regInfo{
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inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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|
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|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
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},
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outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
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},
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},
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},
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2015-07-21 16:58:18 +02:00
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{
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name: "SUBQ",
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asm: x86.ASUBQ,
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reg: regInfo{
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inputs: []regMask{
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|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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{
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name: "SUBQconst",
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asm: x86.ASUBQ,
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reg: regInfo{
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inputs: []regMask{
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|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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|
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outputs: []regMask{
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|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
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},
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},
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},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
|
|
|
|
name: "SUBL",
|
|
|
|
|
asm: x86.ASUBL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SUBW",
|
|
|
|
|
asm: x86.ASUBW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SUBB",
|
|
|
|
|
asm: x86.ASUBB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
|
|
|
|
name: "NEGQ",
|
|
|
|
|
asm: x86.ANEGQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "NEGL",
|
|
|
|
|
asm: x86.ANEGL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "NEGW",
|
|
|
|
|
asm: x86.ANEGW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "NEGB",
|
|
|
|
|
asm: x86.ANEGB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-22 13:46:15 -07:00
|
|
|
{
|
|
|
|
|
name: "MULL",
|
|
|
|
|
asm: x86.AIMULL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MULW",
|
|
|
|
|
asm: x86.AIMULW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
|
|
|
|
name: "ANDQ",
|
|
|
|
|
asm: x86.AANDQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ANDQconst",
|
|
|
|
|
asm: x86.AANDQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ANDL",
|
|
|
|
|
asm: x86.AANDL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ANDW",
|
|
|
|
|
asm: x86.AANDW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ANDB",
|
|
|
|
|
asm: x86.AANDB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
|
|
|
|
name: "InvertFlags",
|
2015-07-21 07:10:56 -07:00
|
|
|
reg: regInfo{},
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Add8",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Add16",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Add32",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Add64",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "AddPtr",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub8",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub16",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub32",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub64",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-22 13:46:15 -07:00
|
|
|
name: "Mul8",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mul16",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mul32",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mul64",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MulPtr",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
|
|
|
|
name: "And8",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "And16",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "And32",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "And64",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Lsh8",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Lsh16",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Lsh32",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Lsh64",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Rsh8",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Rsh8U",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Rsh16",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Rsh16U",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Rsh32",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Rsh32U",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Rsh64",
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
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{
|
2015-07-21 07:10:56 -07:00
|
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|
2015-07-19 15:48:20 -07:00
|
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{
|
2015-07-21 07:10:56 -07:00
|
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name: "Eq8",
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2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
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name: "Eq16",
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2015-07-19 15:48:20 -07:00
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{
|
2015-07-21 07:10:56 -07:00
|
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name: "Eq32",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
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2015-07-21 07:10:56 -07:00
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name: "Eq64",
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2015-07-19 15:48:20 -07:00
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generic: true,
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2015-07-27 13:17:45 -07:00
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{
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2015-07-19 15:48:20 -07:00
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{
|
2015-07-21 07:10:56 -07:00
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name: "Neq8",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
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name: "Neq16",
|
2015-07-19 15:48:20 -07:00
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{
|
2015-07-21 07:10:56 -07:00
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|
2015-07-19 15:48:20 -07:00
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{
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2015-07-21 07:10:56 -07:00
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2015-07-19 15:48:20 -07:00
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2015-07-27 13:17:45 -07:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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name: "Less16",
|
2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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name: "Less16U",
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2015-07-19 15:48:20 -07:00
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{
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2015-07-21 07:10:56 -07:00
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name: "Less32",
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2015-07-19 15:48:20 -07:00
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{
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2015-07-21 07:10:56 -07:00
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2015-07-19 15:48:20 -07:00
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generic: true,
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{
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2015-07-21 07:10:56 -07:00
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2015-07-19 15:48:20 -07:00
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{
|
2015-07-21 07:10:56 -07:00
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name: "Leq8",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
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name: "Leq8U",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
|
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name: "Leq16",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
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name: "Leq16U",
|
2015-07-19 15:48:20 -07:00
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{
|
2015-07-21 07:10:56 -07:00
|
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name: "Leq32",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
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name: "Leq32U",
|
2015-07-19 15:48:20 -07:00
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{
|
2015-07-21 07:10:56 -07:00
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name: "Leq64",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
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name: "Leq64U",
|
2015-07-19 15:48:20 -07:00
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{
|
2015-07-21 07:10:56 -07:00
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name: "Greater8",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
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name: "Greater8U",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
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name: "Greater16",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
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name: "Greater16U",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
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name: "Greater32",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
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name: "Greater32U",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
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name: "Greater64",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
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name: "Greater64U",
|
2015-07-19 15:48:20 -07:00
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generic: true,
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},
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{
|
2015-07-21 07:10:56 -07:00
|
|
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name: "Geq8",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
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},
|
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{
|
2015-07-21 07:10:56 -07:00
|
|
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name: "Geq8U",
|
2015-06-06 16:03:33 -07:00
|
|
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generic: true,
|
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},
|
2015-06-24 17:48:22 -07:00
|
|
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{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq16",
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
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|
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},
|
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|
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{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq16U",
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
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|
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},
|
2015-06-06 16:03:33 -07:00
|
|
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{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq32",
|
2015-06-24 17:48:22 -07:00
|
|
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generic: true,
|
|
|
|
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},
|
|
|
|
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{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq32U",
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
|
|
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},
|
|
|
|
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{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq64",
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
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|
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},
|
|
|
|
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{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq64U",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
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},
|
2015-07-10 11:25:48 -06:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Not",
|
2015-07-10 11:25:48 -06:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
|
|
|
|
name: "Neg8",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg16",
|
|
|
|
|
generic: true,
|
|
|
|
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},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg32",
|
|
|
|
|
generic: true,
|
|
|
|
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},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg64",
|
|
|
|
|
generic: true,
|
|
|
|
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},
|
2015-06-06 16:03:33 -07:00
|
|
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{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Phi",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Copy",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Const",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Arg",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Addr",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SP",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SB",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
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},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Func",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Load",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Store",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Move",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-27 15:45:20 +01:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Zero",
|
2015-06-27 15:45:20 +01:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "ClosureCall",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StaticCall",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
name: "SignExt8to16",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt8to32",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt8to64",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt16to32",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt16to64",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt32to64",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt8to16",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt8to32",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt8to64",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt16to32",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt16to64",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt32to64",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc16to8",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc32to8",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc32to16",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc64to8",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc64to16",
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc64to32",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "ConvNop",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "IsNonNil",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "IsInBounds",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "ArrayIndex",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "PtrIndex",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "OffPtr",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-15 21:33:49 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StructSelect",
|
2015-07-15 21:33:49 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SliceMake",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SlicePtr",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SliceLen",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SliceCap",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StringMake",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StringPtr",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StringLen",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-24 14:51:51 -07:00
|
|
|
name: "StoreReg",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-24 14:51:51 -07:00
|
|
|
name: "LoadReg",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "FwdRef",
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
}
|
|
|
|
|
|
2015-06-16 11:11:16 -07:00
|
|
|
func (o Op) Asm() int { return opcodeTable[o].asm }
|
2015-06-06 16:03:33 -07:00
|
|
|
func (o Op) String() string { return opcodeTable[o].name }
|