cmd/internal/obj/riscv: add support for Zicond instructions

This patch implement assembler for the Zicond extension: CZEROEQZ and CZERONEZ.

Follow-up to CL 631576
Updates #75350

Change-Id: Icf4be131fe61c3b7a3bde4811cf42dc807660907
GitHub-Last-Rev: 6539cc86cb
GitHub-Pull-Request: golang/go#75408
Reviewed-on: https://go-review.googlesource.com/c/go/+/702677
Reviewed-by: Mark Freeman <markfreeman@google.com>
Reviewed-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
TryBot-Bypass: Joel Sing <joel@sing.id.au>

src/cmd/asm/internal/asm/testdata/riscv64.s

@@ -195,6 +195,12 @@ start:
 	RDTIME		X5				// f32210c0
 	RDINSTRET	X5				// f32220c0
 
+	// 12.3: Integer Conditional Operations (Zicond)
+	CZEROEQZ	X5, X6, X7			// b353530e
+	CZEROEQZ	X5, X7				// b3d3530e
+	CZERONEZ	X5, X6, X7			// b373530e
+	CZERONEZ	X5, X7				// b3f3530e
+
 	// 13.1: Multiplication Operations
 	MUL	X5, X6, X7				// b3035302
 	MULH	X5, X6, X7				// b3135302

src/cmd/internal/obj/riscv/anames.go

@@ -61,6 +61,8 @@ var Anames = []string{
 	"CSRRWI",
 	"CSRRSI",
 	"CSRRCI",
+	"CZEROEQZ",
+	"CZERONEZ",
 	"MUL",
 	"MULH",
 	"MULHU",

src/cmd/internal/obj/riscv/cpu.go

@@ -409,6 +409,10 @@ const (
 	ACSRRSI
 	ACSRRCI
 
+	// 12.3: Integer Conditional Operations (Zicond)
+	ACZEROEQZ
+	ACZERONEZ
+
 	// 13.1: Multiplication Operations
 	AMUL
 	AMULH

src/cmd/internal/obj/riscv/inst.go

@@ -1,4 +1,4 @@
-// Code generated by ./parse.py -go rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbs rv_zicsr; DO NOT EDIT.
+// Code generated by ./parse.py -go rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbs rv_zicond rv_zicsr; DO NOT EDIT.
 package riscv
 
 import "cmd/internal/obj"
@@ -194,6 +194,10 @@ func encode(a obj.As) *inst {
 		return &inst{0x13, 0x1, 0x0, 0x1, 1537, 0x30}
 	case ACTZW:
 		return &inst{0x1b, 0x1, 0x0, 0x1, 1537, 0x30}
+	case ACZEROEQZ:
+		return &inst{0x33, 0x5, 0x0, 0x0, 224, 0x7}
+	case ACZERONEZ:
+		return &inst{0x33, 0x7, 0x0, 0x0, 224, 0x7}
 	case ADIV:
 		return &inst{0x33, 0x4, 0x0, 0x0, 32, 0x1}
 	case ADIVU:

src/cmd/internal/obj/riscv/obj.go

@@ -1948,6 +1948,10 @@ var instructions = [ALAST & obj.AMask]instructionData{
 	ACSRRW & obj.AMask:  {enc: iIIEncoding, immForm: ACSRRWI},
 	ACSRRWI & obj.AMask: {enc: iIIEncoding},
 
+	// 12.3: "Zicond" Extension for Integer Conditional Operations
+	ACZERONEZ & obj.AMask: {enc: rIIIEncoding, ternary: true},
+	ACZEROEQZ & obj.AMask: {enc: rIIIEncoding, ternary: true},
+
 	// 13.1: Multiplication Operations
 	AMUL & obj.AMask:    {enc: rIIIEncoding, ternary: true},
 	AMULH & obj.AMask:   {enc: rIIIEncoding, ternary: true},