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don't fail hard on some odd io port accesses from archhurd

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Fabian 2025-08-22 16:27:15 -06:00
parent 73945e4574
commit a480e88594
4 changed files with 20 additions and 4 deletions
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6
src/acpi.js
View file

@ -69,7 +69,11 @@ export function ACPI(cpu)
});
// ACPI status
io.register_read(0xB004, this, undefined, function()
io.register_read(0xB004, this, function()
{
dbg_log("ACPI status read8", LOG_ACPI);
return this.status & 0xFF;
}, function()
{
dbg_log("ACPI status read", LOG_ACPI);
return this.status;

7
src/ne2k.js
View file

@ -396,7 +396,12 @@ export function Ne2k(cpu, bus, preserve_mac_from_state_image, mac_address_transl
{
dbg_log("Read cmd", LOG_NET);
return this.cr;
});
}, function()
{
dbg_log("Read16 cmd", LOG_NET);
return this.cr;
}
);
io.register_write(this.port | E8390_CMD, this, function(data_byte)
{

2
src/rust/cpu/instructions_0f.rs
View file

@ -1224,7 +1224,7 @@ pub unsafe fn instr_0F30() {
dbg_log!("GS Base written");
},
IA32_PERFEVTSEL0 | IA32_PERFEVTSEL1 => {}, // linux/9legacy
IA32_PMC0 | IA32_PMC1 => {}, // linux
IA32_PMC0 | IA32_PMC1 => {}, // linux
IA32_PAT => {},
IA32_SPEC_CTRL => {}, // linux 5.19
IA32_TSX_CTRL => {}, // linux 5.19

9
src/virtio.js
View file

@ -825,6 +825,13 @@ VirtIO.prototype.init_capabilities = function(capabilities)
return read(addr & ~3) >> ((addr & 3) << 3) & 0xFF;
};
// archhurd does these reads
const shim_read32_on_16 = function(addr)
{
dbg_log("Warning: 32-bit read from 16-bit virtio port", LOG_VIRTIO);
return read(addr);
};
switch(field.bytes)
{
case 4:
@ -835,7 +842,7 @@ VirtIO.prototype.init_capabilities = function(capabilities)
this.cpu.io.register_write(port, this, undefined, undefined, write);
break;
case 2:
this.cpu.io.register_read(port, this, shim_read8_on_16, read);
this.cpu.io.register_read(port, this, shim_read8_on_16, read, shim_read32_on_16);
this.cpu.io.register_read(port + 1, this, shim_read8_on_16);
this.cpu.io.register_write(port, this, undefined, write);
break;