2015-06-06 16:03:33 -07:00
|
|
|
// autogenerated from gen/AMD64.rules: do not edit!
|
|
|
|
|
// generated with: cd gen; go run *.go
|
2015-03-23 17:02:11 -07:00
|
|
|
package ssa
|
|
|
|
|
|
2015-06-06 16:03:33 -07:00
|
|
|
func rewriteValueAMD64(v *Value, config *Config) bool {
|
2015-03-23 17:02:11 -07:00
|
|
|
switch v.Op {
|
2015-06-06 16:03:33 -07:00
|
|
|
case OpAMD64ADDQ:
|
2015-05-18 16:44:20 -07:00
|
|
|
// match: (ADDQ x (MOVQconst [c]))
|
2015-03-23 17:02:11 -07:00
|
|
|
// cond:
|
2015-05-28 10:47:24 -07:00
|
|
|
// result: (ADDQconst [c] x)
|
2015-03-23 17:02:11 -07:00
|
|
|
{
|
|
|
|
|
x := v.Args[0]
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto endacffd55e74ee0ff59ad58a18ddfc9973
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
|
|
|
|
c := v.Args[1].Aux
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64ADDQconst
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = nil
|
2015-04-15 15:51:25 -07:00
|
|
|
v.resetArgs()
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = c
|
|
|
|
|
v.AddArg(x)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto endacffd55e74ee0ff59ad58a18ddfc9973
|
|
|
|
|
endacffd55e74ee0ff59ad58a18ddfc9973:
|
2015-03-23 17:02:11 -07:00
|
|
|
;
|
2015-05-18 16:44:20 -07:00
|
|
|
// match: (ADDQ (MOVQconst [c]) x)
|
2015-03-23 17:02:11 -07:00
|
|
|
// cond:
|
2015-05-28 10:47:24 -07:00
|
|
|
// result: (ADDQconst [c] x)
|
2015-03-23 17:02:11 -07:00
|
|
|
{
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end7166f476d744ab7a51125959d3d3c7e2
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
|
|
|
|
c := v.Args[0].Aux
|
|
|
|
|
x := v.Args[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64ADDQconst
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = nil
|
2015-04-15 15:51:25 -07:00
|
|
|
v.resetArgs()
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = c
|
|
|
|
|
v.AddArg(x)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end7166f476d744ab7a51125959d3d3c7e2
|
|
|
|
|
end7166f476d744ab7a51125959d3d3c7e2:
|
2015-04-15 15:51:25 -07:00
|
|
|
;
|
2015-05-28 10:47:24 -07:00
|
|
|
// match: (ADDQ x (SHLQconst [shift] y))
|
2015-04-15 15:51:25 -07:00
|
|
|
// cond: shift.(int64) == 3
|
|
|
|
|
// result: (LEAQ8 [int64(0)] x y)
|
|
|
|
|
{
|
|
|
|
|
x := v.Args[0]
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[1].Op != OpAMD64SHLQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto endaf4f724e1e17f2b116d336c07da0165d
|
2015-04-15 15:51:25 -07:00
|
|
|
}
|
|
|
|
|
shift := v.Args[1].Aux
|
|
|
|
|
y := v.Args[1].Args[0]
|
|
|
|
|
if !(shift.(int64) == 3) {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto endaf4f724e1e17f2b116d336c07da0165d
|
2015-04-15 15:51:25 -07:00
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64LEAQ8
|
2015-04-15 15:51:25 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.Aux = int64(0)
|
|
|
|
|
v.AddArg(x)
|
|
|
|
|
v.AddArg(y)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto endaf4f724e1e17f2b116d336c07da0165d
|
|
|
|
|
endaf4f724e1e17f2b116d336c07da0165d:
|
|
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case OpAMD64ADDQconst:
|
2015-05-28 10:47:24 -07:00
|
|
|
// match: (ADDQconst [c] (LEAQ8 [d] x y))
|
|
|
|
|
// cond:
|
|
|
|
|
// result: (LEAQ8 [addOff(c, d)] x y)
|
|
|
|
|
{
|
|
|
|
|
c := v.Aux
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[0].Op != OpAMD64LEAQ8 {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto ende2cc681c9abf9913288803fb1b39e639
|
|
|
|
|
}
|
|
|
|
|
d := v.Args[0].Aux
|
|
|
|
|
x := v.Args[0].Args[0]
|
|
|
|
|
y := v.Args[0].Args[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64LEAQ8
|
2015-05-28 10:47:24 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.Aux = addOff(c, d)
|
|
|
|
|
v.AddArg(x)
|
|
|
|
|
v.AddArg(y)
|
|
|
|
|
return true
|
|
|
|
|
}
|
|
|
|
|
goto ende2cc681c9abf9913288803fb1b39e639
|
|
|
|
|
ende2cc681c9abf9913288803fb1b39e639:
|
|
|
|
|
;
|
|
|
|
|
// match: (ADDQconst [off] x)
|
|
|
|
|
// cond: off.(int64) == 0
|
|
|
|
|
// result: (Copy x)
|
|
|
|
|
{
|
|
|
|
|
off := v.Aux
|
|
|
|
|
x := v.Args[0]
|
|
|
|
|
if !(off.(int64) == 0) {
|
|
|
|
|
goto endfa1c7cc5ac4716697e891376787f86ce
|
|
|
|
|
}
|
|
|
|
|
v.Op = OpCopy
|
|
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.AddArg(x)
|
|
|
|
|
return true
|
|
|
|
|
}
|
|
|
|
|
goto endfa1c7cc5ac4716697e891376787f86ce
|
|
|
|
|
endfa1c7cc5ac4716697e891376787f86ce:
|
2015-03-23 17:02:11 -07:00
|
|
|
;
|
|
|
|
|
case OpAdd:
|
|
|
|
|
// match: (Add <t> x y)
|
2015-04-15 15:51:25 -07:00
|
|
|
// cond: (is64BitInt(t) || isPtr(t))
|
2015-03-23 17:02:11 -07:00
|
|
|
// result: (ADDQ x y)
|
|
|
|
|
{
|
|
|
|
|
t := v.Type
|
|
|
|
|
x := v.Args[0]
|
|
|
|
|
y := v.Args[1]
|
2015-04-15 15:51:25 -07:00
|
|
|
if !(is64BitInt(t) || isPtr(t)) {
|
|
|
|
|
goto endf031c523d7dd08e4b8e7010a94cd94c9
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64ADDQ
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = nil
|
2015-04-15 15:51:25 -07:00
|
|
|
v.resetArgs()
|
2015-03-23 17:02:11 -07:00
|
|
|
v.AddArg(x)
|
|
|
|
|
v.AddArg(y)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-04-15 15:51:25 -07:00
|
|
|
goto endf031c523d7dd08e4b8e7010a94cd94c9
|
|
|
|
|
endf031c523d7dd08e4b8e7010a94cd94c9:
|
2015-03-23 17:02:11 -07:00
|
|
|
;
|
|
|
|
|
// match: (Add <t> x y)
|
|
|
|
|
// cond: is32BitInt(t)
|
|
|
|
|
// result: (ADDL x y)
|
|
|
|
|
{
|
|
|
|
|
t := v.Type
|
|
|
|
|
x := v.Args[0]
|
|
|
|
|
y := v.Args[1]
|
|
|
|
|
if !(is32BitInt(t)) {
|
2015-04-15 15:51:25 -07:00
|
|
|
goto end35a02a1587264e40cf1055856ff8445a
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64ADDL
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = nil
|
2015-04-15 15:51:25 -07:00
|
|
|
v.resetArgs()
|
2015-03-23 17:02:11 -07:00
|
|
|
v.AddArg(x)
|
|
|
|
|
v.AddArg(y)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-04-15 15:51:25 -07:00
|
|
|
goto end35a02a1587264e40cf1055856ff8445a
|
|
|
|
|
end35a02a1587264e40cf1055856ff8445a:
|
2015-03-23 17:02:11 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case OpAMD64CMPQ:
|
2015-05-18 16:44:20 -07:00
|
|
|
// match: (CMPQ x (MOVQconst [c]))
|
2015-03-23 17:02:11 -07:00
|
|
|
// cond:
|
2015-05-28 10:47:24 -07:00
|
|
|
// result: (CMPQconst x [c])
|
2015-03-23 17:02:11 -07:00
|
|
|
{
|
|
|
|
|
x := v.Args[0]
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end32ef1328af280ac18fa8045a3502dae9
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
|
|
|
|
c := v.Args[1].Aux
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64CMPQconst
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = nil
|
2015-04-15 15:51:25 -07:00
|
|
|
v.resetArgs()
|
2015-03-23 17:02:11 -07:00
|
|
|
v.AddArg(x)
|
|
|
|
|
v.Aux = c
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end32ef1328af280ac18fa8045a3502dae9
|
|
|
|
|
end32ef1328af280ac18fa8045a3502dae9:
|
2015-03-23 17:02:11 -07:00
|
|
|
;
|
2015-05-18 16:44:20 -07:00
|
|
|
// match: (CMPQ (MOVQconst [c]) x)
|
2015-03-23 17:02:11 -07:00
|
|
|
// cond:
|
2015-05-28 10:47:24 -07:00
|
|
|
// result: (InvertFlags (CMPQconst <TypeFlags> x [c]))
|
2015-03-23 17:02:11 -07:00
|
|
|
{
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto endf8ca12fe79290bc82b11cfa463bc9413
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
|
|
|
|
c := v.Args[0].Aux
|
|
|
|
|
x := v.Args[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64InvertFlags
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = nil
|
2015-04-15 15:51:25 -07:00
|
|
|
v.resetArgs()
|
2015-05-30 01:03:06 -04:00
|
|
|
v0 := v.Block.NewValue(v.Line, OpAMD64CMPQconst, TypeInvalid, nil)
|
2015-03-26 10:49:03 -07:00
|
|
|
v0.Type = TypeFlags
|
2015-03-23 17:02:11 -07:00
|
|
|
v0.AddArg(x)
|
|
|
|
|
v0.Aux = c
|
|
|
|
|
v.AddArg(v0)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto endf8ca12fe79290bc82b11cfa463bc9413
|
|
|
|
|
endf8ca12fe79290bc82b11cfa463bc9413:
|
2015-05-18 16:44:20 -07:00
|
|
|
;
|
|
|
|
|
case OpConst:
|
|
|
|
|
// match: (Const <t> [val])
|
|
|
|
|
// cond: is64BitInt(t)
|
|
|
|
|
// result: (MOVQconst [val])
|
|
|
|
|
{
|
|
|
|
|
t := v.Type
|
|
|
|
|
val := v.Aux
|
|
|
|
|
if !(is64BitInt(t)) {
|
|
|
|
|
goto end7f5c5b34093fbc6860524cb803ee51bf
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64MOVQconst
|
2015-05-18 16:44:20 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.Aux = val
|
|
|
|
|
return true
|
|
|
|
|
}
|
|
|
|
|
goto end7f5c5b34093fbc6860524cb803ee51bf
|
|
|
|
|
end7f5c5b34093fbc6860524cb803ee51bf:
|
|
|
|
|
;
|
|
|
|
|
case OpGlobal:
|
|
|
|
|
// match: (Global [sym])
|
|
|
|
|
// cond:
|
|
|
|
|
// result: (LEAQglobal [GlobalOffset{sym,0}])
|
|
|
|
|
{
|
|
|
|
|
sym := v.Aux
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64LEAQglobal
|
2015-05-18 16:44:20 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.Aux = GlobalOffset{sym, 0}
|
|
|
|
|
return true
|
|
|
|
|
}
|
|
|
|
|
goto end3a3c76fac0e2e53c0e1c60b9524e6f1c
|
|
|
|
|
end3a3c76fac0e2e53c0e1c60b9524e6f1c:
|
2015-04-15 15:51:25 -07:00
|
|
|
;
|
2015-05-13 14:11:39 -07:00
|
|
|
case OpIsInBounds:
|
|
|
|
|
// match: (IsInBounds idx len)
|
2015-04-15 15:51:25 -07:00
|
|
|
// cond:
|
|
|
|
|
// result: (SETB (CMPQ <TypeFlags> idx len))
|
|
|
|
|
{
|
|
|
|
|
idx := v.Args[0]
|
|
|
|
|
len := v.Args[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64SETB
|
2015-04-15 15:51:25 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
2015-05-30 01:03:06 -04:00
|
|
|
v0 := v.Block.NewValue(v.Line, OpAMD64CMPQ, TypeInvalid, nil)
|
2015-04-15 15:51:25 -07:00
|
|
|
v0.Type = TypeFlags
|
|
|
|
|
v0.AddArg(idx)
|
|
|
|
|
v0.AddArg(len)
|
|
|
|
|
v.AddArg(v0)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-13 14:11:39 -07:00
|
|
|
goto endb51d371171154c0f1613b687757e0576
|
|
|
|
|
endb51d371171154c0f1613b687757e0576:
|
2015-04-15 15:51:25 -07:00
|
|
|
;
|
2015-05-13 14:11:39 -07:00
|
|
|
case OpIsNonNil:
|
|
|
|
|
// match: (IsNonNil p)
|
2015-04-15 15:51:25 -07:00
|
|
|
// cond:
|
|
|
|
|
// result: (SETNE (TESTQ <TypeFlags> p p))
|
|
|
|
|
{
|
|
|
|
|
p := v.Args[0]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64SETNE
|
2015-04-15 15:51:25 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
2015-05-30 01:03:06 -04:00
|
|
|
v0 := v.Block.NewValue(v.Line, OpAMD64TESTQ, TypeInvalid, nil)
|
2015-04-15 15:51:25 -07:00
|
|
|
v0.Type = TypeFlags
|
|
|
|
|
v0.AddArg(p)
|
|
|
|
|
v0.AddArg(p)
|
|
|
|
|
v.AddArg(v0)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-13 14:11:39 -07:00
|
|
|
goto endff508c3726edfb573abc6128c177e76c
|
|
|
|
|
endff508c3726edfb573abc6128c177e76c:
|
2015-03-23 17:02:11 -07:00
|
|
|
;
|
|
|
|
|
case OpLess:
|
|
|
|
|
// match: (Less x y)
|
|
|
|
|
// cond: is64BitInt(v.Args[0].Type) && isSigned(v.Args[0].Type)
|
2015-03-26 10:49:03 -07:00
|
|
|
// result: (SETL (CMPQ <TypeFlags> x y))
|
2015-03-23 17:02:11 -07:00
|
|
|
{
|
|
|
|
|
x := v.Args[0]
|
|
|
|
|
y := v.Args[1]
|
|
|
|
|
if !(is64BitInt(v.Args[0].Type) && isSigned(v.Args[0].Type)) {
|
2015-04-15 15:51:25 -07:00
|
|
|
goto endcecf13a952d4c6c2383561c7d68a3cf9
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64SETL
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = nil
|
2015-04-15 15:51:25 -07:00
|
|
|
v.resetArgs()
|
2015-05-30 01:03:06 -04:00
|
|
|
v0 := v.Block.NewValue(v.Line, OpAMD64CMPQ, TypeInvalid, nil)
|
2015-03-26 10:49:03 -07:00
|
|
|
v0.Type = TypeFlags
|
2015-03-23 17:02:11 -07:00
|
|
|
v0.AddArg(x)
|
|
|
|
|
v0.AddArg(y)
|
|
|
|
|
v.AddArg(v0)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-04-15 15:51:25 -07:00
|
|
|
goto endcecf13a952d4c6c2383561c7d68a3cf9
|
|
|
|
|
endcecf13a952d4c6c2383561c7d68a3cf9:
|
2015-03-23 17:02:11 -07:00
|
|
|
;
|
2015-04-15 15:51:25 -07:00
|
|
|
case OpLoad:
|
|
|
|
|
// match: (Load <t> ptr mem)
|
2015-05-18 16:44:20 -07:00
|
|
|
// cond: t.IsBoolean()
|
|
|
|
|
// result: (MOVBload [int64(0)] ptr mem)
|
2015-03-23 17:02:11 -07:00
|
|
|
{
|
|
|
|
|
t := v.Type
|
2015-04-15 15:51:25 -07:00
|
|
|
ptr := v.Args[0]
|
|
|
|
|
mem := v.Args[1]
|
2015-05-18 16:44:20 -07:00
|
|
|
if !(t.IsBoolean()) {
|
|
|
|
|
goto end73f21632e56c3614902d3c29c82dc4ea
|
2015-04-15 15:51:25 -07:00
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64MOVBload
|
2015-04-15 15:51:25 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.Aux = int64(0)
|
|
|
|
|
v.AddArg(ptr)
|
|
|
|
|
v.AddArg(mem)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-18 16:44:20 -07:00
|
|
|
goto end73f21632e56c3614902d3c29c82dc4ea
|
|
|
|
|
end73f21632e56c3614902d3c29c82dc4ea:
|
2015-03-23 17:02:11 -07:00
|
|
|
;
|
2015-05-18 16:44:20 -07:00
|
|
|
// match: (Load <t> ptr mem)
|
|
|
|
|
// cond: (is64BitInt(t) || isPtr(t))
|
|
|
|
|
// result: (MOVQload [int64(0)] ptr mem)
|
2015-03-23 17:02:11 -07:00
|
|
|
{
|
2015-05-18 16:44:20 -07:00
|
|
|
t := v.Type
|
|
|
|
|
ptr := v.Args[0]
|
2015-04-15 15:51:25 -07:00
|
|
|
mem := v.Args[1]
|
2015-05-18 16:44:20 -07:00
|
|
|
if !(is64BitInt(t) || isPtr(t)) {
|
|
|
|
|
goto end581ce5a20901df1b8143448ba031685b
|
2015-05-12 15:16:52 -07:00
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64MOVQload
|
2015-05-12 15:16:52 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
2015-05-18 16:44:20 -07:00
|
|
|
v.Aux = int64(0)
|
|
|
|
|
v.AddArg(ptr)
|
2015-05-12 15:16:52 -07:00
|
|
|
v.AddArg(mem)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-18 16:44:20 -07:00
|
|
|
goto end581ce5a20901df1b8143448ba031685b
|
|
|
|
|
end581ce5a20901df1b8143448ba031685b:
|
2015-04-15 15:51:25 -07:00
|
|
|
;
|
2015-05-28 10:47:24 -07:00
|
|
|
case OpLsh:
|
|
|
|
|
// match: (Lsh <t> x y)
|
|
|
|
|
// cond: is64BitInt(t)
|
|
|
|
|
// result: (SHLQ x y)
|
|
|
|
|
{
|
|
|
|
|
t := v.Type
|
|
|
|
|
x := v.Args[0]
|
|
|
|
|
y := v.Args[1]
|
|
|
|
|
if !(is64BitInt(t)) {
|
|
|
|
|
goto end9f05c9539e51db6ad557989e0c822e9b
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64SHLQ
|
2015-05-28 10:47:24 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.AddArg(x)
|
|
|
|
|
v.AddArg(y)
|
|
|
|
|
return true
|
|
|
|
|
}
|
|
|
|
|
goto end9f05c9539e51db6ad557989e0c822e9b
|
|
|
|
|
end9f05c9539e51db6ad557989e0c822e9b:
|
|
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case OpAMD64MOVQload:
|
2015-05-28 10:47:24 -07:00
|
|
|
// match: (MOVQload [off1] (ADDQconst [off2] ptr) mem)
|
2015-04-15 15:51:25 -07:00
|
|
|
// cond:
|
2015-05-18 16:44:20 -07:00
|
|
|
// result: (MOVQload [addOff(off1, off2)] ptr mem)
|
2015-04-15 15:51:25 -07:00
|
|
|
{
|
|
|
|
|
off1 := v.Aux
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[0].Op != OpAMD64ADDQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end843d29b538c4483b432b632e5666d6e3
|
2015-04-15 15:51:25 -07:00
|
|
|
}
|
|
|
|
|
off2 := v.Args[0].Aux
|
|
|
|
|
ptr := v.Args[0].Args[0]
|
|
|
|
|
mem := v.Args[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64MOVQload
|
2015-04-15 15:51:25 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
2015-05-18 16:44:20 -07:00
|
|
|
v.Aux = addOff(off1, off2)
|
2015-04-15 15:51:25 -07:00
|
|
|
v.AddArg(ptr)
|
|
|
|
|
v.AddArg(mem)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end843d29b538c4483b432b632e5666d6e3
|
|
|
|
|
end843d29b538c4483b432b632e5666d6e3:
|
2015-04-15 15:51:25 -07:00
|
|
|
;
|
|
|
|
|
// match: (MOVQload [off1] (LEAQ8 [off2] ptr idx) mem)
|
|
|
|
|
// cond:
|
2015-05-18 16:44:20 -07:00
|
|
|
// result: (MOVQloadidx8 [addOff(off1, off2)] ptr idx mem)
|
2015-04-15 15:51:25 -07:00
|
|
|
{
|
|
|
|
|
off1 := v.Aux
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[0].Op != OpAMD64LEAQ8 {
|
2015-05-18 16:44:20 -07:00
|
|
|
goto end02f5ad148292c46463e7c20d3b821735
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
2015-04-15 15:51:25 -07:00
|
|
|
off2 := v.Args[0].Aux
|
|
|
|
|
ptr := v.Args[0].Args[0]
|
|
|
|
|
idx := v.Args[0].Args[1]
|
|
|
|
|
mem := v.Args[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64MOVQloadidx8
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = nil
|
2015-04-15 15:51:25 -07:00
|
|
|
v.resetArgs()
|
2015-05-18 16:44:20 -07:00
|
|
|
v.Aux = addOff(off1, off2)
|
2015-04-15 15:51:25 -07:00
|
|
|
v.AddArg(ptr)
|
|
|
|
|
v.AddArg(idx)
|
2015-03-23 17:02:11 -07:00
|
|
|
v.AddArg(mem)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-18 16:44:20 -07:00
|
|
|
goto end02f5ad148292c46463e7c20d3b821735
|
|
|
|
|
end02f5ad148292c46463e7c20d3b821735:
|
2015-04-15 15:51:25 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case OpAMD64MOVQloadidx8:
|
2015-05-28 10:47:24 -07:00
|
|
|
// match: (MOVQloadidx8 [off1] (ADDQconst [off2] ptr) idx mem)
|
2015-04-15 15:51:25 -07:00
|
|
|
// cond:
|
2015-05-18 16:44:20 -07:00
|
|
|
// result: (MOVQloadidx8 [addOff(off1, off2)] ptr idx mem)
|
2015-04-15 15:51:25 -07:00
|
|
|
{
|
|
|
|
|
off1 := v.Aux
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[0].Op != OpAMD64ADDQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto ende81e44bcfb11f90916ccb440c590121f
|
2015-04-15 15:51:25 -07:00
|
|
|
}
|
|
|
|
|
off2 := v.Args[0].Aux
|
2015-05-18 16:44:20 -07:00
|
|
|
ptr := v.Args[0].Args[0]
|
|
|
|
|
idx := v.Args[1]
|
2015-04-15 15:51:25 -07:00
|
|
|
mem := v.Args[2]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64MOVQloadidx8
|
2015-04-15 15:51:25 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
2015-05-18 16:44:20 -07:00
|
|
|
v.Aux = addOff(off1, off2)
|
|
|
|
|
v.AddArg(ptr)
|
|
|
|
|
v.AddArg(idx)
|
2015-04-15 15:51:25 -07:00
|
|
|
v.AddArg(mem)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto ende81e44bcfb11f90916ccb440c590121f
|
|
|
|
|
ende81e44bcfb11f90916ccb440c590121f:
|
2015-04-15 15:51:25 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case OpAMD64MOVQstore:
|
2015-05-28 10:47:24 -07:00
|
|
|
// match: (MOVQstore [off1] (ADDQconst [off2] ptr) val mem)
|
2015-04-15 15:51:25 -07:00
|
|
|
// cond:
|
2015-05-18 16:44:20 -07:00
|
|
|
// result: (MOVQstore [addOff(off1, off2)] ptr val mem)
|
2015-04-15 15:51:25 -07:00
|
|
|
{
|
|
|
|
|
off1 := v.Aux
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[0].Op != OpAMD64ADDQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end2108c693a43c79aed10b9246c39c80aa
|
2015-04-15 15:51:25 -07:00
|
|
|
}
|
|
|
|
|
off2 := v.Args[0].Aux
|
2015-05-18 16:44:20 -07:00
|
|
|
ptr := v.Args[0].Args[0]
|
2015-04-15 15:51:25 -07:00
|
|
|
val := v.Args[1]
|
|
|
|
|
mem := v.Args[2]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64MOVQstore
|
2015-05-12 15:16:52 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
2015-05-18 16:44:20 -07:00
|
|
|
v.Aux = addOff(off1, off2)
|
|
|
|
|
v.AddArg(ptr)
|
2015-05-12 15:16:52 -07:00
|
|
|
v.AddArg(val)
|
|
|
|
|
v.AddArg(mem)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end2108c693a43c79aed10b9246c39c80aa
|
|
|
|
|
end2108c693a43c79aed10b9246c39c80aa:
|
2015-04-15 15:51:25 -07:00
|
|
|
;
|
2015-05-18 16:44:20 -07:00
|
|
|
// match: (MOVQstore [off1] (LEAQ8 [off2] ptr idx) val mem)
|
2015-04-15 15:51:25 -07:00
|
|
|
// cond:
|
2015-05-18 16:44:20 -07:00
|
|
|
// result: (MOVQstoreidx8 [addOff(off1, off2)] ptr idx val mem)
|
2015-04-15 15:51:25 -07:00
|
|
|
{
|
|
|
|
|
off1 := v.Aux
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[0].Op != OpAMD64LEAQ8 {
|
2015-05-18 16:44:20 -07:00
|
|
|
goto endce1db8c8d37c8397c500a2068a65c215
|
2015-04-15 15:51:25 -07:00
|
|
|
}
|
|
|
|
|
off2 := v.Args[0].Aux
|
|
|
|
|
ptr := v.Args[0].Args[0]
|
2015-05-18 16:44:20 -07:00
|
|
|
idx := v.Args[0].Args[1]
|
2015-04-15 15:51:25 -07:00
|
|
|
val := v.Args[1]
|
|
|
|
|
mem := v.Args[2]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64MOVQstoreidx8
|
2015-04-15 15:51:25 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
2015-05-18 16:44:20 -07:00
|
|
|
v.Aux = addOff(off1, off2)
|
2015-04-15 15:51:25 -07:00
|
|
|
v.AddArg(ptr)
|
2015-05-18 16:44:20 -07:00
|
|
|
v.AddArg(idx)
|
2015-04-15 15:51:25 -07:00
|
|
|
v.AddArg(val)
|
|
|
|
|
v.AddArg(mem)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-18 16:44:20 -07:00
|
|
|
goto endce1db8c8d37c8397c500a2068a65c215
|
|
|
|
|
endce1db8c8d37c8397c500a2068a65c215:
|
2015-04-15 15:51:25 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case OpAMD64MOVQstoreidx8:
|
2015-05-28 10:47:24 -07:00
|
|
|
// match: (MOVQstoreidx8 [off1] (ADDQconst [off2] ptr) idx val mem)
|
2015-04-15 15:51:25 -07:00
|
|
|
// cond:
|
2015-05-18 16:44:20 -07:00
|
|
|
// result: (MOVQstoreidx8 [addOff(off1, off2)] ptr idx val mem)
|
2015-04-15 15:51:25 -07:00
|
|
|
{
|
|
|
|
|
off1 := v.Aux
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[0].Op != OpAMD64ADDQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end01c970657b0fdefeab82458c15022163
|
2015-04-15 15:51:25 -07:00
|
|
|
}
|
|
|
|
|
off2 := v.Args[0].Aux
|
|
|
|
|
ptr := v.Args[0].Args[0]
|
2015-05-18 16:44:20 -07:00
|
|
|
idx := v.Args[1]
|
|
|
|
|
val := v.Args[2]
|
|
|
|
|
mem := v.Args[3]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64MOVQstoreidx8
|
2015-04-15 15:51:25 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
2015-05-18 16:44:20 -07:00
|
|
|
v.Aux = addOff(off1, off2)
|
2015-04-15 15:51:25 -07:00
|
|
|
v.AddArg(ptr)
|
|
|
|
|
v.AddArg(idx)
|
|
|
|
|
v.AddArg(val)
|
|
|
|
|
v.AddArg(mem)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end01c970657b0fdefeab82458c15022163
|
|
|
|
|
end01c970657b0fdefeab82458c15022163:
|
2015-04-15 15:51:25 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case OpAMD64MULQ:
|
2015-05-18 16:44:20 -07:00
|
|
|
// match: (MULQ x (MOVQconst [c]))
|
2015-05-28 10:47:24 -07:00
|
|
|
// cond: c.(int64) == int64(int32(c.(int64)))
|
|
|
|
|
// result: (MULQconst [c] x)
|
2015-04-15 15:51:25 -07:00
|
|
|
{
|
|
|
|
|
x := v.Args[0]
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto ende8c09b194fcde7d9cdc69f2deff86304
|
2015-04-15 15:51:25 -07:00
|
|
|
}
|
|
|
|
|
c := v.Args[1].Aux
|
2015-05-28 10:47:24 -07:00
|
|
|
if !(c.(int64) == int64(int32(c.(int64)))) {
|
|
|
|
|
goto ende8c09b194fcde7d9cdc69f2deff86304
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64MULQconst
|
2015-04-15 15:51:25 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.Aux = c
|
|
|
|
|
v.AddArg(x)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto ende8c09b194fcde7d9cdc69f2deff86304
|
|
|
|
|
ende8c09b194fcde7d9cdc69f2deff86304:
|
2015-04-15 15:51:25 -07:00
|
|
|
;
|
2015-05-18 16:44:20 -07:00
|
|
|
// match: (MULQ (MOVQconst [c]) x)
|
2015-04-15 15:51:25 -07:00
|
|
|
// cond:
|
2015-05-28 10:47:24 -07:00
|
|
|
// result: (MULQconst [c] x)
|
2015-04-15 15:51:25 -07:00
|
|
|
{
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto endc6e18d6968175d6e58eafa6dcf40c1b8
|
2015-04-15 15:51:25 -07:00
|
|
|
}
|
|
|
|
|
c := v.Args[0].Aux
|
|
|
|
|
x := v.Args[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64MULQconst
|
2015-04-15 15:51:25 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.Aux = c
|
|
|
|
|
v.AddArg(x)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto endc6e18d6968175d6e58eafa6dcf40c1b8
|
|
|
|
|
endc6e18d6968175d6e58eafa6dcf40c1b8:
|
|
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case OpAMD64MULQconst:
|
2015-05-28 10:47:24 -07:00
|
|
|
// match: (MULQconst [c] x)
|
|
|
|
|
// cond: c.(int64) == 8
|
|
|
|
|
// result: (SHLQconst [int64(3)] x)
|
|
|
|
|
{
|
|
|
|
|
c := v.Aux
|
|
|
|
|
x := v.Args[0]
|
|
|
|
|
if !(c.(int64) == 8) {
|
|
|
|
|
goto end7e16978c56138324ff2abf91fd6d94d4
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64SHLQconst
|
2015-05-28 10:47:24 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.Aux = int64(3)
|
|
|
|
|
v.AddArg(x)
|
|
|
|
|
return true
|
|
|
|
|
}
|
|
|
|
|
goto end7e16978c56138324ff2abf91fd6d94d4
|
|
|
|
|
end7e16978c56138324ff2abf91fd6d94d4:
|
|
|
|
|
;
|
|
|
|
|
// match: (MULQconst [c] x)
|
|
|
|
|
// cond: c.(int64) == 64
|
|
|
|
|
// result: (SHLQconst [int64(5)] x)
|
|
|
|
|
{
|
|
|
|
|
c := v.Aux
|
|
|
|
|
x := v.Args[0]
|
|
|
|
|
if !(c.(int64) == 64) {
|
|
|
|
|
goto end2c7a02f230e4b311ac3a4e22f70a4f08
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64SHLQconst
|
2015-05-28 10:47:24 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.Aux = int64(5)
|
|
|
|
|
v.AddArg(x)
|
|
|
|
|
return true
|
|
|
|
|
}
|
|
|
|
|
goto end2c7a02f230e4b311ac3a4e22f70a4f08
|
|
|
|
|
end2c7a02f230e4b311ac3a4e22f70a4f08:
|
2015-05-18 16:44:20 -07:00
|
|
|
;
|
|
|
|
|
case OpMove:
|
|
|
|
|
// match: (Move [size] dst src mem)
|
|
|
|
|
// cond:
|
|
|
|
|
// result: (REPMOVSB dst src (Const <TypeUInt64> [size.(int64)]) mem)
|
|
|
|
|
{
|
|
|
|
|
size := v.Aux
|
|
|
|
|
dst := v.Args[0]
|
|
|
|
|
src := v.Args[1]
|
|
|
|
|
mem := v.Args[2]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64REPMOVSB
|
2015-05-18 16:44:20 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.AddArg(dst)
|
|
|
|
|
v.AddArg(src)
|
2015-05-30 01:03:06 -04:00
|
|
|
v0 := v.Block.NewValue(v.Line, OpConst, TypeInvalid, nil)
|
2015-05-18 16:44:20 -07:00
|
|
|
v0.Type = TypeUInt64
|
|
|
|
|
v0.Aux = size.(int64)
|
|
|
|
|
v.AddArg(v0)
|
|
|
|
|
v.AddArg(mem)
|
|
|
|
|
return true
|
|
|
|
|
}
|
|
|
|
|
goto end48909259b265a6bb2a076bc2c2dc7d1f
|
|
|
|
|
end48909259b265a6bb2a076bc2c2dc7d1f:
|
2015-04-15 15:51:25 -07:00
|
|
|
;
|
|
|
|
|
case OpMul:
|
|
|
|
|
// match: (Mul <t> x y)
|
|
|
|
|
// cond: is64BitInt(t)
|
|
|
|
|
// result: (MULQ x y)
|
|
|
|
|
{
|
|
|
|
|
t := v.Type
|
|
|
|
|
x := v.Args[0]
|
|
|
|
|
y := v.Args[1]
|
|
|
|
|
if !(is64BitInt(t)) {
|
|
|
|
|
goto endfab0d598f376ecba45a22587d50f7aff
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64MULQ
|
2015-04-15 15:51:25 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.AddArg(x)
|
|
|
|
|
v.AddArg(y)
|
|
|
|
|
return true
|
|
|
|
|
}
|
|
|
|
|
goto endfab0d598f376ecba45a22587d50f7aff
|
|
|
|
|
endfab0d598f376ecba45a22587d50f7aff:
|
2015-03-23 17:02:11 -07:00
|
|
|
;
|
2015-05-18 16:44:20 -07:00
|
|
|
case OpOffPtr:
|
|
|
|
|
// match: (OffPtr [off] ptr)
|
|
|
|
|
// cond:
|
2015-05-28 10:47:24 -07:00
|
|
|
// result: (ADDQconst [off] ptr)
|
2015-05-18 16:44:20 -07:00
|
|
|
{
|
|
|
|
|
off := v.Aux
|
|
|
|
|
ptr := v.Args[0]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64ADDQconst
|
2015-05-18 16:44:20 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.Aux = off
|
|
|
|
|
v.AddArg(ptr)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end0429f947ee7ac49ff45a243e461a5290
|
|
|
|
|
end0429f947ee7ac49ff45a243e461a5290:
|
2015-05-18 16:44:20 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case OpAMD64SETG:
|
2015-05-28 16:45:33 -07:00
|
|
|
// match: (SETG (InvertFlags x))
|
|
|
|
|
// cond:
|
|
|
|
|
// result: (SETL x)
|
|
|
|
|
{
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
2015-05-28 16:45:33 -07:00
|
|
|
goto endf7586738694c9cd0b74ae28bbadb649f
|
|
|
|
|
}
|
|
|
|
|
x := v.Args[0].Args[0]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64SETL
|
2015-05-28 16:45:33 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.AddArg(x)
|
|
|
|
|
return true
|
|
|
|
|
}
|
|
|
|
|
goto endf7586738694c9cd0b74ae28bbadb649f
|
|
|
|
|
endf7586738694c9cd0b74ae28bbadb649f:
|
|
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case OpAMD64SETL:
|
2015-03-23 17:02:11 -07:00
|
|
|
// match: (SETL (InvertFlags x))
|
|
|
|
|
// cond:
|
2015-05-28 16:45:33 -07:00
|
|
|
// result: (SETG x)
|
2015-03-23 17:02:11 -07:00
|
|
|
{
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[0].Op != OpAMD64InvertFlags {
|
2015-05-28 16:45:33 -07:00
|
|
|
goto ende33160cd86b9d4d3b77e02fb4658d5d3
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
|
|
|
|
x := v.Args[0].Args[0]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64SETG
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = nil
|
2015-04-15 15:51:25 -07:00
|
|
|
v.resetArgs()
|
2015-03-23 17:02:11 -07:00
|
|
|
v.AddArg(x)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 16:45:33 -07:00
|
|
|
goto ende33160cd86b9d4d3b77e02fb4658d5d3
|
|
|
|
|
ende33160cd86b9d4d3b77e02fb4658d5d3:
|
2015-03-23 17:02:11 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case OpAMD64SHLQ:
|
2015-05-28 10:47:24 -07:00
|
|
|
// match: (SHLQ x (MOVQconst [c]))
|
|
|
|
|
// cond:
|
|
|
|
|
// result: (SHLQconst [c] x)
|
|
|
|
|
{
|
|
|
|
|
x := v.Args[0]
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto endcca412bead06dc3d56ef034a82d184d6
|
|
|
|
|
}
|
|
|
|
|
c := v.Args[1].Aux
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64SHLQconst
|
2015-05-28 10:47:24 -07:00
|
|
|
v.Aux = nil
|
|
|
|
|
v.resetArgs()
|
|
|
|
|
v.Aux = c
|
|
|
|
|
v.AddArg(x)
|
|
|
|
|
return true
|
|
|
|
|
}
|
|
|
|
|
goto endcca412bead06dc3d56ef034a82d184d6
|
|
|
|
|
endcca412bead06dc3d56ef034a82d184d6:
|
|
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case OpAMD64SUBQ:
|
2015-05-18 16:44:20 -07:00
|
|
|
// match: (SUBQ x (MOVQconst [c]))
|
2015-03-23 17:02:11 -07:00
|
|
|
// cond:
|
2015-05-28 10:47:24 -07:00
|
|
|
// result: (SUBQconst x [c])
|
2015-03-23 17:02:11 -07:00
|
|
|
{
|
|
|
|
|
x := v.Args[0]
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[1].Op != OpAMD64MOVQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end5a74a63bd9ad15437717c6df3b25eebb
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
|
|
|
|
c := v.Args[1].Aux
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64SUBQconst
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = nil
|
2015-04-15 15:51:25 -07:00
|
|
|
v.resetArgs()
|
2015-03-23 17:02:11 -07:00
|
|
|
v.AddArg(x)
|
|
|
|
|
v.Aux = c
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end5a74a63bd9ad15437717c6df3b25eebb
|
|
|
|
|
end5a74a63bd9ad15437717c6df3b25eebb:
|
2015-03-23 17:02:11 -07:00
|
|
|
;
|
2015-05-18 16:44:20 -07:00
|
|
|
// match: (SUBQ <t> (MOVQconst [c]) x)
|
2015-03-23 17:02:11 -07:00
|
|
|
// cond:
|
2015-05-28 10:47:24 -07:00
|
|
|
// result: (NEGQ (SUBQconst <t> x [c]))
|
2015-03-23 17:02:11 -07:00
|
|
|
{
|
2015-03-26 10:49:03 -07:00
|
|
|
t := v.Type
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Args[0].Op != OpAMD64MOVQconst {
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end78e66b6fc298684ff4ac8aec5ce873c9
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
|
|
|
|
c := v.Args[0].Aux
|
|
|
|
|
x := v.Args[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64NEGQ
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = nil
|
2015-04-15 15:51:25 -07:00
|
|
|
v.resetArgs()
|
2015-05-30 01:03:06 -04:00
|
|
|
v0 := v.Block.NewValue(v.Line, OpAMD64SUBQconst, TypeInvalid, nil)
|
2015-03-26 10:49:03 -07:00
|
|
|
v0.Type = t
|
2015-03-23 17:02:11 -07:00
|
|
|
v0.AddArg(x)
|
|
|
|
|
v0.Aux = c
|
|
|
|
|
v.AddArg(v0)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-05-28 10:47:24 -07:00
|
|
|
goto end78e66b6fc298684ff4ac8aec5ce873c9
|
|
|
|
|
end78e66b6fc298684ff4ac8aec5ce873c9:
|
2015-03-23 17:02:11 -07:00
|
|
|
;
|
2015-04-15 15:51:25 -07:00
|
|
|
case OpStore:
|
|
|
|
|
// match: (Store ptr val mem)
|
|
|
|
|
// cond: (is64BitInt(val.Type) || isPtr(val.Type))
|
|
|
|
|
// result: (MOVQstore [int64(0)] ptr val mem)
|
2015-03-23 17:02:11 -07:00
|
|
|
{
|
2015-04-15 15:51:25 -07:00
|
|
|
ptr := v.Args[0]
|
|
|
|
|
val := v.Args[1]
|
|
|
|
|
mem := v.Args[2]
|
|
|
|
|
if !(is64BitInt(val.Type) || isPtr(val.Type)) {
|
|
|
|
|
goto end9680b43f504bc06f9fab000823ce471a
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64MOVQstore
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = nil
|
2015-04-15 15:51:25 -07:00
|
|
|
v.resetArgs()
|
|
|
|
|
v.Aux = int64(0)
|
|
|
|
|
v.AddArg(ptr)
|
2015-03-23 17:02:11 -07:00
|
|
|
v.AddArg(val)
|
|
|
|
|
v.AddArg(mem)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-04-15 15:51:25 -07:00
|
|
|
goto end9680b43f504bc06f9fab000823ce471a
|
|
|
|
|
end9680b43f504bc06f9fab000823ce471a:
|
2015-03-23 17:02:11 -07:00
|
|
|
;
|
|
|
|
|
case OpSub:
|
|
|
|
|
// match: (Sub <t> x y)
|
|
|
|
|
// cond: is64BitInt(t)
|
|
|
|
|
// result: (SUBQ x y)
|
|
|
|
|
{
|
|
|
|
|
t := v.Type
|
|
|
|
|
x := v.Args[0]
|
|
|
|
|
y := v.Args[1]
|
|
|
|
|
if !(is64BitInt(t)) {
|
2015-04-15 15:51:25 -07:00
|
|
|
goto ende6ef29f885a8ecf3058212bb95917323
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
v.Op = OpAMD64SUBQ
|
2015-03-23 17:02:11 -07:00
|
|
|
v.Aux = nil
|
2015-04-15 15:51:25 -07:00
|
|
|
v.resetArgs()
|
2015-03-23 17:02:11 -07:00
|
|
|
v.AddArg(x)
|
|
|
|
|
v.AddArg(y)
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-04-15 15:51:25 -07:00
|
|
|
goto ende6ef29f885a8ecf3058212bb95917323
|
|
|
|
|
ende6ef29f885a8ecf3058212bb95917323:
|
2015-03-23 17:02:11 -07:00
|
|
|
}
|
|
|
|
|
return false
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
func rewriteBlockAMD64(b *Block) bool {
|
2015-05-28 16:45:33 -07:00
|
|
|
switch b.Kind {
|
2015-06-06 16:03:33 -07:00
|
|
|
case BlockAMD64EQ:
|
|
|
|
|
// match: (EQ (InvertFlags cmp) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
// cond:
|
2015-06-06 16:03:33 -07:00
|
|
|
// result: (EQ cmp yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Op != OpAMD64InvertFlags {
|
|
|
|
|
goto end6b8e9afc73b1c4d528f31a60d2575fae
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
cmp := v.Args[0]
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64EQ
|
2015-05-28 16:45:33 -07:00
|
|
|
b.Control = cmp
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto end6b8e9afc73b1c4d528f31a60d2575fae
|
|
|
|
|
end6b8e9afc73b1c4d528f31a60d2575fae:
|
2015-05-28 16:45:33 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case BlockAMD64GE:
|
|
|
|
|
// match: (GE (InvertFlags cmp) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
// cond:
|
2015-06-06 16:03:33 -07:00
|
|
|
// result: (LE cmp yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Op != OpAMD64InvertFlags {
|
|
|
|
|
goto end0610f000a6988ee8310307ec2ea138f8
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
cmp := v.Args[0]
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64LE
|
2015-05-28 16:45:33 -07:00
|
|
|
b.Control = cmp
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto end0610f000a6988ee8310307ec2ea138f8
|
|
|
|
|
end0610f000a6988ee8310307ec2ea138f8:
|
2015-05-28 16:45:33 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case BlockAMD64GT:
|
|
|
|
|
// match: (GT (InvertFlags cmp) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
// cond:
|
2015-06-06 16:03:33 -07:00
|
|
|
// result: (LT cmp yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Op != OpAMD64InvertFlags {
|
|
|
|
|
goto endf60c0660b6a8aa9565c97fc87f04eb34
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
cmp := v.Args[0]
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64LT
|
2015-05-28 16:45:33 -07:00
|
|
|
b.Control = cmp
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto endf60c0660b6a8aa9565c97fc87f04eb34
|
|
|
|
|
endf60c0660b6a8aa9565c97fc87f04eb34:
|
2015-05-28 16:45:33 -07:00
|
|
|
;
|
|
|
|
|
case BlockIf:
|
2015-06-06 16:03:33 -07:00
|
|
|
// match: (If (SETL cmp) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
// cond:
|
2015-06-06 16:03:33 -07:00
|
|
|
// result: (LT cmp yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Op != OpAMD64SETL {
|
|
|
|
|
goto ende4d36879bb8e1bd8facaa8c91ba99dcc
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
cmp := v.Args[0]
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64LT
|
2015-05-28 16:45:33 -07:00
|
|
|
b.Control = cmp
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto ende4d36879bb8e1bd8facaa8c91ba99dcc
|
|
|
|
|
ende4d36879bb8e1bd8facaa8c91ba99dcc:
|
2015-05-28 16:45:33 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
// match: (If (SETNE cmp) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
// cond:
|
2015-06-06 16:03:33 -07:00
|
|
|
// result: (NE cmp yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Op != OpAMD64SETNE {
|
|
|
|
|
goto end5ff1403aaf7b543bc454177ab584e4f5
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
cmp := v.Args[0]
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64NE
|
2015-05-28 16:45:33 -07:00
|
|
|
b.Control = cmp
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto end5ff1403aaf7b543bc454177ab584e4f5
|
|
|
|
|
end5ff1403aaf7b543bc454177ab584e4f5:
|
2015-05-28 16:45:33 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
// match: (If (SETB cmp) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
// cond:
|
2015-06-06 16:03:33 -07:00
|
|
|
// result: (ULT cmp yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Op != OpAMD64SETB {
|
|
|
|
|
goto end04935012db9defeafceef8175f803ea2
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
cmp := v.Args[0]
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64ULT
|
2015-05-28 16:45:33 -07:00
|
|
|
b.Control = cmp
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto end04935012db9defeafceef8175f803ea2
|
|
|
|
|
end04935012db9defeafceef8175f803ea2:
|
2015-05-28 16:45:33 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
// match: (If cond yes no)
|
|
|
|
|
// cond: cond.Op == OpAMD64MOVBload
|
|
|
|
|
// result: (NE (TESTB <TypeFlags> cond cond) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
|
|
|
|
cond := v
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
if !(cond.Op == OpAMD64MOVBload) {
|
|
|
|
|
goto end7e22019fb0effc80f85c05ea30bdb5d9
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64NE
|
2015-05-30 01:03:06 -04:00
|
|
|
v0 := v.Block.NewValue(v.Line, OpAMD64TESTB, TypeInvalid, nil)
|
2015-05-28 16:45:33 -07:00
|
|
|
v0.Type = TypeFlags
|
|
|
|
|
v0.AddArg(cond)
|
|
|
|
|
v0.AddArg(cond)
|
|
|
|
|
b.Control = v0
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto end7e22019fb0effc80f85c05ea30bdb5d9
|
|
|
|
|
end7e22019fb0effc80f85c05ea30bdb5d9:
|
2015-05-28 16:45:33 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case BlockAMD64LE:
|
|
|
|
|
// match: (LE (InvertFlags cmp) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
// cond:
|
2015-06-06 16:03:33 -07:00
|
|
|
// result: (GE cmp yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Op != OpAMD64InvertFlags {
|
|
|
|
|
goto end0d49d7d087fe7578e8015cf13dae37e3
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
cmp := v.Args[0]
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64GE
|
2015-05-28 16:45:33 -07:00
|
|
|
b.Control = cmp
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto end0d49d7d087fe7578e8015cf13dae37e3
|
|
|
|
|
end0d49d7d087fe7578e8015cf13dae37e3:
|
2015-05-28 16:45:33 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case BlockAMD64LT:
|
|
|
|
|
// match: (LT (InvertFlags cmp) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
// cond:
|
2015-06-06 16:03:33 -07:00
|
|
|
// result: (GT cmp yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Op != OpAMD64InvertFlags {
|
|
|
|
|
goto end6a408cde0fee0ae7b7da0443c8d902bf
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
cmp := v.Args[0]
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64GT
|
2015-05-28 16:45:33 -07:00
|
|
|
b.Control = cmp
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto end6a408cde0fee0ae7b7da0443c8d902bf
|
|
|
|
|
end6a408cde0fee0ae7b7da0443c8d902bf:
|
2015-05-28 16:45:33 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case BlockAMD64NE:
|
|
|
|
|
// match: (NE (InvertFlags cmp) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
// cond:
|
2015-06-06 16:03:33 -07:00
|
|
|
// result: (NE cmp yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Op != OpAMD64InvertFlags {
|
|
|
|
|
goto end713001aba794e50b582fbff930e110af
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
cmp := v.Args[0]
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64NE
|
2015-05-28 16:45:33 -07:00
|
|
|
b.Control = cmp
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto end713001aba794e50b582fbff930e110af
|
|
|
|
|
end713001aba794e50b582fbff930e110af:
|
2015-05-28 16:45:33 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case BlockAMD64UGE:
|
|
|
|
|
// match: (UGE (InvertFlags cmp) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
// cond:
|
2015-06-06 16:03:33 -07:00
|
|
|
// result: (ULE cmp yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Op != OpAMD64InvertFlags {
|
|
|
|
|
goto ende3e4ddc183ca1a46598b11c2d0d13966
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
cmp := v.Args[0]
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64ULE
|
2015-05-28 16:45:33 -07:00
|
|
|
b.Control = cmp
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto ende3e4ddc183ca1a46598b11c2d0d13966
|
|
|
|
|
ende3e4ddc183ca1a46598b11c2d0d13966:
|
2015-05-28 16:45:33 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case BlockAMD64UGT:
|
|
|
|
|
// match: (UGT (InvertFlags cmp) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
// cond:
|
2015-06-06 16:03:33 -07:00
|
|
|
// result: (ULT cmp yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Op != OpAMD64InvertFlags {
|
|
|
|
|
goto end49818853af2e5251175d06c62768cae7
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
cmp := v.Args[0]
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64ULT
|
2015-05-28 16:45:33 -07:00
|
|
|
b.Control = cmp
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto end49818853af2e5251175d06c62768cae7
|
|
|
|
|
end49818853af2e5251175d06c62768cae7:
|
2015-05-28 16:45:33 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case BlockAMD64ULE:
|
|
|
|
|
// match: (ULE (InvertFlags cmp) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
// cond:
|
2015-06-06 16:03:33 -07:00
|
|
|
// result: (UGE cmp yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Op != OpAMD64InvertFlags {
|
|
|
|
|
goto endd6698aac0d67261293b558c95ea17b4f
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
cmp := v.Args[0]
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64UGE
|
2015-05-28 16:45:33 -07:00
|
|
|
b.Control = cmp
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto endd6698aac0d67261293b558c95ea17b4f
|
|
|
|
|
endd6698aac0d67261293b558c95ea17b4f:
|
2015-05-28 16:45:33 -07:00
|
|
|
;
|
2015-06-06 16:03:33 -07:00
|
|
|
case BlockAMD64ULT:
|
|
|
|
|
// match: (ULT (InvertFlags cmp) yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
// cond:
|
2015-06-06 16:03:33 -07:00
|
|
|
// result: (UGT cmp yes no)
|
2015-05-28 16:45:33 -07:00
|
|
|
{
|
|
|
|
|
v := b.Control
|
2015-06-06 16:03:33 -07:00
|
|
|
if v.Op != OpAMD64InvertFlags {
|
|
|
|
|
goto end35105dbc9646f02577167e45ae2f2fd2
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
cmp := v.Args[0]
|
|
|
|
|
yes := b.Succs[0]
|
|
|
|
|
no := b.Succs[1]
|
2015-06-06 16:03:33 -07:00
|
|
|
b.Kind = BlockAMD64UGT
|
2015-05-28 16:45:33 -07:00
|
|
|
b.Control = cmp
|
|
|
|
|
b.Succs[0] = yes
|
|
|
|
|
b.Succs[1] = no
|
|
|
|
|
return true
|
|
|
|
|
}
|
2015-06-06 16:03:33 -07:00
|
|
|
goto end35105dbc9646f02577167e45ae2f2fd2
|
|
|
|
|
end35105dbc9646f02577167e45ae2f2fd2:
|
2015-05-28 16:45:33 -07:00
|
|
|
}
|
|
|
|
|
return false
|
|
|
|
|
}
|