2015-06-06 16:03:33 -07:00
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// autogenerated: do not edit!
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// generated from gen/*Ops.go
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2016-03-01 10:58:06 -08:00
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2015-06-06 16:03:33 -07:00
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package ssa
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2015-06-16 11:11:16 -07:00
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import "cmd/internal/obj/x86"
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2015-06-06 16:03:33 -07:00
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const (
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2015-08-18 14:39:26 -04:00
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BlockInvalid BlockKind = iota
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2015-06-06 16:03:33 -07:00
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BlockAMD64EQ
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BlockAMD64NE
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BlockAMD64LT
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BlockAMD64LE
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BlockAMD64GT
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BlockAMD64GE
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BlockAMD64ULT
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BlockAMD64ULE
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BlockAMD64UGT
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BlockAMD64UGE
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2015-08-18 14:39:26 -04:00
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BlockAMD64EQF
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BlockAMD64NEF
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BlockAMD64ORD
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BlockAMD64NAN
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2015-06-06 16:03:33 -07:00
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BlockPlain
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BlockIf
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BlockCall
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2015-10-23 19:12:49 -07:00
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BlockCheck
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2015-09-03 09:09:59 -07:00
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BlockRet
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2015-09-08 21:28:44 -07:00
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BlockRetJmp
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2015-09-09 18:03:41 -07:00
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BlockExit
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BlockFirst
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BlockDead
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2015-06-06 16:03:33 -07:00
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)
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var blockString = [...]string{
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BlockInvalid: "BlockInvalid",
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BlockAMD64EQ: "EQ",
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BlockAMD64NE: "NE",
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BlockAMD64LT: "LT",
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BlockAMD64LE: "LE",
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BlockAMD64GT: "GT",
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BlockAMD64GE: "GE",
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BlockAMD64ULT: "ULT",
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BlockAMD64ULE: "ULE",
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BlockAMD64UGT: "UGT",
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BlockAMD64UGE: "UGE",
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BlockAMD64EQF: "EQF",
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BlockAMD64NEF: "NEF",
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BlockAMD64ORD: "ORD",
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BlockAMD64NAN: "NAN",
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2015-09-08 21:28:44 -07:00
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BlockPlain: "Plain",
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BlockIf: "If",
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BlockCall: "Call",
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BlockCheck: "Check",
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BlockRet: "Ret",
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BlockRetJmp: "RetJmp",
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2015-09-09 18:03:41 -07:00
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BlockExit: "Exit",
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BlockFirst: "First",
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BlockDead: "Dead",
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}
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func (k BlockKind) String() string { return blockString[k] }
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const (
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OpInvalid Op = iota
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2015-08-12 16:38:11 -04:00
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OpAMD64ADDSS
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OpAMD64ADDSD
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OpAMD64SUBSS
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OpAMD64SUBSD
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OpAMD64MULSS
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OpAMD64MULSD
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OpAMD64DIVSS
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OpAMD64DIVSD
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OpAMD64MOVSSload
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OpAMD64MOVSDload
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OpAMD64MOVSSconst
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OpAMD64MOVSDconst
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OpAMD64MOVSSloadidx4
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OpAMD64MOVSDloadidx8
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OpAMD64MOVSSstore
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OpAMD64MOVSDstore
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OpAMD64MOVSSstoreidx4
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OpAMD64MOVSDstoreidx8
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2015-07-28 16:04:50 -07:00
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OpAMD64ADDQ
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OpAMD64ADDL
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OpAMD64ADDW
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OpAMD64ADDB
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OpAMD64ADDQconst
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OpAMD64ADDLconst
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OpAMD64ADDWconst
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OpAMD64ADDBconst
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OpAMD64SUBQ
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OpAMD64SUBL
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OpAMD64SUBW
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OpAMD64SUBB
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OpAMD64SUBQconst
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OpAMD64SUBLconst
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OpAMD64SUBWconst
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OpAMD64SUBBconst
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2015-06-06 16:03:33 -07:00
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OpAMD64MULQ
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2015-07-28 16:04:50 -07:00
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OpAMD64MULL
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OpAMD64MULW
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2015-08-14 13:23:11 +02:00
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OpAMD64MULB
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2015-06-06 16:03:33 -07:00
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OpAMD64MULQconst
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2015-07-28 16:04:50 -07:00
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OpAMD64MULLconst
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OpAMD64MULWconst
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2015-08-14 13:23:11 +02:00
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OpAMD64MULBconst
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2016-02-05 20:26:18 -08:00
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OpAMD64HMULQ
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2015-08-18 19:14:47 -05:00
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OpAMD64HMULL
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OpAMD64HMULW
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OpAMD64HMULB
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2016-02-05 20:26:18 -08:00
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OpAMD64HMULQU
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2015-08-18 19:14:47 -05:00
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OpAMD64HMULLU
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OpAMD64HMULWU
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OpAMD64HMULBU
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2016-02-05 20:26:18 -08:00
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OpAMD64AVGQU
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2015-08-17 17:46:06 -05:00
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OpAMD64DIVQ
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OpAMD64DIVL
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OpAMD64DIVW
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OpAMD64DIVQU
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OpAMD64DIVLU
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OpAMD64DIVWU
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2015-08-18 19:51:44 -05:00
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OpAMD64MODQ
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OpAMD64MODL
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OpAMD64MODW
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OpAMD64MODQU
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OpAMD64MODLU
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OpAMD64MODWU
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2015-07-28 16:04:50 -07:00
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OpAMD64ANDQ
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OpAMD64ANDL
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OpAMD64ANDW
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OpAMD64ANDB
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OpAMD64ANDQconst
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OpAMD64ANDLconst
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OpAMD64ANDWconst
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OpAMD64ANDBconst
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OpAMD64ORQ
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OpAMD64ORL
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OpAMD64ORW
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OpAMD64ORB
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OpAMD64ORQconst
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OpAMD64ORLconst
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OpAMD64ORWconst
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OpAMD64ORBconst
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OpAMD64XORQ
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OpAMD64XORL
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OpAMD64XORW
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OpAMD64XORB
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2015-07-10 11:25:48 -06:00
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OpAMD64XORQconst
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2015-07-28 16:04:50 -07:00
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OpAMD64XORLconst
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OpAMD64XORWconst
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OpAMD64XORBconst
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2015-06-06 16:03:33 -07:00
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OpAMD64CMPQ
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2015-07-21 18:06:15 +02:00
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OpAMD64CMPL
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OpAMD64CMPW
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OpAMD64CMPB
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2015-07-28 16:04:50 -07:00
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OpAMD64CMPQconst
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OpAMD64CMPLconst
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OpAMD64CMPWconst
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OpAMD64CMPBconst
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2015-08-18 14:39:26 -04:00
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OpAMD64UCOMISS
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OpAMD64UCOMISD
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OpAMD64TESTQ
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2015-07-28 16:04:50 -07:00
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OpAMD64TESTL
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OpAMD64TESTW
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2015-06-06 16:03:33 -07:00
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OpAMD64TESTB
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2015-07-28 16:04:50 -07:00
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OpAMD64TESTQconst
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OpAMD64TESTLconst
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OpAMD64TESTWconst
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OpAMD64TESTBconst
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OpAMD64SHLQ
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OpAMD64SHLL
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OpAMD64SHLW
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OpAMD64SHLB
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OpAMD64SHLQconst
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OpAMD64SHLLconst
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OpAMD64SHLWconst
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OpAMD64SHLBconst
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OpAMD64SHRQ
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OpAMD64SHRL
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OpAMD64SHRW
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OpAMD64SHRB
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OpAMD64SHRQconst
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OpAMD64SHRLconst
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OpAMD64SHRWconst
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OpAMD64SHRBconst
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OpAMD64SARQ
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OpAMD64SARL
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OpAMD64SARW
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OpAMD64SARB
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OpAMD64SARQconst
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OpAMD64SARLconst
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OpAMD64SARWconst
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OpAMD64SARBconst
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2015-08-05 22:11:14 -04:00
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OpAMD64ROLQconst
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OpAMD64ROLLconst
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OpAMD64ROLWconst
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OpAMD64ROLBconst
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2015-07-28 16:04:50 -07:00
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OpAMD64NEGQ
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OpAMD64NEGL
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OpAMD64NEGW
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OpAMD64NEGB
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2015-07-29 17:07:09 -07:00
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OpAMD64NOTQ
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OpAMD64NOTL
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OpAMD64NOTW
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OpAMD64NOTB
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2015-09-12 13:26:57 -07:00
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OpAMD64SQRTSD
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2015-06-10 10:39:57 -07:00
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OpAMD64SBBQcarrymask
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2015-07-29 17:07:09 -07:00
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OpAMD64SBBLcarrymask
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2015-06-06 16:03:33 -07:00
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OpAMD64SETEQ
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OpAMD64SETNE
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OpAMD64SETL
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2015-06-24 17:48:22 -07:00
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OpAMD64SETLE
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2015-06-06 16:03:33 -07:00
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OpAMD64SETG
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OpAMD64SETGE
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OpAMD64SETB
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2015-07-24 12:47:00 -07:00
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OpAMD64SETBE
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OpAMD64SETA
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OpAMD64SETAE
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2015-08-18 14:39:26 -04:00
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OpAMD64SETEQF
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OpAMD64SETNEF
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OpAMD64SETORD
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OpAMD64SETNAN
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OpAMD64SETGF
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OpAMD64SETGEF
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2015-06-14 11:38:46 -07:00
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OpAMD64MOVBQSX
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2015-07-22 13:46:15 -07:00
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OpAMD64MOVBQZX
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OpAMD64MOVWQSX
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OpAMD64MOVWQZX
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OpAMD64MOVLQSX
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OpAMD64MOVLQZX
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2015-07-28 14:19:20 -07:00
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OpAMD64MOVBconst
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OpAMD64MOVWconst
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OpAMD64MOVLconst
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2015-06-06 16:03:33 -07:00
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OpAMD64MOVQconst
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2015-09-01 19:05:44 -05:00
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OpAMD64CVTTSD2SL
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OpAMD64CVTTSD2SQ
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OpAMD64CVTTSS2SL
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OpAMD64CVTTSS2SQ
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2015-08-20 15:14:20 -04:00
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OpAMD64CVTSL2SS
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OpAMD64CVTSL2SD
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OpAMD64CVTSQ2SS
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OpAMD64CVTSQ2SD
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OpAMD64CVTSD2SS
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OpAMD64CVTSS2SD
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2015-08-28 14:24:10 -04:00
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OpAMD64PXOR
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2015-06-06 16:03:33 -07:00
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OpAMD64LEAQ
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2015-06-19 21:02:28 -07:00
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OpAMD64LEAQ1
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2015-06-06 16:03:33 -07:00
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OpAMD64LEAQ2
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OpAMD64LEAQ4
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OpAMD64LEAQ8
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OpAMD64MOVBload
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OpAMD64MOVBQSXload
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[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
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OpAMD64MOVBQZXload
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2015-06-14 11:38:46 -07:00
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OpAMD64MOVWload
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2016-01-30 11:25:38 -08:00
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OpAMD64MOVWQSXload
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OpAMD64MOVWQZXload
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2015-06-14 11:38:46 -07:00
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OpAMD64MOVLload
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2016-01-30 11:25:38 -08:00
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OpAMD64MOVLQSXload
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OpAMD64MOVLQZXload
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2015-06-06 16:03:33 -07:00
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OpAMD64MOVQload
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OpAMD64MOVBstore
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2015-06-14 11:38:46 -07:00
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OpAMD64MOVWstore
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OpAMD64MOVLstore
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2015-06-06 16:03:33 -07:00
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OpAMD64MOVQstore
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2016-02-02 11:13:50 -08:00
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OpAMD64MOVOload
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OpAMD64MOVOstore
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OpAMD64MOVBloadidx1
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OpAMD64MOVWloadidx2
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OpAMD64MOVLloadidx4
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OpAMD64MOVQloadidx8
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2016-01-30 11:25:38 -08:00
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OpAMD64MOVBstoreidx1
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OpAMD64MOVWstoreidx2
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OpAMD64MOVLstoreidx4
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2015-06-06 16:03:33 -07:00
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OpAMD64MOVQstoreidx8
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2015-10-21 13:13:56 -07:00
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OpAMD64MOVBstoreconst
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OpAMD64MOVWstoreconst
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OpAMD64MOVLstoreconst
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OpAMD64MOVQstoreconst
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2016-02-04 15:53:33 -08:00
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OpAMD64MOVBstoreconstidx1
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OpAMD64MOVWstoreconstidx2
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OpAMD64MOVLstoreconstidx4
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OpAMD64MOVQstoreconstidx8
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2015-09-18 18:23:34 -07:00
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OpAMD64DUFFZERO
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2015-10-19 13:56:55 -07:00
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OpAMD64MOVOconst
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2015-06-27 15:45:20 +01:00
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OpAMD64REPSTOSQ
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2015-06-10 15:03:06 -07:00
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OpAMD64CALLstatic
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OpAMD64CALLclosure
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2015-08-28 22:51:01 -07:00
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OpAMD64CALLdefer
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OpAMD64CALLgo
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2015-09-09 23:56:59 -07:00
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OpAMD64CALLinter
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2015-10-21 17:18:07 -07:00
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OpAMD64DUFFCOPY
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OpAMD64REPMOVSQ
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2015-06-06 16:03:33 -07:00
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OpAMD64InvertFlags
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2015-08-12 11:22:16 -07:00
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OpAMD64LoweredGetG
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2015-09-11 16:40:05 -04:00
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OpAMD64LoweredGetClosurePtr
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2015-10-23 19:12:49 -07:00
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OpAMD64LoweredNilCheck
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2015-11-10 15:35:36 -08:00
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OpAMD64MOVQconvert
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2016-01-05 14:56:26 -08:00
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OpAMD64FlagEQ
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OpAMD64FlagLT_ULT
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OpAMD64FlagLT_UGT
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OpAMD64FlagGT_UGT
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OpAMD64FlagGT_ULT
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2015-06-06 16:03:33 -07:00
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2015-07-19 15:48:20 -07:00
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OpAdd8
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OpAdd64F
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2015-07-19 15:48:20 -07:00
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2015-08-24 23:52:03 -07:00
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OpSubPtr
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OpSub32F
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2015-07-22 13:46:15 -07:00
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2015-08-12 16:38:11 -04:00
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2015-08-18 19:14:47 -05:00
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2016-02-05 20:26:18 -08:00
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OpAvg64u
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2015-08-17 17:46:06 -05:00
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OpDiv8
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2015-08-18 19:51:44 -05:00
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2015-07-28 14:58:49 +02:00
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OpAnd8
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OpAnd64
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2015-07-29 17:52:25 +02:00
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2015-07-28 16:04:50 -07:00
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2015-07-29 17:07:09 -07:00
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OpLsh32x64
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OpRsh8x8
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OpRsh64Ux64
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2015-08-05 22:11:14 -04:00
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OpLrot8
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OpLrot16
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OpLrot32
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OpLrot64
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2015-07-19 15:48:20 -07:00
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OpEq8
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OpEq16
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OpEq32
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OpEq64
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2015-07-27 13:17:45 -07:00
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OpEqPtr
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2015-09-10 13:53:27 -07:00
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OpEqInter
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OpEqSlice
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2015-08-18 14:39:26 -04:00
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OpEq32F
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OpEq64F
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2015-07-19 15:48:20 -07:00
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OpNeq8
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OpNeq16
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OpNeq32
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OpNeq64
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2015-07-27 13:17:45 -07:00
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OpNeqPtr
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2015-09-10 13:53:27 -07:00
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OpNeqInter
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OpNeqSlice
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2015-08-18 14:39:26 -04:00
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OpNeq32F
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OpNeq64F
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2015-07-19 15:48:20 -07:00
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OpLess8
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OpLess8U
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OpLess16
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OpLess32
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OpLess64
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OpLess64U
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2015-08-18 14:39:26 -04:00
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OpLess32F
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OpLess64F
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2015-07-19 15:48:20 -07:00
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OpLeq8
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OpLeq16
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OpLeq32
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OpLeq32U
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OpLeq64
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OpLeq64U
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2015-08-18 14:39:26 -04:00
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OpLeq32F
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OpLeq64F
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2015-07-19 15:48:20 -07:00
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OpGreater8
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OpGreater8U
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OpGreater16
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OpGreater32
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OpGreater64
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OpGreater64U
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2015-08-18 14:39:26 -04:00
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OpGreater32F
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OpGreater64F
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2015-07-19 15:48:20 -07:00
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OpGeq8
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OpGeq32
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OpGeq64
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OpGeq64U
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2015-08-18 14:39:26 -04:00
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OpGeq32F
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OpGeq64F
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2015-07-10 11:25:48 -06:00
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OpNot
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2015-07-21 16:58:18 +02:00
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OpNeg8
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OpNeg16
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OpNeg32
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OpNeg64
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2015-08-28 14:24:10 -04:00
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OpNeg32F
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OpNeg64F
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2015-07-29 17:07:09 -07:00
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OpCom8
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OpCom16
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OpCom64
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2015-09-12 13:26:57 -07:00
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OpSqrt
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2015-06-06 16:03:33 -07:00
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OpPhi
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OpCopy
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2015-10-19 11:36:07 -04:00
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OpConvert
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2015-07-28 14:19:20 -07:00
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2015-08-12 16:38:11 -04:00
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OpConst64F
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2015-08-18 10:26:28 -07:00
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OpConstInterface
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OpConstSlice
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2015-11-02 08:10:26 -08:00
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OpInitMem
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2015-06-06 16:03:33 -07:00
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OpArg
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2015-06-19 21:02:28 -07:00
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OpAddr
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2015-06-06 16:03:33 -07:00
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OpSP
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2015-06-19 21:02:28 -07:00
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OpSB
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2015-06-06 16:03:33 -07:00
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OpFunc
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OpLoad
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OpStore
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OpMove
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2015-06-27 15:45:20 +01:00
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OpZero
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2015-06-10 15:03:06 -07:00
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OpClosureCall
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2015-06-06 16:03:33 -07:00
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OpStaticCall
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2015-08-28 22:51:01 -07:00
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OpDeferCall
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OpGoCall
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2015-09-09 23:56:59 -07:00
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OpInterCall
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
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OpSignExt8to16
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OpSignExt8to64
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OpSignExt16to64
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OpSignExt32to64
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OpZeroExt8to16
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OpZeroExt8to64
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OpZeroExt32to64
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OpTrunc16to8
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OpTrunc32to8
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OpTrunc32to16
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OpTrunc64to8
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OpTrunc64to16
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OpTrunc64to32
|
2015-08-20 15:14:20 -04:00
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OpCvt32to32F
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OpCvt32to64F
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OpCvt64to32F
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OpCvt64to64F
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OpCvt32Fto32
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OpCvt32Fto64
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OpCvt64Fto32
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OpCvt64Fto64
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OpCvt32Fto64F
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OpCvt64Fto32F
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2015-06-06 16:03:33 -07:00
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OpIsNonNil
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OpIsInBounds
|
2015-08-24 23:52:03 -07:00
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OpIsSliceInBounds
|
2015-10-23 19:12:49 -07:00
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OpNilCheck
|
2015-08-12 11:22:16 -07:00
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OpGetG
|
2015-09-11 16:40:05 -04:00
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OpGetClosurePtr
|
2015-06-06 16:03:33 -07:00
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OpArrayIndex
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OpPtrIndex
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OpOffPtr
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OpSliceMake
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OpSlicePtr
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OpSliceLen
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OpSliceCap
|
2015-08-28 14:24:10 -04:00
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OpComplexMake
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OpComplexReal
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OpComplexImag
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2015-06-06 16:03:33 -07:00
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OpStringMake
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OpStringPtr
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OpStringLen
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2015-08-18 10:26:28 -07:00
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OpIMake
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2015-08-04 15:47:22 -07:00
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OpITab
|
2015-08-18 10:26:28 -07:00
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OpIData
|
2016-01-11 21:05:33 -08:00
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OpStructMake0
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OpStructMake1
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OpStructMake2
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OpStructMake3
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OpStructMake4
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OpStructSelect
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2015-07-24 14:51:51 -07:00
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OpStoreReg
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OpLoadReg
|
2015-06-06 16:03:33 -07:00
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OpFwdRef
|
2016-01-14 16:02:23 -08:00
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OpUnknown
|
2015-08-24 02:16:19 -07:00
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OpVarDef
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OpVarKill
|
2016-01-19 09:59:21 -08:00
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OpVarLive
|
2015-06-06 16:03:33 -07:00
|
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)
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|
var opcodeTable = [...]opInfo{
|
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{name: "OpInvalid"},
|
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2015-08-12 16:38:11 -04:00
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{
|
2016-02-27 08:04:48 -06:00
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|
name: "ADDSS",
|
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|
argLen: 2,
|
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asm: x86.AADDSS,
|
2015-08-12 16:38:11 -04:00
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reg: regInfo{
|
2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
|
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|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
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|
{1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "ADDSD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AADDSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
{1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SUBSS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ASUBSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
|
|
|
|
|
{1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
clobbers: 2147483648, // .X15
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SUBSD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ASUBSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
|
|
|
|
|
{1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
clobbers: 2147483648, // .X15
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MULSS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
{1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MULSD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
{1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVSS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
|
|
|
|
|
{1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
clobbers: 2147483648, // .X15
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVSD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
|
|
|
|
|
{1, 2147418112}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
clobbers: 2147483648, // .X15
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
2147418112, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSconst",
|
|
|
|
|
auxType: auxFloat,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDconst",
|
|
|
|
|
auxType: auxFloat,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSloadidx4",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDloadidx8",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSstoreidx4",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{2, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDstoreidx8",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{2, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "ADDQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AADDQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "ADDL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AADDL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "ADDW",
|
|
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AADDL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "ADDB",
|
|
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AADDL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ADDQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AADDQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ADDLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AADDL,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ADDWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AADDL,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ADDBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AADDL,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-10 11:25:48 -06:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SUBQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ASUBQ,
|
2015-07-10 11:25:48 -06:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-10 11:25:48 -06:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-10 11:25:48 -06:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SUBL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ASUBL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-07-28 16:04:50 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SUBW",
|
|
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.ASUBL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-07-28 16:04:50 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 18:06:15 +02:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SUBB",
|
|
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.ASUBL,
|
2015-07-21 18:06:15 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-21 18:06:15 +02:00
|
|
|
outputs: []regMask{
|
2015-07-28 16:04:50 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SUBQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ASUBQ,
|
2015-07-21 18:06:15 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-21 18:06:15 +02:00
|
|
|
outputs: []regMask{
|
2015-07-28 16:04:50 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SUBLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ASUBL,
|
2015-07-21 18:06:15 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-21 18:06:15 +02:00
|
|
|
outputs: []regMask{
|
2015-07-28 16:04:50 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SUBWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.ASUBL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-07-28 16:04:50 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SUBBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.ASUBL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-07-28 16:04:50 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MULQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MULL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MULW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULW,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-14 13:23:11 +02:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MULB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULW,
|
2015-08-14 13:23:11 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-08-14 13:23:11 +02:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-08-14 13:23:11 +02:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MULQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AIMULQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-24 17:48:22 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MULLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AIMULL,
|
2015-06-24 17:48:22 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-24 17:48:22 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-24 17:48:22 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MULWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AIMULW,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-14 13:23:11 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MULBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AIMULW,
|
2015-08-14 13:23:11 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-08-14 13:23:11 +02:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-08-14 13:23:11 +02:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-05 20:26:18 -08:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULQ,
|
2016-02-05 20:26:18 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 19:14:47 -05:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULL,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULW,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULB,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-05 20:26:18 -08:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULQU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULQ,
|
2016-02-05 20:26:18 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 19:14:47 -05:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULLU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULL,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULWU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULW,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULBU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULB,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-05 20:26:18 -08:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "AVGQU",
|
|
|
|
|
argLen: 2,
|
2016-02-05 20:26:18 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-17 17:46:06 -05:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVQ,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934596, // .DX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1, // .AX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVL,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934596, // .DX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1, // .AX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVW,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934596, // .DX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1, // .AX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVQU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVQ,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934596, // .DX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1, // .AX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVLU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVL,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934596, // .DX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1, // .AX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVWU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVW,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934596, // .DX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1, // .AX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 19:51:44 -05:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVQ,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVL,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVW,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODQU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVQ,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODLU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVL,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODWU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVW,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1}, // .AX
|
|
|
|
|
{1, 65531}, // .AX .CX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "ANDQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AANDQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "ANDL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AANDL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-24 12:47:00 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "ANDW",
|
|
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AANDL,
|
2015-07-24 12:47:00 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-24 12:47:00 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-24 12:47:00 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "ANDB",
|
|
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AANDL,
|
2015-07-24 12:47:00 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-24 12:47:00 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-24 12:47:00 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ANDQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AANDQ,
|
2015-07-24 12:47:00 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-24 12:47:00 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-24 12:47:00 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ANDLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AANDL,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-14 11:38:46 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ANDWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AANDL,
|
2015-07-22 13:46:15 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-22 13:46:15 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ANDBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AANDL,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-14 11:38:46 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "ORQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AORQ,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-14 11:38:46 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "ORL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AORL,
|
2015-07-22 13:46:15 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-22 13:46:15 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "ORW",
|
|
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AORL,
|
2015-07-22 13:46:15 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-22 13:46:15 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "ORB",
|
|
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AORL,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-14 11:38:46 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 14:19:20 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ORQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AORQ,
|
2015-07-28 14:19:20 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ORLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ORWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ORBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "XORQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AXORQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "XORL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "XORW",
|
|
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "XORB",
|
|
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "XORQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AXORQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "XORLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "XORWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "XORBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CMPQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ACMPQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CMPL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ACMPL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CMPW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ACMPW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CMPB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ACMPB,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CMPQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ACMPQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CMPLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ACMPL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CMPWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ACMPW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CMPBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ACMPB,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "UCOMISS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AUCOMISS,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
{1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "UCOMISD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AUCOMISD,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
{1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "TESTQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ATESTQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "TESTL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ATESTL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "TESTW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ATESTW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "TESTB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ATESTB,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "TESTQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
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asm: x86.ATESTQ,
|
2015-07-28 16:04:50 -07:00
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reg: regInfo{
|
2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
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},
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outputs: []regMask{
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8589934592, // .FLAGS
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},
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},
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|
},
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|
{
|
2016-01-31 11:39:39 -08:00
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|
name: "TESTLconst",
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|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
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argLen: 1,
|
2016-01-31 11:39:39 -08:00
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asm: x86.ATESTL,
|
2015-07-28 16:04:50 -07:00
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reg: regInfo{
|
2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
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|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
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},
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outputs: []regMask{
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8589934592, // .FLAGS
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},
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},
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},
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{
|
2016-01-31 11:39:39 -08:00
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|
|
name: "TESTWconst",
|
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|
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|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
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argLen: 1,
|
2016-01-31 11:39:39 -08:00
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asm: x86.ATESTW,
|
2015-07-28 16:04:50 -07:00
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reg: regInfo{
|
2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
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},
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outputs: []regMask{
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8589934592, // .FLAGS
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},
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},
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},
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{
|
2016-01-31 11:39:39 -08:00
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|
name: "TESTBconst",
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|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
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argLen: 1,
|
2016-01-31 11:39:39 -08:00
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asm: x86.ATESTB,
|
2015-07-28 16:04:50 -07:00
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reg: regInfo{
|
2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
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|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
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},
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outputs: []regMask{
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8589934592, // .FLAGS
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},
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},
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},
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{
|
2016-02-27 08:04:48 -06:00
|
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|
name: "SHLQ",
|
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|
argLen: 2,
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|
asm: x86.ASHLQ,
|
2015-07-28 16:04:50 -07:00
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reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 2}, // .CX
|
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|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
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},
|
2015-08-11 12:51:33 -07:00
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|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2015-08-07 12:19:03 +02:00
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|
|
65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
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},
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},
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{
|
2016-02-27 08:04:48 -06:00
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|
|
name: "SHLL",
|
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|
argLen: 2,
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asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
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|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 2}, // .CX
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2015-08-07 12:19:03 +02:00
|
|
|
65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SHLW",
|
|
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 2}, // .CX
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2015-08-07 12:19:03 +02:00
|
|
|
65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SHLB",
|
|
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 2}, // .CX
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2015-08-07 12:19:03 +02:00
|
|
|
65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SHLQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ASHLQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SHLLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SHLWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SHLBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SHRQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ASHRQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 2}, // .CX
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2015-08-07 12:19:03 +02:00
|
|
|
65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 14:19:20 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SHRL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ASHRL,
|
2015-07-28 14:19:20 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 2}, // .CX
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 14:19:20 -07:00
|
|
|
outputs: []regMask{
|
2015-08-07 12:19:03 +02:00
|
|
|
65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 14:19:20 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SHRW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ASHRW,
|
2015-07-28 14:19:20 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 2}, // .CX
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-28 14:19:20 -07:00
|
|
|
outputs: []regMask{
|
2015-08-07 12:19:03 +02:00
|
|
|
65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 14:19:20 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SHRB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ASHRB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 2}, // .CX
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-08-07 12:19:03 +02:00
|
|
|
65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SHRQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ASHRQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SHRLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ASHRL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SHRWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ASHRW,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SHRBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ASHRB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SARQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ASARQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 2}, // .CX
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-19 21:02:28 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-08-07 12:19:03 +02:00
|
|
|
65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SARL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ASARL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 2}, // .CX
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-08-07 12:19:03 +02:00
|
|
|
65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SARW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ASARW,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 2}, // .CX
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-08-07 12:19:03 +02:00
|
|
|
65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SARB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ASARB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 2}, // .CX
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-08-07 12:19:03 +02:00
|
|
|
65517, // .AX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-14 11:38:46 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SARQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ASARQ,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-14 11:38:46 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SARLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ASARL,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-14 11:38:46 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SARWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ASARW,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "SARBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ASARB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-05 22:11:14 -04:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ROLQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AROLQ,
|
2015-08-05 22:11:14 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-08-05 22:11:14 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ROLLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AROLL,
|
2015-08-05 22:11:14 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-08-05 22:11:14 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ROLWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AROLW,
|
2015-08-05 22:11:14 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-08-05 22:11:14 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "ROLBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AROLB,
|
2015-08-05 22:11:14 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-08-05 22:11:14 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "NEGQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ANEGQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
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},
|
2015-08-11 12:51:33 -07:00
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clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
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outputs: []regMask{
|
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|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
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},
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},
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},
|
2015-06-14 11:38:46 -07:00
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{
|
2016-02-27 08:04:48 -06:00
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|
name: "NEGL",
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argLen: 1,
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asm: x86.ANEGL,
|
2015-06-14 11:38:46 -07:00
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reg: regInfo{
|
2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
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|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
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},
|
2015-08-11 12:51:33 -07:00
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clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
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outputs: []regMask{
|
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|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-14 11:38:46 -07:00
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},
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},
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{
|
2016-02-27 08:04:48 -06:00
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|
name: "NEGW",
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argLen: 1,
|
2016-02-15 17:01:26 +03:00
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asm: x86.ANEGL,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
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|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
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},
|
2015-08-11 12:51:33 -07:00
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clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-14 11:38:46 -07:00
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},
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},
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},
|
2015-06-06 16:03:33 -07:00
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{
|
2016-02-27 08:04:48 -06:00
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|
|
name: "NEGB",
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|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
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asm: x86.ANEGL,
|
2015-06-06 16:03:33 -07:00
|
|
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reg: regInfo{
|
2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-28 16:04:50 -07:00
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},
|
2015-08-11 12:51:33 -07:00
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clobbers: 8589934592, // .FLAGS
|
2015-07-28 16:04:50 -07:00
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outputs: []regMask{
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|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
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|
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},
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},
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},
|
2015-07-29 17:07:09 -07:00
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{
|
2016-02-27 08:04:48 -06:00
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|
|
name: "NOTQ",
|
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|
argLen: 1,
|
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asm: x86.ANOTQ,
|
2015-07-29 17:07:09 -07:00
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|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
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|
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|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-29 17:07:09 -07:00
|
|
|
outputs: []regMask{
|
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|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "NOTL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ANOTL,
|
2015-07-29 17:07:09 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
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|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-29 17:07:09 -07:00
|
|
|
outputs: []regMask{
|
|
|
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|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
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|
|
},
|
|
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},
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|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "NOTW",
|
|
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.ANOTL,
|
2015-07-29 17:07:09 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-29 17:07:09 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "NOTB",
|
|
|
|
|
argLen: 1,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.ANOTL,
|
2015-07-29 17:07:09 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
2015-08-24 23:52:03 -07:00
|
|
|
clobbers: 8589934592, // .FLAGS
|
2015-07-29 17:07:09 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-09-12 13:26:57 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SQRTSD",
|
|
|
|
|
argLen: 1,
|
|
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|
asm: x86.ASQRTSD,
|
2015-09-12 13:26:57 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
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|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SBBQcarrymask",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASBBQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:07:09 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SBBLcarrymask",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASBBL,
|
2015-07-29 17:07:09 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-27 15:45:20 +01:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETEQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETEQ,
|
2015-06-27 15:45:20 +01:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-27 15:45:20 +01:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETNE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETNE,
|
2015-06-27 15:45:20 +01:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-27 15:45:20 +01:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETLT,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETLE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETLE,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
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|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-06-10 15:03:06 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETG",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETGT,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 15:03:06 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETGE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETGE,
|
2015-06-10 15:03:06 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 15:03:06 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETB",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETCS,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETBE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETLS,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETA",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETHI,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETAE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETCC,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETEQF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETEQ,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
|
|
|
|
},
|
2015-09-01 15:18:01 -07:00
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETNEF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETNE,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
|
|
|
|
},
|
2015-09-01 15:18:01 -07:00
|
|
|
clobbers: 8589934593, // .AX .FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETORD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETPC,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETNAN",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETPS,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETGF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETHI,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETGEF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETCC,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589934592}, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVBQSX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVBQSX,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVBQZX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVBQZX,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVWQSX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVWQSX,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVWQZX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVWQZX,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVLQSX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVLQSX,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVLQZX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVLQZX,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVB,
|
2015-07-19 15:48:20 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVW,
|
2015-07-19 15:48:20 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVL,
|
2015-07-19 15:48:20 -07:00
|
|
|
reg: regInfo{
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-07-19 15:48:20 -07:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-20 15:14:20 -04:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTTSD2SL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTTSD2SL,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTTSD2SQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTTSD2SQ,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTTSS2SL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTTSS2SL,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTTSS2SQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTTSS2SQ,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSL2SS",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSL2SS,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSL2SD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSL2SD,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSQ2SS",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSQ2SS,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSQ2SD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSQ2SD,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSD2SS",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSD2SS,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSS2SD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSS2SD,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-28 14:24:10 -04:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "PXOR",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.APXOR,
|
2015-08-28 14:24:10 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
{1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ1",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ2",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ4",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-22 13:46:15 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ8",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-22 13:46:15 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AMOVBLZX,
|
2015-07-22 13:46:15 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBQSXload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVBQSX,
|
2015-07-28 14:58:49 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBQZXload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-03-04 10:26:57 -08:00
|
|
|
asm: x86.AMOVBLZX,
|
2015-07-28 14:58:49 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AMOVWLZX,
|
2015-07-28 14:58:49 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWQSXload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVWQSX,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWQZXload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-03-04 10:26:57 -08:00
|
|
|
asm: x86.AMOVWLZX,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVL,
|
2015-07-28 14:58:49 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLQSXload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVLQSX,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLQZXload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-03-04 10:26:57 -08:00
|
|
|
asm: x86.AMOVL,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVQload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVQ,
|
2015-07-28 14:58:49 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:52:25 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVB,
|
2015-07-29 17:52:25 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVL,
|
2015-07-29 17:52:25 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVQstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVOload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVUPS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVOstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVUPS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 4294901760}, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBloadidx1",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AMOVBLZX,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
2016-02-02 11:13:50 -08:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVWloadidx2",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AMOVWLZX,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
2016-02-02 11:13:50 -08:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVLloadidx4",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVL,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
2016-02-02 11:13:50 -08:00
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:52:25 +02:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVQloadidx8",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVQ,
|
2016-02-02 11:13:50 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBstoreidx1",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVB,
|
2015-07-29 17:52:25 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{2, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-10-21 17:18:07 -07:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVWstoreidx2",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVW,
|
2015-10-21 17:18:07 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-02-02 11:13:50 -08:00
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{2, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-10-21 17:18:07 -07:00
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVLstoreidx4",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{2, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-10-21 17:18:07 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVQstoreidx8",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVQ,
|
2015-10-21 17:18:07 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-02-02 11:13:50 -08:00
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{2, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-10-21 17:18:07 -07:00
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-10-21 13:13:56 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVB,
|
2015-10-21 13:13:56 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVW,
|
2015-10-21 13:13:56 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVL,
|
2015-10-21 13:13:56 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVQstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVQ,
|
2015-10-21 13:13:56 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-04 15:53:33 -08:00
|
|
|
{
|
|
|
|
|
name: "MOVBstoreconstidx1",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-04 15:53:33 -08:00
|
|
|
asm: x86.AMOVB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWstoreconstidx2",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-04 15:53:33 -08:00
|
|
|
asm: x86.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVLstoreconstidx4",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-04 15:53:33 -08:00
|
|
|
asm: x86.AMOVL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVQstoreconstidx8",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-04 15:53:33 -08:00
|
|
|
asm: x86.AMOVQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "DUFFZERO",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2015-10-19 13:56:55 -07:00
|
|
|
{0, 128}, // .DI
|
|
|
|
|
{1, 65536}, // .X0
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-09-18 18:23:34 -07:00
|
|
|
clobbers: 8589934720, // .DI .FLAGS
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
},
|
2015-10-19 13:56:55 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVOconst",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
2015-10-19 13:56:55 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:52:25 +02:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "REPSTOSQ",
|
|
|
|
|
argLen: 4,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 128}, // .DI
|
|
|
|
|
{1, 2}, // .CX
|
2015-09-18 18:23:34 -07:00
|
|
|
{2, 1}, // .AX
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-01 15:59:15 -08:00
|
|
|
clobbers: 130, // .CX .DI
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLstatic",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-11 12:51:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
|
|
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLclosure",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-07-29 17:52:25 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 4}, // .DX
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-08-11 12:51:33 -07:00
|
|
|
clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-08-28 22:51:01 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLdefer",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 22:51:01 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLgo",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 22:51:01 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-09-09 23:56:59 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLinter",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-09-09 23:56:59 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "DUFFCOPY",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-10-21 17:18:07 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 128}, // .DI
|
|
|
|
|
{1, 64}, // .SI
|
|
|
|
|
},
|
2015-12-11 14:59:01 -08:00
|
|
|
clobbers: 8590000320, // .SI .DI .X0 .FLAGS
|
2015-10-21 17:18:07 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "REPMOVSQ",
|
|
|
|
|
argLen: 4,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 128}, // .DI
|
|
|
|
|
{1, 64}, // .SI
|
|
|
|
|
{2, 2}, // .CX
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
clobbers: 194, // .CX .SI .DI
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "InvertFlags",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{},
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-12 11:22:16 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "LoweredGetG",
|
|
|
|
|
argLen: 1,
|
2015-08-13 13:12:17 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-12 11:22:16 -07:00
|
|
|
},
|
2015-09-11 16:40:05 -04:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "LoweredGetClosurePtr",
|
|
|
|
|
argLen: 0,
|
2015-09-11 16:40:05 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4, // .DX
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-10-23 19:12:49 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "LoweredNilCheck",
|
|
|
|
|
argLen: 2,
|
2015-10-23 19:12:49 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // .FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-11-10 15:35:36 -08:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVQconvert",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMOVQ,
|
2015-11-10 15:35:36 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-05 14:56:26 -08:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagEQ",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagLT_ULT",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagLT_UGT",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagGT_UGT",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagGT_ULT",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Add8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Add16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Add32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Add64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "AddPtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
|
|
|
|
name: "Add32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Add64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-24 23:52:03 -07:00
|
|
|
{
|
|
|
|
|
name: "SubPtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-24 23:52:03 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
|
|
|
|
name: "Sub32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Sub64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Mul8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Mul16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Mul32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Mul64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
|
|
|
|
name: "Mul32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mul64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 19:14:47 -05:00
|
|
|
{
|
|
|
|
|
name: "Hmul8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul8u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul16u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul32u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-02-05 20:26:18 -08:00
|
|
|
{
|
|
|
|
|
name: "Hmul64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-05 20:26:18 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul64u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-05 20:26:18 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Avg64u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-05 20:26:18 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-17 17:46:06 -05:00
|
|
|
{
|
|
|
|
|
name: "Div8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div8u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div16u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div32u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div64u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 19:51:44 -05:00
|
|
|
{
|
|
|
|
|
name: "Mod8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod8u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod16u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod32u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod64u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "And8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "And16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "And32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "And64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
2015-07-29 17:52:25 +02:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Or8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Or16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Or32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Or64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Xor8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Xor16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Xor32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Xor64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh8x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh8x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh8x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh8x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh16x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh16x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh16x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh16x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh32x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh32x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh32x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh32x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh64x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh64x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh64x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh64x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh8x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh8x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh8x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh8x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh16x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh16x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh8Ux8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh8Ux16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh8Ux32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh8Ux64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16Ux8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16Ux16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16Ux32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16Ux64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32Ux8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32Ux16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32Ux32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32Ux64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64Ux8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64Ux16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64Ux32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64Ux64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-05 22:11:14 -04:00
|
|
|
{
|
|
|
|
|
name: "Lrot8",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-05 22:11:14 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lrot16",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-05 22:11:14 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lrot32",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
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2015-08-05 22:11:14 -04:00
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2016-01-31 11:39:39 -08:00
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2016-02-27 08:04:48 -06:00
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2015-08-05 22:11:14 -04:00
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2015-07-19 15:48:20 -07:00
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2016-02-22 11:19:15 +01:00
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2016-02-27 08:04:48 -06:00
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2016-02-22 11:19:15 +01:00
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2015-07-19 15:48:20 -07:00
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2016-02-22 11:19:15 +01:00
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2016-02-27 08:04:48 -06:00
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2016-02-22 11:19:15 +01:00
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2015-07-19 15:48:20 -07:00
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2016-02-22 11:19:15 +01:00
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2016-02-27 08:04:48 -06:00
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2016-02-22 11:19:15 +01:00
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2015-07-19 15:48:20 -07:00
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2016-02-22 11:19:15 +01:00
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2016-02-27 08:04:48 -06:00
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2016-02-22 11:19:15 +01:00
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2015-07-19 15:48:20 -07:00
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2015-07-27 13:17:45 -07:00
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2016-02-22 11:19:15 +01:00
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2016-02-27 08:04:48 -06:00
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2016-02-22 11:19:15 +01:00
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2015-07-27 13:17:45 -07:00
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2015-09-10 13:53:27 -07:00
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2016-02-27 08:04:48 -06:00
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2016-02-27 08:04:48 -06:00
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2015-07-27 13:17:45 -07:00
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2016-02-27 08:04:48 -06:00
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2015-08-18 14:39:26 -04:00
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2016-02-27 08:04:48 -06:00
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2015-08-18 14:39:26 -04:00
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2015-07-19 15:48:20 -07:00
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2016-02-22 11:19:15 +01:00
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2016-02-27 08:04:48 -06:00
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2016-02-22 11:19:15 +01:00
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2015-07-19 15:48:20 -07:00
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2016-02-22 11:19:15 +01:00
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2016-02-27 08:04:48 -06:00
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2016-02-22 11:19:15 +01:00
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2015-07-19 15:48:20 -07:00
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2016-02-22 11:19:15 +01:00
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2016-02-27 08:04:48 -06:00
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2016-02-22 11:19:15 +01:00
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2015-07-19 15:48:20 -07:00
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2016-02-22 11:19:15 +01:00
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2016-02-27 08:04:48 -06:00
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2016-02-22 11:19:15 +01:00
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2015-07-19 15:48:20 -07:00
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2015-07-27 13:17:45 -07:00
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2016-02-22 11:19:15 +01:00
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2016-02-27 08:04:48 -06:00
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2016-02-22 11:19:15 +01:00
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2015-07-27 13:17:45 -07:00
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2015-09-10 13:53:27 -07:00
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2016-02-27 08:04:48 -06:00
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2015-09-10 13:53:27 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-27 13:17:45 -07:00
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2015-08-18 14:39:26 -04:00
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2016-02-27 08:04:48 -06:00
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2015-08-18 14:39:26 -04:00
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2016-02-27 08:04:48 -06:00
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2015-08-18 14:39:26 -04:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-08-18 14:39:26 -04:00
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2016-02-27 08:04:48 -06:00
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2015-08-18 14:39:26 -04:00
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2016-02-27 08:04:48 -06:00
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2015-08-18 14:39:26 -04:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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|
2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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|
2016-02-27 08:04:48 -06:00
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argLen: 2,
|
2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-08-18 14:39:26 -04:00
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|
2016-02-27 08:04:48 -06:00
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2015-08-18 14:39:26 -04:00
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2016-02-27 08:04:48 -06:00
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2015-08-18 14:39:26 -04:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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argLen: 2,
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2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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2016-02-27 08:04:48 -06:00
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argLen: 2,
|
2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
|
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2016-02-27 08:04:48 -06:00
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argLen: 2,
|
2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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|
2016-02-27 08:04:48 -06:00
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argLen: 2,
|
2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
|
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2016-02-27 08:04:48 -06:00
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argLen: 2,
|
2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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|
2016-02-27 08:04:48 -06:00
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argLen: 2,
|
2015-07-19 15:48:20 -07:00
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2015-07-21 07:10:56 -07:00
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|
2016-02-27 08:04:48 -06:00
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argLen: 2,
|
2015-07-19 15:48:20 -07:00
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2015-08-18 14:39:26 -04:00
|
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{
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name: "Greater32F",
|
2016-02-27 08:04:48 -06:00
|
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argLen: 2,
|
2015-08-18 14:39:26 -04:00
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|
2016-02-27 08:04:48 -06:00
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argLen: 2,
|
2015-08-18 14:39:26 -04:00
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generic: true,
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|
2015-07-19 15:48:20 -07:00
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{
|
2015-07-21 07:10:56 -07:00
|
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|
name: "Geq8",
|
2016-02-27 08:04:48 -06:00
|
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|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
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generic: true,
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{
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2015-07-21 07:10:56 -07:00
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name: "Geq8U",
|
2016-02-27 08:04:48 -06:00
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argLen: 2,
|
2015-06-06 16:03:33 -07:00
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generic: true,
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|
2015-06-24 17:48:22 -07:00
|
|
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{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq16",
|
2016-02-27 08:04:48 -06:00
|
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|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
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generic: true,
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{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq16U",
|
2016-02-27 08:04:48 -06:00
|
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|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
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|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
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|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq32U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq64U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
|
|
|
|
name: "Geq32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Geq64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-10 11:25:48 -06:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Not",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-10 11:25:48 -06:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
|
|
|
|
name: "Neg8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-21 16:58:18 +02:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-21 16:58:18 +02:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-21 16:58:18 +02:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-21 16:58:18 +02:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-28 14:24:10 -04:00
|
|
|
{
|
|
|
|
|
name: "Neg32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-29 17:07:09 -07:00
|
|
|
{
|
|
|
|
|
name: "Com8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Com16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Com32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Com64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-09-12 13:26:57 -07:00
|
|
|
{
|
|
|
|
|
name: "Sqrt",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-09-12 13:26:57 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Phi",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: -1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Copy",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-10-19 11:36:07 -04:00
|
|
|
{
|
|
|
|
|
name: "Convert",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-10-19 11:36:07 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-28 14:19:20 -07:00
|
|
|
name: "ConstBool",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxBool,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ConstString",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxString,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ConstNil",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const8",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const16",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const32",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const64",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
|
|
|
|
name: "Const32F",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxFloat,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const64F",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxFloat,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 10:26:28 -07:00
|
|
|
{
|
|
|
|
|
name: "ConstInterface",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-08-18 10:26:28 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ConstSlice",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-08-18 10:26:28 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-11-02 08:10:26 -08:00
|
|
|
{
|
|
|
|
|
name: "InitMem",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-11-02 08:10:26 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Arg",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Addr",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SP",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SB",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Func",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Load",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Store",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Move",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-27 15:45:20 +01:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Zero",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-27 15:45:20 +01:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "ClosureCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StaticCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-28 22:51:01 -07:00
|
|
|
{
|
|
|
|
|
name: "DeferCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 22:51:01 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "GoCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 22:51:01 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-09-09 23:56:59 -07:00
|
|
|
{
|
|
|
|
|
name: "InterCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-09-09 23:56:59 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
name: "SignExt8to16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt8to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt8to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt16to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt16to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt32to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt8to16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt8to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt8to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt16to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt16to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt32to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc16to8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc32to8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc32to16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc64to8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc64to16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc64to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-20 15:14:20 -04:00
|
|
|
{
|
|
|
|
|
name: "Cvt32to32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32to64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64to32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64to64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32Fto32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32Fto64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64Fto32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64Fto64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32Fto64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64Fto32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "IsNonNil",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "IsInBounds",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-24 23:52:03 -07:00
|
|
|
{
|
|
|
|
|
name: "IsSliceInBounds",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-24 23:52:03 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-11 09:47:45 -07:00
|
|
|
{
|
2015-10-23 19:12:49 -07:00
|
|
|
name: "NilCheck",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-11 09:47:45 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-12 11:22:16 -07:00
|
|
|
{
|
|
|
|
|
name: "GetG",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-12 11:22:16 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-09-11 16:40:05 -04:00
|
|
|
{
|
|
|
|
|
name: "GetClosurePtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-09-11 16:40:05 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "ArrayIndex",
|
2016-03-01 15:59:15 -08:00
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "PtrIndex",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "OffPtr",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SliceMake",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SlicePtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SliceLen",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SliceCap",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-28 14:24:10 -04:00
|
|
|
{
|
|
|
|
|
name: "ComplexMake",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ComplexReal",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ComplexImag",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StringMake",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StringPtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StringLen",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 10:26:28 -07:00
|
|
|
{
|
|
|
|
|
name: "IMake",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 10:26:28 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-04 15:47:22 -07:00
|
|
|
{
|
|
|
|
|
name: "ITab",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-04 15:47:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 10:26:28 -07:00
|
|
|
{
|
|
|
|
|
name: "IData",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-18 10:26:28 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-01-11 21:05:33 -08:00
|
|
|
{
|
|
|
|
|
name: "StructMake0",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructMake1",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructMake2",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructMake3",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructMake4",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructSelect",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-24 14:51:51 -07:00
|
|
|
name: "StoreReg",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-24 14:51:51 -07:00
|
|
|
name: "LoadReg",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "FwdRef",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-01-14 16:02:23 -08:00
|
|
|
{
|
|
|
|
|
name: "Unknown",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-14 16:02:23 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-24 02:16:19 -07:00
|
|
|
{
|
|
|
|
|
name: "VarDef",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-24 02:16:19 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "VarKill",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-24 02:16:19 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-01-19 09:59:21 -08:00
|
|
|
{
|
|
|
|
|
name: "VarLive",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-19 09:59:21 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
}
|
|
|
|
|
|
2015-06-16 11:11:16 -07:00
|
|
|
func (o Op) Asm() int { return opcodeTable[o].asm }
|
2015-06-06 16:03:33 -07:00
|
|
|
func (o Op) String() string { return opcodeTable[o].name }
|