2015-06-06 16:03:33 -07:00
|
|
|
// autogenerated: do not edit!
|
|
|
|
|
// generated from gen/*Ops.go
|
2016-03-01 10:58:06 -08:00
|
|
|
|
2015-06-06 16:03:33 -07:00
|
|
|
package ssa
|
|
|
|
|
|
2016-03-07 18:00:08 -08:00
|
|
|
import (
|
|
|
|
|
"cmd/internal/obj"
|
2016-03-21 22:57:26 -07:00
|
|
|
"cmd/internal/obj/arm"
|
2016-03-07 18:00:08 -08:00
|
|
|
"cmd/internal/obj/x86"
|
|
|
|
|
)
|
2015-06-16 11:11:16 -07:00
|
|
|
|
2015-06-06 16:03:33 -07:00
|
|
|
const (
|
2015-08-18 14:39:26 -04:00
|
|
|
BlockInvalid BlockKind = iota
|
2015-06-06 16:03:33 -07:00
|
|
|
|
|
|
|
|
BlockAMD64EQ
|
|
|
|
|
BlockAMD64NE
|
|
|
|
|
BlockAMD64LT
|
|
|
|
|
BlockAMD64LE
|
|
|
|
|
BlockAMD64GT
|
|
|
|
|
BlockAMD64GE
|
|
|
|
|
BlockAMD64ULT
|
|
|
|
|
BlockAMD64ULE
|
|
|
|
|
BlockAMD64UGT
|
|
|
|
|
BlockAMD64UGE
|
2015-08-18 14:39:26 -04:00
|
|
|
BlockAMD64EQF
|
|
|
|
|
BlockAMD64NEF
|
|
|
|
|
BlockAMD64ORD
|
|
|
|
|
BlockAMD64NAN
|
2015-06-06 16:03:33 -07:00
|
|
|
|
2016-03-21 22:57:26 -07:00
|
|
|
BlockARMEQ
|
|
|
|
|
BlockARMNE
|
|
|
|
|
BlockARMLT
|
|
|
|
|
BlockARMLE
|
|
|
|
|
BlockARMGT
|
|
|
|
|
BlockARMGE
|
|
|
|
|
BlockARMULT
|
|
|
|
|
BlockARMULE
|
|
|
|
|
BlockARMUGT
|
|
|
|
|
BlockARMUGE
|
|
|
|
|
|
2015-06-06 16:03:33 -07:00
|
|
|
BlockPlain
|
|
|
|
|
BlockIf
|
|
|
|
|
BlockCall
|
2016-03-09 19:27:57 -08:00
|
|
|
BlockDefer
|
2015-10-23 19:12:49 -07:00
|
|
|
BlockCheck
|
2015-09-03 09:09:59 -07:00
|
|
|
BlockRet
|
2015-09-08 21:28:44 -07:00
|
|
|
BlockRetJmp
|
2015-09-09 18:03:41 -07:00
|
|
|
BlockExit
|
|
|
|
|
BlockFirst
|
|
|
|
|
BlockDead
|
2015-06-06 16:03:33 -07:00
|
|
|
)
|
|
|
|
|
|
|
|
|
|
var blockString = [...]string{
|
2015-08-18 14:39:26 -04:00
|
|
|
BlockInvalid: "BlockInvalid",
|
2015-06-06 16:03:33 -07:00
|
|
|
|
|
|
|
|
BlockAMD64EQ: "EQ",
|
|
|
|
|
BlockAMD64NE: "NE",
|
|
|
|
|
BlockAMD64LT: "LT",
|
|
|
|
|
BlockAMD64LE: "LE",
|
|
|
|
|
BlockAMD64GT: "GT",
|
|
|
|
|
BlockAMD64GE: "GE",
|
|
|
|
|
BlockAMD64ULT: "ULT",
|
|
|
|
|
BlockAMD64ULE: "ULE",
|
|
|
|
|
BlockAMD64UGT: "UGT",
|
|
|
|
|
BlockAMD64UGE: "UGE",
|
2015-08-18 14:39:26 -04:00
|
|
|
BlockAMD64EQF: "EQF",
|
|
|
|
|
BlockAMD64NEF: "NEF",
|
|
|
|
|
BlockAMD64ORD: "ORD",
|
|
|
|
|
BlockAMD64NAN: "NAN",
|
2015-06-06 16:03:33 -07:00
|
|
|
|
2016-03-21 22:57:26 -07:00
|
|
|
BlockARMEQ: "EQ",
|
|
|
|
|
BlockARMNE: "NE",
|
|
|
|
|
BlockARMLT: "LT",
|
|
|
|
|
BlockARMLE: "LE",
|
|
|
|
|
BlockARMGT: "GT",
|
|
|
|
|
BlockARMGE: "GE",
|
|
|
|
|
BlockARMULT: "ULT",
|
|
|
|
|
BlockARMULE: "ULE",
|
|
|
|
|
BlockARMUGT: "UGT",
|
|
|
|
|
BlockARMUGE: "UGE",
|
|
|
|
|
|
2015-09-08 21:28:44 -07:00
|
|
|
BlockPlain: "Plain",
|
|
|
|
|
BlockIf: "If",
|
|
|
|
|
BlockCall: "Call",
|
2016-03-09 19:27:57 -08:00
|
|
|
BlockDefer: "Defer",
|
2015-10-23 19:12:49 -07:00
|
|
|
BlockCheck: "Check",
|
2015-09-08 21:28:44 -07:00
|
|
|
BlockRet: "Ret",
|
|
|
|
|
BlockRetJmp: "RetJmp",
|
2015-09-09 18:03:41 -07:00
|
|
|
BlockExit: "Exit",
|
|
|
|
|
BlockFirst: "First",
|
|
|
|
|
BlockDead: "Dead",
|
2015-06-06 16:03:33 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
func (k BlockKind) String() string { return blockString[k] }
|
|
|
|
|
|
|
|
|
|
const (
|
|
|
|
|
OpInvalid Op = iota
|
|
|
|
|
|
2015-08-12 16:38:11 -04:00
|
|
|
OpAMD64ADDSS
|
|
|
|
|
OpAMD64ADDSD
|
|
|
|
|
OpAMD64SUBSS
|
|
|
|
|
OpAMD64SUBSD
|
|
|
|
|
OpAMD64MULSS
|
|
|
|
|
OpAMD64MULSD
|
|
|
|
|
OpAMD64DIVSS
|
|
|
|
|
OpAMD64DIVSD
|
|
|
|
|
OpAMD64MOVSSload
|
|
|
|
|
OpAMD64MOVSDload
|
|
|
|
|
OpAMD64MOVSSconst
|
|
|
|
|
OpAMD64MOVSDconst
|
|
|
|
|
OpAMD64MOVSSloadidx4
|
|
|
|
|
OpAMD64MOVSDloadidx8
|
|
|
|
|
OpAMD64MOVSSstore
|
|
|
|
|
OpAMD64MOVSDstore
|
|
|
|
|
OpAMD64MOVSSstoreidx4
|
|
|
|
|
OpAMD64MOVSDstoreidx8
|
2015-07-28 16:04:50 -07:00
|
|
|
OpAMD64ADDQ
|
|
|
|
|
OpAMD64ADDL
|
|
|
|
|
OpAMD64ADDW
|
|
|
|
|
OpAMD64ADDB
|
|
|
|
|
OpAMD64ADDQconst
|
|
|
|
|
OpAMD64ADDLconst
|
|
|
|
|
OpAMD64ADDWconst
|
|
|
|
|
OpAMD64ADDBconst
|
|
|
|
|
OpAMD64SUBQ
|
|
|
|
|
OpAMD64SUBL
|
|
|
|
|
OpAMD64SUBW
|
|
|
|
|
OpAMD64SUBB
|
|
|
|
|
OpAMD64SUBQconst
|
|
|
|
|
OpAMD64SUBLconst
|
|
|
|
|
OpAMD64SUBWconst
|
|
|
|
|
OpAMD64SUBBconst
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64MULQ
|
2015-07-28 16:04:50 -07:00
|
|
|
OpAMD64MULL
|
|
|
|
|
OpAMD64MULW
|
2015-08-14 13:23:11 +02:00
|
|
|
OpAMD64MULB
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64MULQconst
|
2015-07-28 16:04:50 -07:00
|
|
|
OpAMD64MULLconst
|
|
|
|
|
OpAMD64MULWconst
|
2015-08-14 13:23:11 +02:00
|
|
|
OpAMD64MULBconst
|
2016-02-05 20:26:18 -08:00
|
|
|
OpAMD64HMULQ
|
2015-08-18 19:14:47 -05:00
|
|
|
OpAMD64HMULL
|
|
|
|
|
OpAMD64HMULW
|
|
|
|
|
OpAMD64HMULB
|
2016-02-05 20:26:18 -08:00
|
|
|
OpAMD64HMULQU
|
2015-08-18 19:14:47 -05:00
|
|
|
OpAMD64HMULLU
|
|
|
|
|
OpAMD64HMULWU
|
|
|
|
|
OpAMD64HMULBU
|
2016-02-05 20:26:18 -08:00
|
|
|
OpAMD64AVGQU
|
2015-08-17 17:46:06 -05:00
|
|
|
OpAMD64DIVQ
|
|
|
|
|
OpAMD64DIVL
|
|
|
|
|
OpAMD64DIVW
|
|
|
|
|
OpAMD64DIVQU
|
|
|
|
|
OpAMD64DIVLU
|
|
|
|
|
OpAMD64DIVWU
|
2015-08-18 19:51:44 -05:00
|
|
|
OpAMD64MODQ
|
|
|
|
|
OpAMD64MODL
|
|
|
|
|
OpAMD64MODW
|
|
|
|
|
OpAMD64MODQU
|
|
|
|
|
OpAMD64MODLU
|
|
|
|
|
OpAMD64MODWU
|
2015-07-28 16:04:50 -07:00
|
|
|
OpAMD64ANDQ
|
|
|
|
|
OpAMD64ANDL
|
|
|
|
|
OpAMD64ANDW
|
|
|
|
|
OpAMD64ANDB
|
|
|
|
|
OpAMD64ANDQconst
|
|
|
|
|
OpAMD64ANDLconst
|
|
|
|
|
OpAMD64ANDWconst
|
|
|
|
|
OpAMD64ANDBconst
|
|
|
|
|
OpAMD64ORQ
|
|
|
|
|
OpAMD64ORL
|
|
|
|
|
OpAMD64ORW
|
|
|
|
|
OpAMD64ORB
|
|
|
|
|
OpAMD64ORQconst
|
|
|
|
|
OpAMD64ORLconst
|
|
|
|
|
OpAMD64ORWconst
|
|
|
|
|
OpAMD64ORBconst
|
|
|
|
|
OpAMD64XORQ
|
|
|
|
|
OpAMD64XORL
|
|
|
|
|
OpAMD64XORW
|
|
|
|
|
OpAMD64XORB
|
2015-07-10 11:25:48 -06:00
|
|
|
OpAMD64XORQconst
|
2015-07-28 16:04:50 -07:00
|
|
|
OpAMD64XORLconst
|
|
|
|
|
OpAMD64XORWconst
|
|
|
|
|
OpAMD64XORBconst
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64CMPQ
|
2015-07-21 18:06:15 +02:00
|
|
|
OpAMD64CMPL
|
|
|
|
|
OpAMD64CMPW
|
|
|
|
|
OpAMD64CMPB
|
2015-07-28 16:04:50 -07:00
|
|
|
OpAMD64CMPQconst
|
|
|
|
|
OpAMD64CMPLconst
|
|
|
|
|
OpAMD64CMPWconst
|
|
|
|
|
OpAMD64CMPBconst
|
2015-08-18 14:39:26 -04:00
|
|
|
OpAMD64UCOMISS
|
|
|
|
|
OpAMD64UCOMISD
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64TESTQ
|
2015-07-28 16:04:50 -07:00
|
|
|
OpAMD64TESTL
|
|
|
|
|
OpAMD64TESTW
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64TESTB
|
2015-07-28 16:04:50 -07:00
|
|
|
OpAMD64TESTQconst
|
|
|
|
|
OpAMD64TESTLconst
|
|
|
|
|
OpAMD64TESTWconst
|
|
|
|
|
OpAMD64TESTBconst
|
|
|
|
|
OpAMD64SHLQ
|
|
|
|
|
OpAMD64SHLL
|
|
|
|
|
OpAMD64SHLW
|
|
|
|
|
OpAMD64SHLB
|
|
|
|
|
OpAMD64SHLQconst
|
|
|
|
|
OpAMD64SHLLconst
|
|
|
|
|
OpAMD64SHLWconst
|
|
|
|
|
OpAMD64SHLBconst
|
|
|
|
|
OpAMD64SHRQ
|
|
|
|
|
OpAMD64SHRL
|
|
|
|
|
OpAMD64SHRW
|
|
|
|
|
OpAMD64SHRB
|
|
|
|
|
OpAMD64SHRQconst
|
|
|
|
|
OpAMD64SHRLconst
|
|
|
|
|
OpAMD64SHRWconst
|
|
|
|
|
OpAMD64SHRBconst
|
|
|
|
|
OpAMD64SARQ
|
|
|
|
|
OpAMD64SARL
|
|
|
|
|
OpAMD64SARW
|
|
|
|
|
OpAMD64SARB
|
|
|
|
|
OpAMD64SARQconst
|
|
|
|
|
OpAMD64SARLconst
|
|
|
|
|
OpAMD64SARWconst
|
|
|
|
|
OpAMD64SARBconst
|
2015-08-05 22:11:14 -04:00
|
|
|
OpAMD64ROLQconst
|
|
|
|
|
OpAMD64ROLLconst
|
|
|
|
|
OpAMD64ROLWconst
|
|
|
|
|
OpAMD64ROLBconst
|
2015-07-28 16:04:50 -07:00
|
|
|
OpAMD64NEGQ
|
|
|
|
|
OpAMD64NEGL
|
|
|
|
|
OpAMD64NEGW
|
|
|
|
|
OpAMD64NEGB
|
2015-07-29 17:07:09 -07:00
|
|
|
OpAMD64NOTQ
|
|
|
|
|
OpAMD64NOTL
|
|
|
|
|
OpAMD64NOTW
|
|
|
|
|
OpAMD64NOTB
|
2016-03-11 00:10:52 -05:00
|
|
|
OpAMD64BSFQ
|
|
|
|
|
OpAMD64BSFL
|
|
|
|
|
OpAMD64BSFW
|
|
|
|
|
OpAMD64BSRQ
|
|
|
|
|
OpAMD64BSRL
|
|
|
|
|
OpAMD64BSRW
|
|
|
|
|
OpAMD64CMOVQEQconst
|
|
|
|
|
OpAMD64CMOVLEQconst
|
|
|
|
|
OpAMD64CMOVWEQconst
|
|
|
|
|
OpAMD64CMOVQNEconst
|
|
|
|
|
OpAMD64CMOVLNEconst
|
|
|
|
|
OpAMD64CMOVWNEconst
|
|
|
|
|
OpAMD64BSWAPQ
|
|
|
|
|
OpAMD64BSWAPL
|
2015-09-12 13:26:57 -07:00
|
|
|
OpAMD64SQRTSD
|
2015-06-10 10:39:57 -07:00
|
|
|
OpAMD64SBBQcarrymask
|
2015-07-29 17:07:09 -07:00
|
|
|
OpAMD64SBBLcarrymask
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64SETEQ
|
|
|
|
|
OpAMD64SETNE
|
|
|
|
|
OpAMD64SETL
|
2015-06-24 17:48:22 -07:00
|
|
|
OpAMD64SETLE
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64SETG
|
|
|
|
|
OpAMD64SETGE
|
|
|
|
|
OpAMD64SETB
|
2015-07-24 12:47:00 -07:00
|
|
|
OpAMD64SETBE
|
|
|
|
|
OpAMD64SETA
|
|
|
|
|
OpAMD64SETAE
|
2015-08-18 14:39:26 -04:00
|
|
|
OpAMD64SETEQF
|
|
|
|
|
OpAMD64SETNEF
|
|
|
|
|
OpAMD64SETORD
|
|
|
|
|
OpAMD64SETNAN
|
|
|
|
|
OpAMD64SETGF
|
|
|
|
|
OpAMD64SETGEF
|
2015-06-14 11:38:46 -07:00
|
|
|
OpAMD64MOVBQSX
|
2015-07-22 13:46:15 -07:00
|
|
|
OpAMD64MOVBQZX
|
|
|
|
|
OpAMD64MOVWQSX
|
|
|
|
|
OpAMD64MOVWQZX
|
|
|
|
|
OpAMD64MOVLQSX
|
|
|
|
|
OpAMD64MOVLQZX
|
2015-07-28 14:19:20 -07:00
|
|
|
OpAMD64MOVBconst
|
|
|
|
|
OpAMD64MOVWconst
|
|
|
|
|
OpAMD64MOVLconst
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64MOVQconst
|
2015-09-01 19:05:44 -05:00
|
|
|
OpAMD64CVTTSD2SL
|
|
|
|
|
OpAMD64CVTTSD2SQ
|
|
|
|
|
OpAMD64CVTTSS2SL
|
|
|
|
|
OpAMD64CVTTSS2SQ
|
2015-08-20 15:14:20 -04:00
|
|
|
OpAMD64CVTSL2SS
|
|
|
|
|
OpAMD64CVTSL2SD
|
|
|
|
|
OpAMD64CVTSQ2SS
|
|
|
|
|
OpAMD64CVTSQ2SD
|
|
|
|
|
OpAMD64CVTSD2SS
|
|
|
|
|
OpAMD64CVTSS2SD
|
2015-08-28 14:24:10 -04:00
|
|
|
OpAMD64PXOR
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64LEAQ
|
2015-06-19 21:02:28 -07:00
|
|
|
OpAMD64LEAQ1
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64LEAQ2
|
|
|
|
|
OpAMD64LEAQ4
|
|
|
|
|
OpAMD64LEAQ8
|
|
|
|
|
OpAMD64MOVBload
|
|
|
|
|
OpAMD64MOVBQSXload
|
2015-06-14 11:38:46 -07:00
|
|
|
OpAMD64MOVWload
|
2016-01-30 11:25:38 -08:00
|
|
|
OpAMD64MOVWQSXload
|
2015-06-14 11:38:46 -07:00
|
|
|
OpAMD64MOVLload
|
2016-01-30 11:25:38 -08:00
|
|
|
OpAMD64MOVLQSXload
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64MOVQload
|
|
|
|
|
OpAMD64MOVBstore
|
2015-06-14 11:38:46 -07:00
|
|
|
OpAMD64MOVWstore
|
|
|
|
|
OpAMD64MOVLstore
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64MOVQstore
|
2016-02-02 11:13:50 -08:00
|
|
|
OpAMD64MOVOload
|
|
|
|
|
OpAMD64MOVOstore
|
|
|
|
|
OpAMD64MOVBloadidx1
|
cmd/compile: fix plan9-amd64 build
The previous rules to combine indexed loads produced addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_CX,
Name: NAME_AUTO,
Offset: 121,
...
}
which are erroneous because NAME_AUTO implies a base register of
REG_SP, and cmd/internal/obj/x86 makes many assumptions to this
effect. Note that previously we were also producing an extra "ADDQ
SP, CX" instruction, so indexing off of SP was already handled.
The approach taken by this CL to address the problem is to instead
produce addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_SP,
Name: NAME_AUTO,
Offset: 121,
Index: REG_CX,
Scale: 1,
}
and to omit the "ADDQ SP, CX" instruction.
Downside to this approach is it requires adding a lot of new
MOV[WLQ]loadidx1 instructions that nearly duplicate functionality of
the existing MOV[WLQ]loadidx[248] instructions, but with a different
Scale.
Fixes #15001.
Change-Id: Iad9a1a41e5e2552f8d22e3ba975e4ea0862dffd2
Reviewed-on: https://go-review.googlesource.com/21245
Run-TryBot: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
2016-03-28 19:10:13 -07:00
|
|
|
OpAMD64MOVWloadidx1
|
2016-02-02 11:13:50 -08:00
|
|
|
OpAMD64MOVWloadidx2
|
cmd/compile: fix plan9-amd64 build
The previous rules to combine indexed loads produced addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_CX,
Name: NAME_AUTO,
Offset: 121,
...
}
which are erroneous because NAME_AUTO implies a base register of
REG_SP, and cmd/internal/obj/x86 makes many assumptions to this
effect. Note that previously we were also producing an extra "ADDQ
SP, CX" instruction, so indexing off of SP was already handled.
The approach taken by this CL to address the problem is to instead
produce addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_SP,
Name: NAME_AUTO,
Offset: 121,
Index: REG_CX,
Scale: 1,
}
and to omit the "ADDQ SP, CX" instruction.
Downside to this approach is it requires adding a lot of new
MOV[WLQ]loadidx1 instructions that nearly duplicate functionality of
the existing MOV[WLQ]loadidx[248] instructions, but with a different
Scale.
Fixes #15001.
Change-Id: Iad9a1a41e5e2552f8d22e3ba975e4ea0862dffd2
Reviewed-on: https://go-review.googlesource.com/21245
Run-TryBot: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
2016-03-28 19:10:13 -07:00
|
|
|
OpAMD64MOVLloadidx1
|
2016-02-02 11:13:50 -08:00
|
|
|
OpAMD64MOVLloadidx4
|
cmd/compile: fix plan9-amd64 build
The previous rules to combine indexed loads produced addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_CX,
Name: NAME_AUTO,
Offset: 121,
...
}
which are erroneous because NAME_AUTO implies a base register of
REG_SP, and cmd/internal/obj/x86 makes many assumptions to this
effect. Note that previously we were also producing an extra "ADDQ
SP, CX" instruction, so indexing off of SP was already handled.
The approach taken by this CL to address the problem is to instead
produce addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_SP,
Name: NAME_AUTO,
Offset: 121,
Index: REG_CX,
Scale: 1,
}
and to omit the "ADDQ SP, CX" instruction.
Downside to this approach is it requires adding a lot of new
MOV[WLQ]loadidx1 instructions that nearly duplicate functionality of
the existing MOV[WLQ]loadidx[248] instructions, but with a different
Scale.
Fixes #15001.
Change-Id: Iad9a1a41e5e2552f8d22e3ba975e4ea0862dffd2
Reviewed-on: https://go-review.googlesource.com/21245
Run-TryBot: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
2016-03-28 19:10:13 -07:00
|
|
|
OpAMD64MOVQloadidx1
|
2016-02-02 11:13:50 -08:00
|
|
|
OpAMD64MOVQloadidx8
|
2016-01-30 11:25:38 -08:00
|
|
|
OpAMD64MOVBstoreidx1
|
|
|
|
|
OpAMD64MOVWstoreidx2
|
|
|
|
|
OpAMD64MOVLstoreidx4
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64MOVQstoreidx8
|
2015-10-21 13:13:56 -07:00
|
|
|
OpAMD64MOVBstoreconst
|
|
|
|
|
OpAMD64MOVWstoreconst
|
|
|
|
|
OpAMD64MOVLstoreconst
|
|
|
|
|
OpAMD64MOVQstoreconst
|
2016-02-04 15:53:33 -08:00
|
|
|
OpAMD64MOVBstoreconstidx1
|
|
|
|
|
OpAMD64MOVWstoreconstidx2
|
|
|
|
|
OpAMD64MOVLstoreconstidx4
|
|
|
|
|
OpAMD64MOVQstoreconstidx8
|
2015-09-18 18:23:34 -07:00
|
|
|
OpAMD64DUFFZERO
|
2015-10-19 13:56:55 -07:00
|
|
|
OpAMD64MOVOconst
|
2015-06-27 15:45:20 +01:00
|
|
|
OpAMD64REPSTOSQ
|
2015-06-10 15:03:06 -07:00
|
|
|
OpAMD64CALLstatic
|
|
|
|
|
OpAMD64CALLclosure
|
2015-08-28 22:51:01 -07:00
|
|
|
OpAMD64CALLdefer
|
|
|
|
|
OpAMD64CALLgo
|
2015-09-09 23:56:59 -07:00
|
|
|
OpAMD64CALLinter
|
2015-10-21 17:18:07 -07:00
|
|
|
OpAMD64DUFFCOPY
|
|
|
|
|
OpAMD64REPMOVSQ
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64InvertFlags
|
2015-08-12 11:22:16 -07:00
|
|
|
OpAMD64LoweredGetG
|
2015-09-11 16:40:05 -04:00
|
|
|
OpAMD64LoweredGetClosurePtr
|
2015-10-23 19:12:49 -07:00
|
|
|
OpAMD64LoweredNilCheck
|
2015-11-10 15:35:36 -08:00
|
|
|
OpAMD64MOVQconvert
|
2016-01-05 14:56:26 -08:00
|
|
|
OpAMD64FlagEQ
|
|
|
|
|
OpAMD64FlagLT_ULT
|
|
|
|
|
OpAMD64FlagLT_UGT
|
|
|
|
|
OpAMD64FlagGT_UGT
|
|
|
|
|
OpAMD64FlagGT_ULT
|
2015-06-06 16:03:33 -07:00
|
|
|
|
2016-03-21 22:57:26 -07:00
|
|
|
OpARMADD
|
|
|
|
|
OpARMADDconst
|
|
|
|
|
OpARMMOVWconst
|
|
|
|
|
OpARMCMP
|
|
|
|
|
OpARMMOVWload
|
|
|
|
|
OpARMMOVWstore
|
|
|
|
|
OpARMCALLstatic
|
|
|
|
|
OpARMLessThan
|
|
|
|
|
|
2015-07-19 15:48:20 -07:00
|
|
|
OpAdd8
|
|
|
|
|
OpAdd16
|
|
|
|
|
OpAdd32
|
|
|
|
|
OpAdd64
|
|
|
|
|
OpAddPtr
|
2015-08-12 16:38:11 -04:00
|
|
|
OpAdd32F
|
|
|
|
|
OpAdd64F
|
2015-07-19 15:48:20 -07:00
|
|
|
OpSub8
|
|
|
|
|
OpSub16
|
|
|
|
|
OpSub32
|
|
|
|
|
OpSub64
|
2015-08-24 23:52:03 -07:00
|
|
|
OpSubPtr
|
2015-08-12 16:38:11 -04:00
|
|
|
OpSub32F
|
|
|
|
|
OpSub64F
|
2015-07-22 13:46:15 -07:00
|
|
|
OpMul8
|
|
|
|
|
OpMul16
|
|
|
|
|
OpMul32
|
|
|
|
|
OpMul64
|
2015-08-12 16:38:11 -04:00
|
|
|
OpMul32F
|
|
|
|
|
OpMul64F
|
|
|
|
|
OpDiv32F
|
|
|
|
|
OpDiv64F
|
2015-08-18 19:14:47 -05:00
|
|
|
OpHmul8
|
|
|
|
|
OpHmul8u
|
|
|
|
|
OpHmul16
|
|
|
|
|
OpHmul16u
|
|
|
|
|
OpHmul32
|
|
|
|
|
OpHmul32u
|
2016-02-05 20:26:18 -08:00
|
|
|
OpHmul64
|
|
|
|
|
OpHmul64u
|
|
|
|
|
OpAvg64u
|
2015-08-17 17:46:06 -05:00
|
|
|
OpDiv8
|
|
|
|
|
OpDiv8u
|
|
|
|
|
OpDiv16
|
|
|
|
|
OpDiv16u
|
|
|
|
|
OpDiv32
|
|
|
|
|
OpDiv32u
|
|
|
|
|
OpDiv64
|
|
|
|
|
OpDiv64u
|
2015-08-18 19:51:44 -05:00
|
|
|
OpMod8
|
|
|
|
|
OpMod8u
|
|
|
|
|
OpMod16
|
|
|
|
|
OpMod16u
|
|
|
|
|
OpMod32
|
|
|
|
|
OpMod32u
|
|
|
|
|
OpMod64
|
|
|
|
|
OpMod64u
|
2015-07-28 14:58:49 +02:00
|
|
|
OpAnd8
|
|
|
|
|
OpAnd16
|
|
|
|
|
OpAnd32
|
|
|
|
|
OpAnd64
|
2015-07-29 17:52:25 +02:00
|
|
|
OpOr8
|
|
|
|
|
OpOr16
|
|
|
|
|
OpOr32
|
|
|
|
|
OpOr64
|
2015-07-28 16:04:50 -07:00
|
|
|
OpXor8
|
|
|
|
|
OpXor16
|
|
|
|
|
OpXor32
|
|
|
|
|
OpXor64
|
2015-07-29 17:07:09 -07:00
|
|
|
OpLsh8x8
|
|
|
|
|
OpLsh8x16
|
|
|
|
|
OpLsh8x32
|
|
|
|
|
OpLsh8x64
|
|
|
|
|
OpLsh16x8
|
|
|
|
|
OpLsh16x16
|
|
|
|
|
OpLsh16x32
|
|
|
|
|
OpLsh16x64
|
|
|
|
|
OpLsh32x8
|
|
|
|
|
OpLsh32x16
|
|
|
|
|
OpLsh32x32
|
|
|
|
|
OpLsh32x64
|
|
|
|
|
OpLsh64x8
|
|
|
|
|
OpLsh64x16
|
|
|
|
|
OpLsh64x32
|
|
|
|
|
OpLsh64x64
|
|
|
|
|
OpRsh8x8
|
|
|
|
|
OpRsh8x16
|
|
|
|
|
OpRsh8x32
|
|
|
|
|
OpRsh8x64
|
|
|
|
|
OpRsh16x8
|
|
|
|
|
OpRsh16x16
|
|
|
|
|
OpRsh16x32
|
|
|
|
|
OpRsh16x64
|
|
|
|
|
OpRsh32x8
|
|
|
|
|
OpRsh32x16
|
|
|
|
|
OpRsh32x32
|
|
|
|
|
OpRsh32x64
|
|
|
|
|
OpRsh64x8
|
|
|
|
|
OpRsh64x16
|
|
|
|
|
OpRsh64x32
|
|
|
|
|
OpRsh64x64
|
|
|
|
|
OpRsh8Ux8
|
|
|
|
|
OpRsh8Ux16
|
|
|
|
|
OpRsh8Ux32
|
|
|
|
|
OpRsh8Ux64
|
|
|
|
|
OpRsh16Ux8
|
|
|
|
|
OpRsh16Ux16
|
|
|
|
|
OpRsh16Ux32
|
|
|
|
|
OpRsh16Ux64
|
|
|
|
|
OpRsh32Ux8
|
|
|
|
|
OpRsh32Ux16
|
|
|
|
|
OpRsh32Ux32
|
|
|
|
|
OpRsh32Ux64
|
|
|
|
|
OpRsh64Ux8
|
|
|
|
|
OpRsh64Ux16
|
|
|
|
|
OpRsh64Ux32
|
|
|
|
|
OpRsh64Ux64
|
2015-08-05 22:11:14 -04:00
|
|
|
OpLrot8
|
|
|
|
|
OpLrot16
|
|
|
|
|
OpLrot32
|
|
|
|
|
OpLrot64
|
2015-07-19 15:48:20 -07:00
|
|
|
OpEq8
|
|
|
|
|
OpEq16
|
|
|
|
|
OpEq32
|
|
|
|
|
OpEq64
|
2015-07-27 13:17:45 -07:00
|
|
|
OpEqPtr
|
2015-09-10 13:53:27 -07:00
|
|
|
OpEqInter
|
|
|
|
|
OpEqSlice
|
2015-08-18 14:39:26 -04:00
|
|
|
OpEq32F
|
|
|
|
|
OpEq64F
|
2015-07-19 15:48:20 -07:00
|
|
|
OpNeq8
|
|
|
|
|
OpNeq16
|
|
|
|
|
OpNeq32
|
|
|
|
|
OpNeq64
|
2015-07-27 13:17:45 -07:00
|
|
|
OpNeqPtr
|
2015-09-10 13:53:27 -07:00
|
|
|
OpNeqInter
|
|
|
|
|
OpNeqSlice
|
2015-08-18 14:39:26 -04:00
|
|
|
OpNeq32F
|
|
|
|
|
OpNeq64F
|
2015-07-19 15:48:20 -07:00
|
|
|
OpLess8
|
|
|
|
|
OpLess8U
|
|
|
|
|
OpLess16
|
|
|
|
|
OpLess16U
|
|
|
|
|
OpLess32
|
|
|
|
|
OpLess32U
|
|
|
|
|
OpLess64
|
|
|
|
|
OpLess64U
|
2015-08-18 14:39:26 -04:00
|
|
|
OpLess32F
|
|
|
|
|
OpLess64F
|
2015-07-19 15:48:20 -07:00
|
|
|
OpLeq8
|
|
|
|
|
OpLeq8U
|
|
|
|
|
OpLeq16
|
|
|
|
|
OpLeq16U
|
|
|
|
|
OpLeq32
|
|
|
|
|
OpLeq32U
|
|
|
|
|
OpLeq64
|
|
|
|
|
OpLeq64U
|
2015-08-18 14:39:26 -04:00
|
|
|
OpLeq32F
|
|
|
|
|
OpLeq64F
|
2015-07-19 15:48:20 -07:00
|
|
|
OpGreater8
|
|
|
|
|
OpGreater8U
|
|
|
|
|
OpGreater16
|
|
|
|
|
OpGreater16U
|
|
|
|
|
OpGreater32
|
|
|
|
|
OpGreater32U
|
|
|
|
|
OpGreater64
|
|
|
|
|
OpGreater64U
|
2015-08-18 14:39:26 -04:00
|
|
|
OpGreater32F
|
|
|
|
|
OpGreater64F
|
2015-07-19 15:48:20 -07:00
|
|
|
OpGeq8
|
|
|
|
|
OpGeq8U
|
|
|
|
|
OpGeq16
|
|
|
|
|
OpGeq16U
|
|
|
|
|
OpGeq32
|
|
|
|
|
OpGeq32U
|
|
|
|
|
OpGeq64
|
|
|
|
|
OpGeq64U
|
2015-08-18 14:39:26 -04:00
|
|
|
OpGeq32F
|
|
|
|
|
OpGeq64F
|
2015-07-10 11:25:48 -06:00
|
|
|
OpNot
|
2015-07-21 16:58:18 +02:00
|
|
|
OpNeg8
|
|
|
|
|
OpNeg16
|
|
|
|
|
OpNeg32
|
|
|
|
|
OpNeg64
|
2015-08-28 14:24:10 -04:00
|
|
|
OpNeg32F
|
|
|
|
|
OpNeg64F
|
2015-07-29 17:07:09 -07:00
|
|
|
OpCom8
|
|
|
|
|
OpCom16
|
|
|
|
|
OpCom32
|
|
|
|
|
OpCom64
|
2016-03-11 00:10:52 -05:00
|
|
|
OpCtz16
|
|
|
|
|
OpCtz32
|
|
|
|
|
OpCtz64
|
|
|
|
|
OpClz16
|
|
|
|
|
OpClz32
|
|
|
|
|
OpClz64
|
|
|
|
|
OpBswap32
|
|
|
|
|
OpBswap64
|
2015-09-12 13:26:57 -07:00
|
|
|
OpSqrt
|
2015-06-06 16:03:33 -07:00
|
|
|
OpPhi
|
|
|
|
|
OpCopy
|
2015-10-19 11:36:07 -04:00
|
|
|
OpConvert
|
2015-07-28 14:19:20 -07:00
|
|
|
OpConstBool
|
|
|
|
|
OpConstString
|
|
|
|
|
OpConstNil
|
|
|
|
|
OpConst8
|
|
|
|
|
OpConst16
|
|
|
|
|
OpConst32
|
|
|
|
|
OpConst64
|
2015-08-12 16:38:11 -04:00
|
|
|
OpConst32F
|
|
|
|
|
OpConst64F
|
2015-08-18 10:26:28 -07:00
|
|
|
OpConstInterface
|
|
|
|
|
OpConstSlice
|
2015-11-02 08:10:26 -08:00
|
|
|
OpInitMem
|
2015-06-06 16:03:33 -07:00
|
|
|
OpArg
|
2015-06-19 21:02:28 -07:00
|
|
|
OpAddr
|
2015-06-06 16:03:33 -07:00
|
|
|
OpSP
|
2015-06-19 21:02:28 -07:00
|
|
|
OpSB
|
2015-06-06 16:03:33 -07:00
|
|
|
OpFunc
|
|
|
|
|
OpLoad
|
|
|
|
|
OpStore
|
|
|
|
|
OpMove
|
2015-06-27 15:45:20 +01:00
|
|
|
OpZero
|
2015-06-10 15:03:06 -07:00
|
|
|
OpClosureCall
|
2015-06-06 16:03:33 -07:00
|
|
|
OpStaticCall
|
2015-08-28 22:51:01 -07:00
|
|
|
OpDeferCall
|
|
|
|
|
OpGoCall
|
2015-09-09 23:56:59 -07:00
|
|
|
OpInterCall
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
OpSignExt8to16
|
|
|
|
|
OpSignExt8to32
|
|
|
|
|
OpSignExt8to64
|
|
|
|
|
OpSignExt16to32
|
|
|
|
|
OpSignExt16to64
|
|
|
|
|
OpSignExt32to64
|
|
|
|
|
OpZeroExt8to16
|
|
|
|
|
OpZeroExt8to32
|
|
|
|
|
OpZeroExt8to64
|
|
|
|
|
OpZeroExt16to32
|
|
|
|
|
OpZeroExt16to64
|
|
|
|
|
OpZeroExt32to64
|
|
|
|
|
OpTrunc16to8
|
|
|
|
|
OpTrunc32to8
|
|
|
|
|
OpTrunc32to16
|
|
|
|
|
OpTrunc64to8
|
|
|
|
|
OpTrunc64to16
|
|
|
|
|
OpTrunc64to32
|
2015-08-20 15:14:20 -04:00
|
|
|
OpCvt32to32F
|
|
|
|
|
OpCvt32to64F
|
|
|
|
|
OpCvt64to32F
|
|
|
|
|
OpCvt64to64F
|
|
|
|
|
OpCvt32Fto32
|
|
|
|
|
OpCvt32Fto64
|
|
|
|
|
OpCvt64Fto32
|
|
|
|
|
OpCvt64Fto64
|
|
|
|
|
OpCvt32Fto64F
|
|
|
|
|
OpCvt64Fto32F
|
2015-06-06 16:03:33 -07:00
|
|
|
OpIsNonNil
|
|
|
|
|
OpIsInBounds
|
2015-08-24 23:52:03 -07:00
|
|
|
OpIsSliceInBounds
|
2015-10-23 19:12:49 -07:00
|
|
|
OpNilCheck
|
2015-08-12 11:22:16 -07:00
|
|
|
OpGetG
|
2015-09-11 16:40:05 -04:00
|
|
|
OpGetClosurePtr
|
2015-06-06 16:03:33 -07:00
|
|
|
OpArrayIndex
|
|
|
|
|
OpPtrIndex
|
|
|
|
|
OpOffPtr
|
|
|
|
|
OpSliceMake
|
|
|
|
|
OpSlicePtr
|
|
|
|
|
OpSliceLen
|
|
|
|
|
OpSliceCap
|
2015-08-28 14:24:10 -04:00
|
|
|
OpComplexMake
|
|
|
|
|
OpComplexReal
|
|
|
|
|
OpComplexImag
|
2015-06-06 16:03:33 -07:00
|
|
|
OpStringMake
|
|
|
|
|
OpStringPtr
|
|
|
|
|
OpStringLen
|
2015-08-18 10:26:28 -07:00
|
|
|
OpIMake
|
2015-08-04 15:47:22 -07:00
|
|
|
OpITab
|
2015-08-18 10:26:28 -07:00
|
|
|
OpIData
|
2016-01-11 21:05:33 -08:00
|
|
|
OpStructMake0
|
|
|
|
|
OpStructMake1
|
|
|
|
|
OpStructMake2
|
|
|
|
|
OpStructMake3
|
|
|
|
|
OpStructMake4
|
|
|
|
|
OpStructSelect
|
2015-07-24 14:51:51 -07:00
|
|
|
OpStoreReg
|
|
|
|
|
OpLoadReg
|
2015-06-06 16:03:33 -07:00
|
|
|
OpFwdRef
|
2016-01-14 16:02:23 -08:00
|
|
|
OpUnknown
|
2015-08-24 02:16:19 -07:00
|
|
|
OpVarDef
|
|
|
|
|
OpVarKill
|
2016-01-19 09:59:21 -08:00
|
|
|
OpVarLive
|
2015-06-06 16:03:33 -07:00
|
|
|
)
|
|
|
|
|
|
|
|
|
|
var opcodeTable = [...]opInfo{
|
|
|
|
|
{name: "OpInvalid"},
|
|
|
|
|
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ADDSS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AADDSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ADDSD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AADDSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBSS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
|
|
|
|
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 2147483648, // X15
|
2015-08-12 16:38:11 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBSD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
|
|
|
|
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 2147483648, // X15
|
2015-08-12 16:38:11 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULSS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AMULSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULSD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AMULSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "DIVSS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ADIVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
|
|
|
|
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 2147483648, // X15
|
2015-08-12 16:38:11 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "DIVSD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ADIVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
|
|
|
|
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 2147483648, // X15
|
2015-08-12 16:38:11 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSconst",
|
2016-03-11 19:36:54 -06:00
|
|
|
auxType: auxFloat32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDconst",
|
2016-03-11 19:36:54 -06:00
|
|
|
auxType: auxFloat64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSloadidx4",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDloadidx8",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSstoreidx4",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDstoreidx8",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ADDQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AADDQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ADDL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AADDL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ADDW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AADDL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ADDB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AADDL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ADDQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AADDQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ADDLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AADDL,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ADDWconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AADDL,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ADDBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AADDL,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-10 11:25:48 -06:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBQ,
|
2015-07-10 11:25:48 -06:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-10 11:25:48 -06:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-10 11:25:48 -06:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-10 11:25:48 -06:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 18:06:15 +02:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBL,
|
2015-07-21 18:06:15 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-21 18:06:15 +02:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBQ,
|
2015-07-21 18:06:15 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-21 18:06:15 +02:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBL,
|
2015-07-21 18:06:15 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-21 18:06:15 +02:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBWconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AIMULQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AIMULL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AIMULW,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-14 13:23:11 +02:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AIMULW,
|
2015-08-14 13:23:11 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-14 13:23:11 +02:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-08-14 13:23:11 +02:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-14 13:23:11 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AIMULQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-24 17:48:22 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AIMULL,
|
2015-06-24 17:48:22 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-24 17:48:22 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-24 17:48:22 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-24 17:48:22 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULWconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AIMULW,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-14 13:23:11 +02:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AIMULW,
|
2015-08-14 13:23:11 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-14 13:23:11 +02:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-08-14 13:23:11 +02:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-14 13:23:11 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-05 20:26:18 -08:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULQ,
|
2016-02-05 20:26:18 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-05 20:26:18 -08:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2016-02-05 20:26:18 -08:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2016-02-05 20:26:18 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 19:14:47 -05:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULL,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:14:47 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULW,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:14:47 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULB,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:14:47 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-05 20:26:18 -08:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULQU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULQ,
|
2016-02-05 20:26:18 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-05 20:26:18 -08:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2016-02-05 20:26:18 -08:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2016-02-05 20:26:18 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 19:14:47 -05:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULLU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULL,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:14:47 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULWU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULW,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:14:47 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULBU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULB,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:14:47 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-05 20:26:18 -08:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "AVGQU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
2016-02-05 20:26:18 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-05 20:26:18 -08:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2016-02-05 20:26:18 -08:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-05 20:26:18 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-17 17:46:06 -05:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVQ,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934596, // DX FLAGS
|
2015-08-17 17:46:06 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
1, // AX
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVL,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934596, // DX FLAGS
|
2015-08-17 17:46:06 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
1, // AX
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVW,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934596, // DX FLAGS
|
2015-08-17 17:46:06 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
1, // AX
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVQU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVQ,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934596, // DX FLAGS
|
2015-08-17 17:46:06 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
1, // AX
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVLU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVL,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934596, // DX FLAGS
|
2015-08-17 17:46:06 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
1, // AX
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVWU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVW,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934596, // DX FLAGS
|
2015-08-17 17:46:06 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
1, // AX
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 19:51:44 -05:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVQ,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:51:44 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVL,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:51:44 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVW,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:51:44 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODQU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVQ,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:51:44 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODLU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVL,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:51:44 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODWU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVW,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:51:44 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ANDQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AANDQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ANDL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AANDL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-24 12:47:00 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ANDW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AANDL,
|
2015-07-24 12:47:00 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-24 12:47:00 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-24 12:47:00 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-24 12:47:00 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ANDB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AANDL,
|
2015-07-24 12:47:00 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-24 12:47:00 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-24 12:47:00 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-24 12:47:00 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ANDQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AANDQ,
|
2015-07-24 12:47:00 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-24 12:47:00 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-24 12:47:00 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ANDLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AANDL,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-14 11:38:46 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ANDWconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AANDL,
|
2015-07-22 13:46:15 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-22 13:46:15 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ANDBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AANDL,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-14 11:38:46 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ORQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AORQ,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-14 11:38:46 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ORL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AORL,
|
2015-07-22 13:46:15 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-22 13:46:15 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ORW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AORL,
|
2015-07-22 13:46:15 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-22 13:46:15 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ORB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AORL,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-14 11:38:46 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 14:19:20 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ORQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AORQ,
|
2015-07-28 14:19:20 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ORLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ORWconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ORBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "XORQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AXORQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "XORL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "XORW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "XORB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "XORQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AXORQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "XORLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "XORWconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "XORBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CMPQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ACMPQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CMPL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ACMPL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CMPW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ACMPW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CMPB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ACMPB,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CMPQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ACMPQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CMPLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ACMPL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CMPWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ACMPW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CMPBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ACMPB,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "UCOMISS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AUCOMISS,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "UCOMISD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AUCOMISD,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "TESTQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ATESTQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "TESTL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ATESTL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "TESTW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ATESTW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "TESTB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ATESTB,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "TESTQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ATESTQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "TESTLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ATESTL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "TESTWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ATESTW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "TESTBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ATESTB,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHLQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHLQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHLL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHLW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHLB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHLQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHLQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHLLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHLWconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHLBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:19:20 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRL,
|
2015-07-28 14:19:20 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 14:19:20 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:19:20 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRW,
|
2015-07-28 14:19:20 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 14:19:20 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:19:20 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRWconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRW,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-19 21:02:28 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARW,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65517, // AX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-14 11:38:46 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARQ,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-14 11:38:46 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARL,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-14 11:38:46 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARWconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARW,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-05 22:11:14 -04:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ROLQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AROLQ,
|
2015-08-05 22:11:14 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-08-05 22:11:14 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ROLLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AROLL,
|
2015-08-05 22:11:14 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-08-05 22:11:14 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ROLWconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AROLW,
|
2015-08-05 22:11:14 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-08-05 22:11:14 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ROLBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AROLB,
|
2015-08-05 22:11:14 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-08-05 22:11:14 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "NEGQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ANEGQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-14 11:38:46 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "NEGL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ANEGL,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "NEGW",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ANEGL,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "NEGB",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ANEGL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:07:09 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "NOTQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ANOTQ,
|
2015-07-29 17:07:09 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-29 17:07:09 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "NOTL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ANOTL,
|
2015-07-29 17:07:09 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-29 17:07:09 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "NOTW",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ANOTL,
|
2015-07-29 17:07:09 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-29 17:07:09 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "NOTB",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ANOTL,
|
2015-07-29 17:07:09 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-29 17:07:09 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-03-11 00:10:52 -05:00
|
|
|
{
|
|
|
|
|
name: "BSFQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ABSFQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSFL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ABSFL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSFW",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ABSFW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSRQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ABSRQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSRL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ABSRL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSRW",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ABSRW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMOVQEQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ACMOVQEQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 8589934592}, // FLAGS
|
|
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // AX FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMOVLEQconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ACMOVLEQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 8589934592}, // FLAGS
|
|
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // AX FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMOVWEQconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ACMOVLEQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 8589934592}, // FLAGS
|
|
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // AX FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMOVQNEconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ACMOVQNE,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 8589934592}, // FLAGS
|
|
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // AX FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMOVLNEconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ACMOVLNE,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 8589934592}, // FLAGS
|
|
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // AX FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMOVWNEconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ACMOVLNE,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 8589934592}, // FLAGS
|
|
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // AX FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSWAPQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ABSWAPQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSWAPL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ABSWAPL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-09-12 13:26:57 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SQRTSD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASQRTSD,
|
2015-09-12 13:26:57 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-09-12 13:26:57 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-09-12 13:26:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SBBQcarrymask",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASBBQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:07:09 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SBBLcarrymask",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASBBL,
|
2015-07-29 17:07:09 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-27 15:45:20 +01:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETEQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETEQ,
|
2015-06-27 15:45:20 +01:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-27 15:45:20 +01:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETNE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETNE,
|
2015-06-27 15:45:20 +01:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-27 15:45:20 +01:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETLT,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETLE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETLE,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-06-10 15:03:06 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETG",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETGT,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 15:03:06 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETGE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETGE,
|
2015-06-10 15:03:06 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 15:03:06 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETB",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETCS,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETBE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETLS,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETA",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETHI,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETAE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETCC,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETEQF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETEQ,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETNEF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETNE,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETORD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETPC,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETNAN",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETPS,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETGF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETHI,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETGEF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETCC,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVBQSX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVBQSX,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVBQZX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVBQZX,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVWQSX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVWQSX,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVWQZX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVWQZX,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVLQSX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVLQSX,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVLQZX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVLQZX,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVB,
|
2015-07-19 15:48:20 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVW,
|
2015-07-19 15:48:20 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVL,
|
2015-07-19 15:48:20 -07:00
|
|
|
reg: regInfo{
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-07-19 15:48:20 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-20 15:14:20 -04:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTTSD2SL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTTSD2SL,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTTSD2SQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTTSD2SQ,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTTSS2SL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTTSS2SL,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTTSS2SQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTTSS2SQ,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSL2SS",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSL2SS,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSL2SD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSL2SD,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSQ2SS",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSQ2SS,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSQ2SD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSQ2SD,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSD2SS",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSD2SS,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSS2SD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSS2SD,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-28 14:24:10 -04:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "PXOR",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.APXOR,
|
2015-08-28 14:24:10 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-28 14:24:10 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-28 14:24:10 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ1",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ2",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ4",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-22 13:46:15 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ8",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-22 13:46:15 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AMOVBLZX,
|
2015-07-22 13:46:15 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBQSXload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVBQSX,
|
2015-07-28 14:58:49 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AMOVWLZX,
|
2015-07-28 14:58:49 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWQSXload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVWQSX,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVL,
|
2015-07-28 14:58:49 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLQSXload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVLQSX,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVQload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVQ,
|
2015-07-28 14:58:49 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:52:25 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVB,
|
2015-07-29 17:52:25 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVL,
|
2015-07-29 17:52:25 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVQstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVOload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVUPS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVOstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVUPS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBloadidx1",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AMOVBLZX,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
2016-02-02 11:13:50 -08:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
},
|
cmd/compile: fix plan9-amd64 build
The previous rules to combine indexed loads produced addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_CX,
Name: NAME_AUTO,
Offset: 121,
...
}
which are erroneous because NAME_AUTO implies a base register of
REG_SP, and cmd/internal/obj/x86 makes many assumptions to this
effect. Note that previously we were also producing an extra "ADDQ
SP, CX" instruction, so indexing off of SP was already handled.
The approach taken by this CL to address the problem is to instead
produce addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_SP,
Name: NAME_AUTO,
Offset: 121,
Index: REG_CX,
Scale: 1,
}
and to omit the "ADDQ SP, CX" instruction.
Downside to this approach is it requires adding a lot of new
MOV[WLQ]loadidx1 instructions that nearly duplicate functionality of
the existing MOV[WLQ]loadidx[248] instructions, but with a different
Scale.
Fixes #15001.
Change-Id: Iad9a1a41e5e2552f8d22e3ba975e4ea0862dffd2
Reviewed-on: https://go-review.googlesource.com/21245
Run-TryBot: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
2016-03-28 19:10:13 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVWloadidx1",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: x86.AMOVWLZX,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVWloadidx2",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AMOVWLZX,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
2016-02-02 11:13:50 -08:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
},
|
cmd/compile: fix plan9-amd64 build
The previous rules to combine indexed loads produced addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_CX,
Name: NAME_AUTO,
Offset: 121,
...
}
which are erroneous because NAME_AUTO implies a base register of
REG_SP, and cmd/internal/obj/x86 makes many assumptions to this
effect. Note that previously we were also producing an extra "ADDQ
SP, CX" instruction, so indexing off of SP was already handled.
The approach taken by this CL to address the problem is to instead
produce addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_SP,
Name: NAME_AUTO,
Offset: 121,
Index: REG_CX,
Scale: 1,
}
and to omit the "ADDQ SP, CX" instruction.
Downside to this approach is it requires adding a lot of new
MOV[WLQ]loadidx1 instructions that nearly duplicate functionality of
the existing MOV[WLQ]loadidx[248] instructions, but with a different
Scale.
Fixes #15001.
Change-Id: Iad9a1a41e5e2552f8d22e3ba975e4ea0862dffd2
Reviewed-on: https://go-review.googlesource.com/21245
Run-TryBot: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
2016-03-28 19:10:13 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVLloadidx1",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: x86.AMOVL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVLloadidx4",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVL,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
cmd/compile: fix plan9-amd64 build
The previous rules to combine indexed loads produced addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_CX,
Name: NAME_AUTO,
Offset: 121,
...
}
which are erroneous because NAME_AUTO implies a base register of
REG_SP, and cmd/internal/obj/x86 makes many assumptions to this
effect. Note that previously we were also producing an extra "ADDQ
SP, CX" instruction, so indexing off of SP was already handled.
The approach taken by this CL to address the problem is to instead
produce addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_SP,
Name: NAME_AUTO,
Offset: 121,
Index: REG_CX,
Scale: 1,
}
and to omit the "ADDQ SP, CX" instruction.
Downside to this approach is it requires adding a lot of new
MOV[WLQ]loadidx1 instructions that nearly duplicate functionality of
the existing MOV[WLQ]loadidx[248] instructions, but with a different
Scale.
Fixes #15001.
Change-Id: Iad9a1a41e5e2552f8d22e3ba975e4ea0862dffd2
Reviewed-on: https://go-review.googlesource.com/21245
Run-TryBot: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
2016-03-28 19:10:13 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVQloadidx1",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: x86.AMOVQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
2016-02-02 11:13:50 -08:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:52:25 +02:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVQloadidx8",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVQ,
|
2016-02-02 11:13:50 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBstoreidx1",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVB,
|
2015-07-29 17:52:25 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-10-21 17:18:07 -07:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVWstoreidx2",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVW,
|
2015-10-21 17:18:07 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 17:18:07 -07:00
|
|
|
},
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVLstoreidx4",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 17:18:07 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVQstoreidx8",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVQ,
|
2015-10-21 17:18:07 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 17:18:07 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-10-21 13:13:56 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVB,
|
2015-10-21 13:13:56 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 13:13:56 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVW,
|
2015-10-21 13:13:56 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 13:13:56 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVL,
|
2015-10-21 13:13:56 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 13:13:56 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVQstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVQ,
|
2015-10-21 13:13:56 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 13:13:56 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-04 15:53:33 -08:00
|
|
|
{
|
|
|
|
|
name: "MOVBstoreconstidx1",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-04 15:53:33 -08:00
|
|
|
asm: x86.AMOVB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-04 15:53:33 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWstoreconstidx2",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-04 15:53:33 -08:00
|
|
|
asm: x86.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-04 15:53:33 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVLstoreconstidx4",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-04 15:53:33 -08:00
|
|
|
asm: x86.AMOVL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-04 15:53:33 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVQstoreconstidx8",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-04 15:53:33 -08:00
|
|
|
asm: x86.AMOVQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-04 15:53:33 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "DUFFZERO",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 128}, // DI
|
|
|
|
|
{1, 65536}, // X0
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934720, // DI FLAGS
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
},
|
2015-10-19 13:56:55 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVOconst",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
2015-10-19 13:56:55 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-10-19 13:56:55 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:52:25 +02:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "REPSTOSQ",
|
|
|
|
|
argLen: 4,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 128}, // DI
|
|
|
|
|
{1, 2}, // CX
|
|
|
|
|
{2, 1}, // AX
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 130, // CX DI
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLstatic",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-11 12:51:33 -07:00
|
|
|
reg: regInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
|
2015-08-11 12:51:33 -07:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLclosure",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-07-29 17:52:25 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 4}, // DX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-08-28 22:51:01 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLdefer",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 22:51:01 -07:00
|
|
|
reg: regInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
|
2015-08-28 22:51:01 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLgo",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 22:51:01 -07:00
|
|
|
reg: regInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
|
2015-08-28 22:51:01 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-09-09 23:56:59 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLinter",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-09-09 23:56:59 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-09-09 23:56:59 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
|
2015-09-09 23:56:59 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "DUFFCOPY",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-10-21 17:18:07 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 128}, // DI
|
|
|
|
|
{1, 64}, // SI
|
2015-10-21 17:18:07 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8590000320, // SI DI X0 FLAGS
|
2015-10-21 17:18:07 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "REPMOVSQ",
|
|
|
|
|
argLen: 4,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 128}, // DI
|
|
|
|
|
{1, 64}, // SI
|
|
|
|
|
{2, 2}, // CX
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 194, // CX SI DI
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "InvertFlags",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{},
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-12 11:22:16 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "LoweredGetG",
|
|
|
|
|
argLen: 1,
|
2015-08-13 13:12:17 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-13 13:12:17 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-08-12 11:22:16 -07:00
|
|
|
},
|
2015-09-11 16:40:05 -04:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "LoweredGetClosurePtr",
|
|
|
|
|
argLen: 0,
|
2015-09-11 16:40:05 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-09-11 16:40:05 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-10-23 19:12:49 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "LoweredNilCheck",
|
|
|
|
|
argLen: 2,
|
2015-10-23 19:12:49 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-10-23 19:12:49 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-10-23 19:12:49 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-11-10 15:35:36 -08:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVQconvert",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMOVQ,
|
2015-11-10 15:35:36 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-11-10 15:35:36 -08:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-11-10 15:35:36 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-05 14:56:26 -08:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagEQ",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagLT_ULT",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagLT_UGT",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagGT_UGT",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagGT_ULT",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
|
2016-03-21 22:57:26 -07:00
|
|
|
{
|
|
|
|
|
name: "ADD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AADD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 31}, // R0 R1 R2 R3 SP
|
|
|
|
|
{1, 31}, // R0 R1 R2 R3 SP
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
31, // R0 R1 R2 R3 SP
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ADDconst",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AADD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 31}, // R0 R1 R2 R3 SP
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
31, // R0 R1 R2 R3 SP
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 0,
|
|
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: arm.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
31, // R0 R1 R2 R3 SP
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMP",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ACMP,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 31}, // R0 R1 R2 R3 SP
|
|
|
|
|
{1, 31}, // R0 R1 R2 R3 SP
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
32, // FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWload",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 31}, // R0 R1 R2 R3 SP
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
31, // R0 R1 R2 R3 SP
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWstore",
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: arm.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 31}, // R0 R1 R2 R3 SP
|
|
|
|
|
{1, 31}, // R0 R1 R2 R3 SP
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CALLstatic",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
clobbers: 15, // R0 R1 R2 R3
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "LessThan",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 32}, // FLAGS
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
31, // R0 R1 R2 R3 SP
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Add8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Add16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Add32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Add64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "AddPtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
|
|
|
|
name: "Add32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Add64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-24 23:52:03 -07:00
|
|
|
{
|
|
|
|
|
name: "SubPtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-24 23:52:03 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
|
|
|
|
name: "Sub32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Sub64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Mul8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Mul16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Mul32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Mul64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
|
|
|
|
name: "Mul32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mul64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 19:14:47 -05:00
|
|
|
{
|
|
|
|
|
name: "Hmul8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul8u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul16u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul32u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-02-05 20:26:18 -08:00
|
|
|
{
|
|
|
|
|
name: "Hmul64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-05 20:26:18 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul64u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-05 20:26:18 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Avg64u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-05 20:26:18 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-17 17:46:06 -05:00
|
|
|
{
|
|
|
|
|
name: "Div8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div8u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div16u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div32u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div64u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 19:51:44 -05:00
|
|
|
{
|
|
|
|
|
name: "Mod8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod8u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod16u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod32u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod64u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "And8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "And16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "And32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "And64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
2015-07-29 17:52:25 +02:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Or8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Or16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Or32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Or64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Xor8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Xor16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Xor32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Xor64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh8x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh8x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh8x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh8x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh16x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh16x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh16x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh16x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh32x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh32x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh32x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh32x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh64x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh64x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh64x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh64x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh8x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh8x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh8x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh8x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh16x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh16x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh8Ux8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh8Ux16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh8Ux32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh8Ux64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16Ux8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16Ux16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16Ux32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16Ux64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32Ux8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32Ux16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32Ux32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32Ux64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64Ux8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64Ux16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64Ux32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64Ux64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-05 22:11:14 -04:00
|
|
|
{
|
|
|
|
|
name: "Lrot8",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-05 22:11:14 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lrot16",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-05 22:11:14 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lrot32",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-05 22:11:14 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lrot64",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-05 22:11:14 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Eq8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Eq16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Eq32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Eq64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
2015-07-27 13:17:45 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "EqPtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-27 13:17:45 -07:00
|
|
|
},
|
|
|
|
|
{
|
2015-09-10 13:53:27 -07:00
|
|
|
name: "EqInter",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-09-10 13:53:27 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "EqSlice",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-27 13:17:45 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
|
|
|
|
name: "Eq32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Eq64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Neq8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Neq16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Neq32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Neq64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
2015-07-27 13:17:45 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "NeqPtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-27 13:17:45 -07:00
|
|
|
},
|
|
|
|
|
{
|
2015-09-10 13:53:27 -07:00
|
|
|
name: "NeqInter",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-09-10 13:53:27 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "NeqSlice",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-27 13:17:45 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
|
|
|
|
name: "Neq32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neq64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less8U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less16U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less32U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less64U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
|
|
|
|
name: "Less32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Less64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq8U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq16U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq32U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq64U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
|
|
|
|
name: "Leq32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Leq64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater8U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater16U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater32U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater64U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
|
|
|
|
name: "Greater32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Greater64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq8U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-24 17:48:22 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq16U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq32U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq64U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
|
|
|
|
name: "Geq32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Geq64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-10 11:25:48 -06:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Not",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-10 11:25:48 -06:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
|
|
|
|
name: "Neg8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-21 16:58:18 +02:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-21 16:58:18 +02:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-21 16:58:18 +02:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-21 16:58:18 +02:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-28 14:24:10 -04:00
|
|
|
{
|
|
|
|
|
name: "Neg32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-29 17:07:09 -07:00
|
|
|
{
|
|
|
|
|
name: "Com8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Com16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Com32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Com64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-03-11 00:10:52 -05:00
|
|
|
{
|
|
|
|
|
name: "Ctz16",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Ctz32",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Ctz64",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Clz16",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Clz32",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Clz64",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Bswap32",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Bswap64",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-09-12 13:26:57 -07:00
|
|
|
{
|
|
|
|
|
name: "Sqrt",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-09-12 13:26:57 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Phi",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: -1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Copy",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-10-19 11:36:07 -04:00
|
|
|
{
|
|
|
|
|
name: "Convert",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-10-19 11:36:07 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-28 14:19:20 -07:00
|
|
|
name: "ConstBool",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxBool,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ConstString",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxString,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ConstNil",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const8",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const16",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const32",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const64",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
|
|
|
|
name: "Const32F",
|
2016-03-11 19:36:54 -06:00
|
|
|
auxType: auxFloat32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const64F",
|
2016-03-11 19:36:54 -06:00
|
|
|
auxType: auxFloat64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 10:26:28 -07:00
|
|
|
{
|
|
|
|
|
name: "ConstInterface",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-08-18 10:26:28 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ConstSlice",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-08-18 10:26:28 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-11-02 08:10:26 -08:00
|
|
|
{
|
|
|
|
|
name: "InitMem",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-11-02 08:10:26 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Arg",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Addr",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SP",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SB",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Func",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Load",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Store",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Move",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-27 15:45:20 +01:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Zero",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-27 15:45:20 +01:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "ClosureCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StaticCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-28 22:51:01 -07:00
|
|
|
{
|
|
|
|
|
name: "DeferCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 22:51:01 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "GoCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 22:51:01 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-09-09 23:56:59 -07:00
|
|
|
{
|
|
|
|
|
name: "InterCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-09-09 23:56:59 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
name: "SignExt8to16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt8to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt8to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt16to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt16to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt32to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt8to16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt8to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt8to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt16to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt16to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt32to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc16to8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc32to8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc32to16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc64to8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc64to16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc64to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-20 15:14:20 -04:00
|
|
|
{
|
|
|
|
|
name: "Cvt32to32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32to64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64to32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64to64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32Fto32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32Fto64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64Fto32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64Fto64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32Fto64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64Fto32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "IsNonNil",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "IsInBounds",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-24 23:52:03 -07:00
|
|
|
{
|
|
|
|
|
name: "IsSliceInBounds",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-24 23:52:03 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-11 09:47:45 -07:00
|
|
|
{
|
2015-10-23 19:12:49 -07:00
|
|
|
name: "NilCheck",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-11 09:47:45 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-12 11:22:16 -07:00
|
|
|
{
|
|
|
|
|
name: "GetG",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-12 11:22:16 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-09-11 16:40:05 -04:00
|
|
|
{
|
|
|
|
|
name: "GetClosurePtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-09-11 16:40:05 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "ArrayIndex",
|
2016-03-01 15:59:15 -08:00
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "PtrIndex",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "OffPtr",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SliceMake",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SlicePtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SliceLen",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SliceCap",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-28 14:24:10 -04:00
|
|
|
{
|
|
|
|
|
name: "ComplexMake",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ComplexReal",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ComplexImag",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StringMake",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StringPtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StringLen",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 10:26:28 -07:00
|
|
|
{
|
|
|
|
|
name: "IMake",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 10:26:28 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-04 15:47:22 -07:00
|
|
|
{
|
|
|
|
|
name: "ITab",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-04 15:47:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 10:26:28 -07:00
|
|
|
{
|
|
|
|
|
name: "IData",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-18 10:26:28 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-01-11 21:05:33 -08:00
|
|
|
{
|
|
|
|
|
name: "StructMake0",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructMake1",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructMake2",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructMake3",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructMake4",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructSelect",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-24 14:51:51 -07:00
|
|
|
name: "StoreReg",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-24 14:51:51 -07:00
|
|
|
name: "LoadReg",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "FwdRef",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-01-14 16:02:23 -08:00
|
|
|
{
|
|
|
|
|
name: "Unknown",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-14 16:02:23 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-24 02:16:19 -07:00
|
|
|
{
|
|
|
|
|
name: "VarDef",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-24 02:16:19 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "VarKill",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-24 02:16:19 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-01-19 09:59:21 -08:00
|
|
|
{
|
|
|
|
|
name: "VarLive",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-19 09:59:21 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
}
|
|
|
|
|
|
2016-03-07 18:00:08 -08:00
|
|
|
func (o Op) Asm() obj.As { return opcodeTable[o].asm }
|
2015-06-06 16:03:33 -07:00
|
|
|
func (o Op) String() string { return opcodeTable[o].name }
|
2016-03-21 22:57:26 -07:00
|
|
|
|
|
|
|
|
var registersAMD64 = [...]Register{
|
|
|
|
|
{0, "AX"},
|
|
|
|
|
{1, "CX"},
|
|
|
|
|
{2, "DX"},
|
|
|
|
|
{3, "BX"},
|
|
|
|
|
{4, "SP"},
|
|
|
|
|
{5, "BP"},
|
|
|
|
|
{6, "SI"},
|
|
|
|
|
{7, "DI"},
|
|
|
|
|
{8, "R8"},
|
|
|
|
|
{9, "R9"},
|
|
|
|
|
{10, "R10"},
|
|
|
|
|
{11, "R11"},
|
|
|
|
|
{12, "R12"},
|
|
|
|
|
{13, "R13"},
|
|
|
|
|
{14, "R14"},
|
|
|
|
|
{15, "R15"},
|
|
|
|
|
{16, "X0"},
|
|
|
|
|
{17, "X1"},
|
|
|
|
|
{18, "X2"},
|
|
|
|
|
{19, "X3"},
|
|
|
|
|
{20, "X4"},
|
|
|
|
|
{21, "X5"},
|
|
|
|
|
{22, "X6"},
|
|
|
|
|
{23, "X7"},
|
|
|
|
|
{24, "X8"},
|
|
|
|
|
{25, "X9"},
|
|
|
|
|
{26, "X10"},
|
|
|
|
|
{27, "X11"},
|
|
|
|
|
{28, "X12"},
|
|
|
|
|
{29, "X13"},
|
|
|
|
|
{30, "X14"},
|
|
|
|
|
{31, "X15"},
|
|
|
|
|
{32, "SB"},
|
|
|
|
|
{33, "FLAGS"},
|
|
|
|
|
}
|
|
|
|
|
var registersARM = [...]Register{
|
|
|
|
|
{0, "R0"},
|
|
|
|
|
{1, "R1"},
|
|
|
|
|
{2, "R2"},
|
|
|
|
|
{3, "R3"},
|
|
|
|
|
{4, "SP"},
|
|
|
|
|
{5, "FLAGS"},
|
|
|
|
|
{6, "SB"},
|
|
|
|
|
}
|