2015-06-06 16:03:33 -07:00
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// autogenerated: do not edit!
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// generated from gen/*Ops.go
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2016-03-01 10:58:06 -08:00
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2015-06-06 16:03:33 -07:00
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package ssa
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2016-03-07 18:00:08 -08:00
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import (
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"cmd/internal/obj"
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2016-03-21 22:57:26 -07:00
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"cmd/internal/obj/arm"
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2016-06-24 14:37:17 -05:00
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"cmd/internal/obj/ppc64"
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2016-03-07 18:00:08 -08:00
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"cmd/internal/obj/x86"
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)
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2015-06-16 11:11:16 -07:00
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2015-06-06 16:03:33 -07:00
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const (
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2015-08-18 14:39:26 -04:00
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BlockInvalid BlockKind = iota
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2015-06-06 16:03:33 -07:00
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BlockAMD64EQ
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BlockAMD64NE
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BlockAMD64LT
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BlockAMD64LE
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BlockAMD64GT
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BlockAMD64GE
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BlockAMD64ULT
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BlockAMD64ULE
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BlockAMD64UGT
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BlockAMD64UGE
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2015-08-18 14:39:26 -04:00
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BlockAMD64EQF
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BlockAMD64NEF
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BlockAMD64ORD
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BlockAMD64NAN
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2015-06-06 16:03:33 -07:00
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2016-03-21 22:57:26 -07:00
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BlockARMEQ
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BlockARMNE
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BlockARMLT
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BlockARMLE
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BlockARMGT
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BlockARMGE
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BlockARMULT
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BlockARMULE
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BlockARMUGT
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BlockARMUGE
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2015-06-06 16:03:33 -07:00
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BlockPlain
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BlockIf
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BlockCall
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2016-03-09 19:27:57 -08:00
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BlockDefer
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2015-10-23 19:12:49 -07:00
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BlockCheck
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2015-09-03 09:09:59 -07:00
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BlockRet
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2015-09-08 21:28:44 -07:00
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BlockRetJmp
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2015-09-09 18:03:41 -07:00
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BlockExit
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BlockFirst
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2016-06-24 14:37:17 -05:00
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BlockPPC64EQ
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BlockPPC64NE
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BlockPPC64LT
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BlockPPC64LE
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BlockPPC64GT
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BlockPPC64GE
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BlockPPC64ULT
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BlockPPC64ULE
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BlockPPC64UGT
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BlockPPC64UGE
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2015-06-06 16:03:33 -07:00
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)
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var blockString = [...]string{
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BlockInvalid: "BlockInvalid",
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BlockAMD64EQ: "EQ",
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BlockAMD64NE: "NE",
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BlockAMD64LT: "LT",
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BlockAMD64LE: "LE",
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BlockAMD64GT: "GT",
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BlockAMD64GE: "GE",
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BlockAMD64ULT: "ULT",
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BlockAMD64ULE: "ULE",
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BlockAMD64UGT: "UGT",
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BlockAMD64UGE: "UGE",
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2015-08-18 14:39:26 -04:00
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BlockAMD64EQF: "EQF",
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BlockAMD64NEF: "NEF",
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BlockAMD64ORD: "ORD",
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BlockAMD64NAN: "NAN",
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2015-06-06 16:03:33 -07:00
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2016-03-21 22:57:26 -07:00
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BlockARMEQ: "EQ",
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BlockARMNE: "NE",
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BlockARMLT: "LT",
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BlockARMLE: "LE",
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BlockARMGT: "GT",
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BlockARMGE: "GE",
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BlockARMULT: "ULT",
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BlockARMULE: "ULE",
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BlockARMUGT: "UGT",
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BlockARMUGE: "UGE",
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2015-09-08 21:28:44 -07:00
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BlockPlain: "Plain",
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BlockIf: "If",
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BlockCall: "Call",
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2016-03-09 19:27:57 -08:00
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BlockDefer: "Defer",
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2015-10-23 19:12:49 -07:00
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BlockCheck: "Check",
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2015-09-08 21:28:44 -07:00
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BlockRet: "Ret",
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BlockRetJmp: "RetJmp",
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2015-09-09 18:03:41 -07:00
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BlockExit: "Exit",
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BlockFirst: "First",
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2016-06-24 14:37:17 -05:00
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BlockPPC64EQ: "EQ",
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BlockPPC64NE: "NE",
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BlockPPC64LT: "LT",
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BlockPPC64LE: "LE",
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BlockPPC64GT: "GT",
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BlockPPC64GE: "GE",
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BlockPPC64ULT: "ULT",
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BlockPPC64ULE: "ULE",
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BlockPPC64UGT: "UGT",
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BlockPPC64UGE: "UGE",
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2015-06-06 16:03:33 -07:00
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}
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func (k BlockKind) String() string { return blockString[k] }
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const (
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OpInvalid Op = iota
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2015-08-12 16:38:11 -04:00
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OpAMD64ADDSS
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OpAMD64ADDSD
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OpAMD64SUBSS
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OpAMD64SUBSD
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OpAMD64MULSS
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OpAMD64MULSD
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OpAMD64DIVSS
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OpAMD64DIVSD
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OpAMD64MOVSSload
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OpAMD64MOVSDload
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OpAMD64MOVSSconst
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OpAMD64MOVSDconst
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2016-03-31 09:34:35 -07:00
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OpAMD64MOVSSloadidx1
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2015-08-12 16:38:11 -04:00
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OpAMD64MOVSSloadidx4
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2016-03-31 09:34:35 -07:00
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OpAMD64MOVSDloadidx1
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2015-08-12 16:38:11 -04:00
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OpAMD64MOVSDloadidx8
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OpAMD64MOVSSstore
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OpAMD64MOVSDstore
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2016-03-31 09:34:35 -07:00
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OpAMD64MOVSSstoreidx1
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2015-08-12 16:38:11 -04:00
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OpAMD64MOVSSstoreidx4
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2016-03-31 09:34:35 -07:00
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OpAMD64MOVSDstoreidx1
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2015-08-12 16:38:11 -04:00
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OpAMD64MOVSDstoreidx8
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2015-07-28 16:04:50 -07:00
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OpAMD64ADDQ
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OpAMD64ADDL
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OpAMD64ADDQconst
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OpAMD64ADDLconst
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OpAMD64SUBQ
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OpAMD64SUBL
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OpAMD64SUBQconst
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OpAMD64SUBLconst
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2015-06-06 16:03:33 -07:00
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OpAMD64MULQ
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2015-07-28 16:04:50 -07:00
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OpAMD64MULL
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2015-06-06 16:03:33 -07:00
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OpAMD64MULQconst
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2015-07-28 16:04:50 -07:00
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OpAMD64MULLconst
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2016-02-05 20:26:18 -08:00
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OpAMD64HMULQ
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2015-08-18 19:14:47 -05:00
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OpAMD64HMULL
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OpAMD64HMULW
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OpAMD64HMULB
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2016-02-05 20:26:18 -08:00
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OpAMD64HMULQU
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2015-08-18 19:14:47 -05:00
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OpAMD64HMULLU
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OpAMD64HMULWU
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OpAMD64HMULBU
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2016-02-05 20:26:18 -08:00
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OpAMD64AVGQU
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2015-08-17 17:46:06 -05:00
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OpAMD64DIVQ
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OpAMD64DIVL
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OpAMD64DIVW
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OpAMD64DIVQU
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OpAMD64DIVLU
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OpAMD64DIVWU
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2015-08-18 19:51:44 -05:00
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OpAMD64MODQ
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OpAMD64MODL
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OpAMD64MODW
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OpAMD64MODQU
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OpAMD64MODLU
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OpAMD64MODWU
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2015-07-28 16:04:50 -07:00
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OpAMD64ANDQ
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OpAMD64ANDL
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OpAMD64ANDQconst
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OpAMD64ANDLconst
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OpAMD64ORQ
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OpAMD64ORL
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OpAMD64ORQconst
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OpAMD64ORLconst
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OpAMD64XORQ
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OpAMD64XORL
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OpAMD64XORQconst
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2015-07-28 16:04:50 -07:00
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OpAMD64XORLconst
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2015-06-06 16:03:33 -07:00
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OpAMD64CMPQ
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2015-07-21 18:06:15 +02:00
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OpAMD64CMPL
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OpAMD64CMPW
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OpAMD64CMPB
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2015-07-28 16:04:50 -07:00
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OpAMD64CMPQconst
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OpAMD64CMPLconst
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OpAMD64CMPWconst
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OpAMD64CMPBconst
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2015-08-18 14:39:26 -04:00
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OpAMD64UCOMISS
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OpAMD64UCOMISD
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2015-06-06 16:03:33 -07:00
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OpAMD64TESTQ
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2015-07-28 16:04:50 -07:00
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OpAMD64TESTL
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OpAMD64TESTW
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2015-06-06 16:03:33 -07:00
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OpAMD64TESTB
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2015-07-28 16:04:50 -07:00
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OpAMD64TESTQconst
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OpAMD64TESTLconst
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OpAMD64TESTWconst
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OpAMD64TESTBconst
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OpAMD64SHLQ
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OpAMD64SHLL
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OpAMD64SHLQconst
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OpAMD64SHLLconst
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OpAMD64SHRQ
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OpAMD64SHRL
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OpAMD64SHRW
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OpAMD64SHRB
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OpAMD64SHRQconst
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OpAMD64SHRLconst
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OpAMD64SHRWconst
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OpAMD64SHRBconst
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OpAMD64SARQ
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OpAMD64SARL
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OpAMD64SARW
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OpAMD64SARB
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OpAMD64SARQconst
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OpAMD64SARLconst
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OpAMD64SARWconst
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OpAMD64SARBconst
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2015-08-05 22:11:14 -04:00
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OpAMD64ROLQconst
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OpAMD64ROLLconst
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OpAMD64ROLWconst
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OpAMD64ROLBconst
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2015-07-28 16:04:50 -07:00
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OpAMD64NEGQ
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OpAMD64NEGL
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2015-07-29 17:07:09 -07:00
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OpAMD64NOTQ
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OpAMD64NOTL
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2016-03-11 00:10:52 -05:00
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OpAMD64BSFQ
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OpAMD64BSFL
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OpAMD64BSFW
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OpAMD64BSRQ
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OpAMD64BSRL
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OpAMD64BSRW
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OpAMD64CMOVQEQconst
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OpAMD64CMOVLEQconst
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OpAMD64CMOVWEQconst
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OpAMD64CMOVQNEconst
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OpAMD64CMOVLNEconst
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OpAMD64CMOVWNEconst
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OpAMD64BSWAPQ
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OpAMD64BSWAPL
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2015-09-12 13:26:57 -07:00
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OpAMD64SQRTSD
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2015-06-10 10:39:57 -07:00
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OpAMD64SBBQcarrymask
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2015-07-29 17:07:09 -07:00
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OpAMD64SBBLcarrymask
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2015-06-06 16:03:33 -07:00
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OpAMD64SETEQ
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OpAMD64SETNE
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OpAMD64SETL
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2015-06-24 17:48:22 -07:00
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OpAMD64SETLE
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2015-06-06 16:03:33 -07:00
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OpAMD64SETG
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OpAMD64SETGE
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OpAMD64SETB
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2015-07-24 12:47:00 -07:00
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OpAMD64SETBE
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OpAMD64SETA
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OpAMD64SETAE
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2015-08-18 14:39:26 -04:00
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OpAMD64SETEQF
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OpAMD64SETNEF
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OpAMD64SETORD
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OpAMD64SETNAN
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OpAMD64SETGF
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OpAMD64SETGEF
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2015-06-14 11:38:46 -07:00
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OpAMD64MOVBQSX
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2015-07-22 13:46:15 -07:00
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OpAMD64MOVBQZX
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OpAMD64MOVWQSX
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OpAMD64MOVWQZX
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OpAMD64MOVLQSX
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OpAMD64MOVLQZX
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2015-07-28 14:19:20 -07:00
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OpAMD64MOVLconst
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2015-06-06 16:03:33 -07:00
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OpAMD64MOVQconst
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2015-09-01 19:05:44 -05:00
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OpAMD64CVTTSD2SL
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OpAMD64CVTTSD2SQ
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OpAMD64CVTTSS2SL
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OpAMD64CVTTSS2SQ
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2015-08-20 15:14:20 -04:00
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OpAMD64CVTSL2SS
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OpAMD64CVTSL2SD
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OpAMD64CVTSQ2SS
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OpAMD64CVTSQ2SD
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OpAMD64CVTSD2SS
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OpAMD64CVTSS2SD
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2015-08-28 14:24:10 -04:00
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OpAMD64PXOR
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2015-06-06 16:03:33 -07:00
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OpAMD64LEAQ
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2015-06-19 21:02:28 -07:00
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OpAMD64LEAQ1
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2015-06-06 16:03:33 -07:00
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OpAMD64LEAQ2
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OpAMD64LEAQ4
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OpAMD64LEAQ8
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OpAMD64MOVBload
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OpAMD64MOVBQSXload
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2015-06-14 11:38:46 -07:00
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OpAMD64MOVWload
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2016-01-30 11:25:38 -08:00
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OpAMD64MOVWQSXload
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2015-06-14 11:38:46 -07:00
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OpAMD64MOVLload
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2016-01-30 11:25:38 -08:00
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OpAMD64MOVLQSXload
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2015-06-06 16:03:33 -07:00
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OpAMD64MOVQload
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OpAMD64MOVBstore
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2015-06-14 11:38:46 -07:00
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OpAMD64MOVWstore
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OpAMD64MOVLstore
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2015-06-06 16:03:33 -07:00
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OpAMD64MOVQstore
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2016-02-02 11:13:50 -08:00
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OpAMD64MOVOload
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OpAMD64MOVOstore
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OpAMD64MOVBloadidx1
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cmd/compile: fix plan9-amd64 build
The previous rules to combine indexed loads produced addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_CX,
Name: NAME_AUTO,
Offset: 121,
...
}
which are erroneous because NAME_AUTO implies a base register of
REG_SP, and cmd/internal/obj/x86 makes many assumptions to this
effect. Note that previously we were also producing an extra "ADDQ
SP, CX" instruction, so indexing off of SP was already handled.
The approach taken by this CL to address the problem is to instead
produce addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_SP,
Name: NAME_AUTO,
Offset: 121,
Index: REG_CX,
Scale: 1,
}
and to omit the "ADDQ SP, CX" instruction.
Downside to this approach is it requires adding a lot of new
MOV[WLQ]loadidx1 instructions that nearly duplicate functionality of
the existing MOV[WLQ]loadidx[248] instructions, but with a different
Scale.
Fixes #15001.
Change-Id: Iad9a1a41e5e2552f8d22e3ba975e4ea0862dffd2
Reviewed-on: https://go-review.googlesource.com/21245
Run-TryBot: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
2016-03-28 19:10:13 -07:00
|
|
|
OpAMD64MOVWloadidx1
|
2016-02-02 11:13:50 -08:00
|
|
|
OpAMD64MOVWloadidx2
|
cmd/compile: fix plan9-amd64 build
The previous rules to combine indexed loads produced addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_CX,
Name: NAME_AUTO,
Offset: 121,
...
}
which are erroneous because NAME_AUTO implies a base register of
REG_SP, and cmd/internal/obj/x86 makes many assumptions to this
effect. Note that previously we were also producing an extra "ADDQ
SP, CX" instruction, so indexing off of SP was already handled.
The approach taken by this CL to address the problem is to instead
produce addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_SP,
Name: NAME_AUTO,
Offset: 121,
Index: REG_CX,
Scale: 1,
}
and to omit the "ADDQ SP, CX" instruction.
Downside to this approach is it requires adding a lot of new
MOV[WLQ]loadidx1 instructions that nearly duplicate functionality of
the existing MOV[WLQ]loadidx[248] instructions, but with a different
Scale.
Fixes #15001.
Change-Id: Iad9a1a41e5e2552f8d22e3ba975e4ea0862dffd2
Reviewed-on: https://go-review.googlesource.com/21245
Run-TryBot: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
2016-03-28 19:10:13 -07:00
|
|
|
OpAMD64MOVLloadidx1
|
2016-02-02 11:13:50 -08:00
|
|
|
OpAMD64MOVLloadidx4
|
cmd/compile: fix plan9-amd64 build
The previous rules to combine indexed loads produced addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_CX,
Name: NAME_AUTO,
Offset: 121,
...
}
which are erroneous because NAME_AUTO implies a base register of
REG_SP, and cmd/internal/obj/x86 makes many assumptions to this
effect. Note that previously we were also producing an extra "ADDQ
SP, CX" instruction, so indexing off of SP was already handled.
The approach taken by this CL to address the problem is to instead
produce addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_SP,
Name: NAME_AUTO,
Offset: 121,
Index: REG_CX,
Scale: 1,
}
and to omit the "ADDQ SP, CX" instruction.
Downside to this approach is it requires adding a lot of new
MOV[WLQ]loadidx1 instructions that nearly duplicate functionality of
the existing MOV[WLQ]loadidx[248] instructions, but with a different
Scale.
Fixes #15001.
Change-Id: Iad9a1a41e5e2552f8d22e3ba975e4ea0862dffd2
Reviewed-on: https://go-review.googlesource.com/21245
Run-TryBot: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
2016-03-28 19:10:13 -07:00
|
|
|
OpAMD64MOVQloadidx1
|
2016-02-02 11:13:50 -08:00
|
|
|
OpAMD64MOVQloadidx8
|
2016-01-30 11:25:38 -08:00
|
|
|
OpAMD64MOVBstoreidx1
|
2016-03-31 09:34:35 -07:00
|
|
|
OpAMD64MOVWstoreidx1
|
2016-01-30 11:25:38 -08:00
|
|
|
OpAMD64MOVWstoreidx2
|
2016-03-31 09:34:35 -07:00
|
|
|
OpAMD64MOVLstoreidx1
|
2016-01-30 11:25:38 -08:00
|
|
|
OpAMD64MOVLstoreidx4
|
2016-03-31 09:34:35 -07:00
|
|
|
OpAMD64MOVQstoreidx1
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64MOVQstoreidx8
|
2015-10-21 13:13:56 -07:00
|
|
|
OpAMD64MOVBstoreconst
|
|
|
|
|
OpAMD64MOVWstoreconst
|
|
|
|
|
OpAMD64MOVLstoreconst
|
|
|
|
|
OpAMD64MOVQstoreconst
|
2016-02-04 15:53:33 -08:00
|
|
|
OpAMD64MOVBstoreconstidx1
|
2016-03-31 09:34:35 -07:00
|
|
|
OpAMD64MOVWstoreconstidx1
|
2016-02-04 15:53:33 -08:00
|
|
|
OpAMD64MOVWstoreconstidx2
|
2016-03-31 09:34:35 -07:00
|
|
|
OpAMD64MOVLstoreconstidx1
|
2016-02-04 15:53:33 -08:00
|
|
|
OpAMD64MOVLstoreconstidx4
|
2016-03-31 09:34:35 -07:00
|
|
|
OpAMD64MOVQstoreconstidx1
|
2016-02-04 15:53:33 -08:00
|
|
|
OpAMD64MOVQstoreconstidx8
|
2015-09-18 18:23:34 -07:00
|
|
|
OpAMD64DUFFZERO
|
2015-10-19 13:56:55 -07:00
|
|
|
OpAMD64MOVOconst
|
2015-06-27 15:45:20 +01:00
|
|
|
OpAMD64REPSTOSQ
|
2015-06-10 15:03:06 -07:00
|
|
|
OpAMD64CALLstatic
|
|
|
|
|
OpAMD64CALLclosure
|
2015-08-28 22:51:01 -07:00
|
|
|
OpAMD64CALLdefer
|
|
|
|
|
OpAMD64CALLgo
|
2015-09-09 23:56:59 -07:00
|
|
|
OpAMD64CALLinter
|
2015-10-21 17:18:07 -07:00
|
|
|
OpAMD64DUFFCOPY
|
|
|
|
|
OpAMD64REPMOVSQ
|
2015-06-06 16:03:33 -07:00
|
|
|
OpAMD64InvertFlags
|
2015-08-12 11:22:16 -07:00
|
|
|
OpAMD64LoweredGetG
|
2015-09-11 16:40:05 -04:00
|
|
|
OpAMD64LoweredGetClosurePtr
|
2015-10-23 19:12:49 -07:00
|
|
|
OpAMD64LoweredNilCheck
|
2015-11-10 15:35:36 -08:00
|
|
|
OpAMD64MOVQconvert
|
2016-01-05 14:56:26 -08:00
|
|
|
OpAMD64FlagEQ
|
|
|
|
|
OpAMD64FlagLT_ULT
|
|
|
|
|
OpAMD64FlagLT_UGT
|
|
|
|
|
OpAMD64FlagGT_UGT
|
|
|
|
|
OpAMD64FlagGT_ULT
|
2015-06-06 16:03:33 -07:00
|
|
|
|
2016-03-21 22:57:26 -07:00
|
|
|
OpARMADD
|
|
|
|
|
OpARMADDconst
|
2016-05-06 10:13:31 -07:00
|
|
|
OpARMSUB
|
|
|
|
|
OpARMSUBconst
|
|
|
|
|
OpARMRSB
|
|
|
|
|
OpARMRSBconst
|
2016-05-13 15:22:56 -04:00
|
|
|
OpARMMUL
|
|
|
|
|
OpARMHMUL
|
|
|
|
|
OpARMHMULU
|
2016-05-25 09:49:28 -04:00
|
|
|
OpARMDIV
|
|
|
|
|
OpARMDIVU
|
|
|
|
|
OpARMMOD
|
|
|
|
|
OpARMMODU
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
OpARMADDS
|
|
|
|
|
OpARMADC
|
|
|
|
|
OpARMSUBS
|
|
|
|
|
OpARMSBC
|
|
|
|
|
OpARMMULLU
|
|
|
|
|
OpARMMULA
|
2016-05-31 11:27:16 -04:00
|
|
|
OpARMADDF
|
|
|
|
|
OpARMADDD
|
|
|
|
|
OpARMSUBF
|
|
|
|
|
OpARMSUBD
|
|
|
|
|
OpARMMULF
|
|
|
|
|
OpARMMULD
|
|
|
|
|
OpARMDIVF
|
|
|
|
|
OpARMDIVD
|
2016-05-06 10:13:31 -07:00
|
|
|
OpARMAND
|
|
|
|
|
OpARMANDconst
|
|
|
|
|
OpARMOR
|
|
|
|
|
OpARMORconst
|
|
|
|
|
OpARMXOR
|
|
|
|
|
OpARMXORconst
|
|
|
|
|
OpARMBIC
|
|
|
|
|
OpARMBICconst
|
2016-05-13 11:25:07 -04:00
|
|
|
OpARMMVN
|
2016-05-31 11:27:16 -04:00
|
|
|
OpARMSQRTD
|
2016-05-13 15:22:56 -04:00
|
|
|
OpARMSLL
|
|
|
|
|
OpARMSLLconst
|
|
|
|
|
OpARMSRL
|
|
|
|
|
OpARMSRLconst
|
|
|
|
|
OpARMSRA
|
|
|
|
|
OpARMSRAconst
|
2016-05-25 23:17:42 -04:00
|
|
|
OpARMSRRconst
|
2016-03-21 22:57:26 -07:00
|
|
|
OpARMCMP
|
2016-05-06 10:13:31 -07:00
|
|
|
OpARMCMPconst
|
|
|
|
|
OpARMCMN
|
|
|
|
|
OpARMCMNconst
|
|
|
|
|
OpARMTST
|
|
|
|
|
OpARMTSTconst
|
|
|
|
|
OpARMTEQ
|
|
|
|
|
OpARMTEQconst
|
2016-05-31 11:27:16 -04:00
|
|
|
OpARMCMPF
|
|
|
|
|
OpARMCMPD
|
2016-05-06 10:13:31 -07:00
|
|
|
OpARMMOVWconst
|
2016-05-31 11:27:16 -04:00
|
|
|
OpARMMOVFconst
|
|
|
|
|
OpARMMOVDconst
|
2016-06-06 22:36:45 -04:00
|
|
|
OpARMMOVWaddr
|
2016-05-06 10:13:31 -07:00
|
|
|
OpARMMOVBload
|
|
|
|
|
OpARMMOVBUload
|
|
|
|
|
OpARMMOVHload
|
|
|
|
|
OpARMMOVHUload
|
2016-03-21 22:57:26 -07:00
|
|
|
OpARMMOVWload
|
2016-05-31 11:27:16 -04:00
|
|
|
OpARMMOVFload
|
|
|
|
|
OpARMMOVDload
|
2016-05-06 10:13:31 -07:00
|
|
|
OpARMMOVBstore
|
|
|
|
|
OpARMMOVHstore
|
2016-03-21 22:57:26 -07:00
|
|
|
OpARMMOVWstore
|
2016-05-31 11:27:16 -04:00
|
|
|
OpARMMOVFstore
|
|
|
|
|
OpARMMOVDstore
|
2016-05-06 10:13:31 -07:00
|
|
|
OpARMMOVBreg
|
|
|
|
|
OpARMMOVBUreg
|
|
|
|
|
OpARMMOVHreg
|
|
|
|
|
OpARMMOVHUreg
|
2016-05-31 11:27:16 -04:00
|
|
|
OpARMMOVWF
|
|
|
|
|
OpARMMOVWD
|
|
|
|
|
OpARMMOVWUF
|
|
|
|
|
OpARMMOVWUD
|
|
|
|
|
OpARMMOVFW
|
|
|
|
|
OpARMMOVDW
|
|
|
|
|
OpARMMOVFWU
|
|
|
|
|
OpARMMOVDWU
|
|
|
|
|
OpARMMOVFD
|
|
|
|
|
OpARMMOVDF
|
2016-03-21 22:57:26 -07:00
|
|
|
OpARMCALLstatic
|
2016-05-06 10:13:31 -07:00
|
|
|
OpARMCALLclosure
|
|
|
|
|
OpARMCALLdefer
|
|
|
|
|
OpARMCALLgo
|
|
|
|
|
OpARMCALLinter
|
|
|
|
|
OpARMLoweredNilCheck
|
|
|
|
|
OpARMEqual
|
|
|
|
|
OpARMNotEqual
|
2016-03-21 22:57:26 -07:00
|
|
|
OpARMLessThan
|
2016-05-06 10:13:31 -07:00
|
|
|
OpARMLessEqual
|
|
|
|
|
OpARMGreaterThan
|
|
|
|
|
OpARMGreaterEqual
|
|
|
|
|
OpARMLessThanU
|
|
|
|
|
OpARMLessEqualU
|
|
|
|
|
OpARMGreaterThanU
|
|
|
|
|
OpARMGreaterEqualU
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
OpARMCarry
|
|
|
|
|
OpARMLoweredSelect0
|
|
|
|
|
OpARMLoweredSelect1
|
2016-05-25 23:17:42 -04:00
|
|
|
OpARMLoweredZeromask
|
2016-05-13 15:31:14 -04:00
|
|
|
OpARMDUFFZERO
|
|
|
|
|
OpARMDUFFCOPY
|
|
|
|
|
OpARMLoweredZero
|
|
|
|
|
OpARMLoweredMove
|
2016-05-25 09:49:28 -04:00
|
|
|
OpARMLoweredGetClosurePtr
|
|
|
|
|
OpARMMOVWconvert
|
2016-03-21 22:57:26 -07:00
|
|
|
|
2015-07-19 15:48:20 -07:00
|
|
|
OpAdd8
|
|
|
|
|
OpAdd16
|
|
|
|
|
OpAdd32
|
|
|
|
|
OpAdd64
|
|
|
|
|
OpAddPtr
|
2015-08-12 16:38:11 -04:00
|
|
|
OpAdd32F
|
|
|
|
|
OpAdd64F
|
2015-07-19 15:48:20 -07:00
|
|
|
OpSub8
|
|
|
|
|
OpSub16
|
|
|
|
|
OpSub32
|
|
|
|
|
OpSub64
|
2015-08-24 23:52:03 -07:00
|
|
|
OpSubPtr
|
2015-08-12 16:38:11 -04:00
|
|
|
OpSub32F
|
|
|
|
|
OpSub64F
|
2015-07-22 13:46:15 -07:00
|
|
|
OpMul8
|
|
|
|
|
OpMul16
|
|
|
|
|
OpMul32
|
|
|
|
|
OpMul64
|
2015-08-12 16:38:11 -04:00
|
|
|
OpMul32F
|
|
|
|
|
OpMul64F
|
|
|
|
|
OpDiv32F
|
|
|
|
|
OpDiv64F
|
2015-08-18 19:14:47 -05:00
|
|
|
OpHmul8
|
|
|
|
|
OpHmul8u
|
|
|
|
|
OpHmul16
|
|
|
|
|
OpHmul16u
|
|
|
|
|
OpHmul32
|
|
|
|
|
OpHmul32u
|
2016-02-05 20:26:18 -08:00
|
|
|
OpHmul64
|
|
|
|
|
OpHmul64u
|
|
|
|
|
OpAvg64u
|
2015-08-17 17:46:06 -05:00
|
|
|
OpDiv8
|
|
|
|
|
OpDiv8u
|
|
|
|
|
OpDiv16
|
|
|
|
|
OpDiv16u
|
|
|
|
|
OpDiv32
|
|
|
|
|
OpDiv32u
|
|
|
|
|
OpDiv64
|
|
|
|
|
OpDiv64u
|
2015-08-18 19:51:44 -05:00
|
|
|
OpMod8
|
|
|
|
|
OpMod8u
|
|
|
|
|
OpMod16
|
|
|
|
|
OpMod16u
|
|
|
|
|
OpMod32
|
|
|
|
|
OpMod32u
|
|
|
|
|
OpMod64
|
|
|
|
|
OpMod64u
|
2015-07-28 14:58:49 +02:00
|
|
|
OpAnd8
|
|
|
|
|
OpAnd16
|
|
|
|
|
OpAnd32
|
|
|
|
|
OpAnd64
|
2015-07-29 17:52:25 +02:00
|
|
|
OpOr8
|
|
|
|
|
OpOr16
|
|
|
|
|
OpOr32
|
|
|
|
|
OpOr64
|
2015-07-28 16:04:50 -07:00
|
|
|
OpXor8
|
|
|
|
|
OpXor16
|
|
|
|
|
OpXor32
|
|
|
|
|
OpXor64
|
2015-07-29 17:07:09 -07:00
|
|
|
OpLsh8x8
|
|
|
|
|
OpLsh8x16
|
|
|
|
|
OpLsh8x32
|
|
|
|
|
OpLsh8x64
|
|
|
|
|
OpLsh16x8
|
|
|
|
|
OpLsh16x16
|
|
|
|
|
OpLsh16x32
|
|
|
|
|
OpLsh16x64
|
|
|
|
|
OpLsh32x8
|
|
|
|
|
OpLsh32x16
|
|
|
|
|
OpLsh32x32
|
|
|
|
|
OpLsh32x64
|
|
|
|
|
OpLsh64x8
|
|
|
|
|
OpLsh64x16
|
|
|
|
|
OpLsh64x32
|
|
|
|
|
OpLsh64x64
|
|
|
|
|
OpRsh8x8
|
|
|
|
|
OpRsh8x16
|
|
|
|
|
OpRsh8x32
|
|
|
|
|
OpRsh8x64
|
|
|
|
|
OpRsh16x8
|
|
|
|
|
OpRsh16x16
|
|
|
|
|
OpRsh16x32
|
|
|
|
|
OpRsh16x64
|
|
|
|
|
OpRsh32x8
|
|
|
|
|
OpRsh32x16
|
|
|
|
|
OpRsh32x32
|
|
|
|
|
OpRsh32x64
|
|
|
|
|
OpRsh64x8
|
|
|
|
|
OpRsh64x16
|
|
|
|
|
OpRsh64x32
|
|
|
|
|
OpRsh64x64
|
|
|
|
|
OpRsh8Ux8
|
|
|
|
|
OpRsh8Ux16
|
|
|
|
|
OpRsh8Ux32
|
|
|
|
|
OpRsh8Ux64
|
|
|
|
|
OpRsh16Ux8
|
|
|
|
|
OpRsh16Ux16
|
|
|
|
|
OpRsh16Ux32
|
|
|
|
|
OpRsh16Ux64
|
|
|
|
|
OpRsh32Ux8
|
|
|
|
|
OpRsh32Ux16
|
|
|
|
|
OpRsh32Ux32
|
|
|
|
|
OpRsh32Ux64
|
|
|
|
|
OpRsh64Ux8
|
|
|
|
|
OpRsh64Ux16
|
|
|
|
|
OpRsh64Ux32
|
|
|
|
|
OpRsh64Ux64
|
2015-08-05 22:11:14 -04:00
|
|
|
OpLrot8
|
|
|
|
|
OpLrot16
|
|
|
|
|
OpLrot32
|
|
|
|
|
OpLrot64
|
2015-07-19 15:48:20 -07:00
|
|
|
OpEq8
|
|
|
|
|
OpEq16
|
|
|
|
|
OpEq32
|
|
|
|
|
OpEq64
|
2015-07-27 13:17:45 -07:00
|
|
|
OpEqPtr
|
2015-09-10 13:53:27 -07:00
|
|
|
OpEqInter
|
|
|
|
|
OpEqSlice
|
2015-08-18 14:39:26 -04:00
|
|
|
OpEq32F
|
|
|
|
|
OpEq64F
|
2015-07-19 15:48:20 -07:00
|
|
|
OpNeq8
|
|
|
|
|
OpNeq16
|
|
|
|
|
OpNeq32
|
|
|
|
|
OpNeq64
|
2015-07-27 13:17:45 -07:00
|
|
|
OpNeqPtr
|
2015-09-10 13:53:27 -07:00
|
|
|
OpNeqInter
|
|
|
|
|
OpNeqSlice
|
2015-08-18 14:39:26 -04:00
|
|
|
OpNeq32F
|
|
|
|
|
OpNeq64F
|
2015-07-19 15:48:20 -07:00
|
|
|
OpLess8
|
|
|
|
|
OpLess8U
|
|
|
|
|
OpLess16
|
|
|
|
|
OpLess16U
|
|
|
|
|
OpLess32
|
|
|
|
|
OpLess32U
|
|
|
|
|
OpLess64
|
|
|
|
|
OpLess64U
|
2015-08-18 14:39:26 -04:00
|
|
|
OpLess32F
|
|
|
|
|
OpLess64F
|
2015-07-19 15:48:20 -07:00
|
|
|
OpLeq8
|
|
|
|
|
OpLeq8U
|
|
|
|
|
OpLeq16
|
|
|
|
|
OpLeq16U
|
|
|
|
|
OpLeq32
|
|
|
|
|
OpLeq32U
|
|
|
|
|
OpLeq64
|
|
|
|
|
OpLeq64U
|
2015-08-18 14:39:26 -04:00
|
|
|
OpLeq32F
|
|
|
|
|
OpLeq64F
|
2015-07-19 15:48:20 -07:00
|
|
|
OpGreater8
|
|
|
|
|
OpGreater8U
|
|
|
|
|
OpGreater16
|
|
|
|
|
OpGreater16U
|
|
|
|
|
OpGreater32
|
|
|
|
|
OpGreater32U
|
|
|
|
|
OpGreater64
|
|
|
|
|
OpGreater64U
|
2015-08-18 14:39:26 -04:00
|
|
|
OpGreater32F
|
|
|
|
|
OpGreater64F
|
2015-07-19 15:48:20 -07:00
|
|
|
OpGeq8
|
|
|
|
|
OpGeq8U
|
|
|
|
|
OpGeq16
|
|
|
|
|
OpGeq16U
|
|
|
|
|
OpGeq32
|
|
|
|
|
OpGeq32U
|
|
|
|
|
OpGeq64
|
|
|
|
|
OpGeq64U
|
2015-08-18 14:39:26 -04:00
|
|
|
OpGeq32F
|
|
|
|
|
OpGeq64F
|
2016-04-24 21:21:07 +02:00
|
|
|
OpAndB
|
|
|
|
|
OpOrB
|
|
|
|
|
OpEqB
|
|
|
|
|
OpNeqB
|
2015-07-10 11:25:48 -06:00
|
|
|
OpNot
|
2015-07-21 16:58:18 +02:00
|
|
|
OpNeg8
|
|
|
|
|
OpNeg16
|
|
|
|
|
OpNeg32
|
|
|
|
|
OpNeg64
|
2015-08-28 14:24:10 -04:00
|
|
|
OpNeg32F
|
|
|
|
|
OpNeg64F
|
2015-07-29 17:07:09 -07:00
|
|
|
OpCom8
|
|
|
|
|
OpCom16
|
|
|
|
|
OpCom32
|
|
|
|
|
OpCom64
|
2016-03-11 00:10:52 -05:00
|
|
|
OpCtz16
|
|
|
|
|
OpCtz32
|
|
|
|
|
OpCtz64
|
|
|
|
|
OpClz16
|
|
|
|
|
OpClz32
|
|
|
|
|
OpClz64
|
|
|
|
|
OpBswap32
|
|
|
|
|
OpBswap64
|
2015-09-12 13:26:57 -07:00
|
|
|
OpSqrt
|
2015-06-06 16:03:33 -07:00
|
|
|
OpPhi
|
|
|
|
|
OpCopy
|
2015-10-19 11:36:07 -04:00
|
|
|
OpConvert
|
2015-07-28 14:19:20 -07:00
|
|
|
OpConstBool
|
|
|
|
|
OpConstString
|
|
|
|
|
OpConstNil
|
|
|
|
|
OpConst8
|
|
|
|
|
OpConst16
|
|
|
|
|
OpConst32
|
|
|
|
|
OpConst64
|
2015-08-12 16:38:11 -04:00
|
|
|
OpConst32F
|
|
|
|
|
OpConst64F
|
2015-08-18 10:26:28 -07:00
|
|
|
OpConstInterface
|
|
|
|
|
OpConstSlice
|
2015-11-02 08:10:26 -08:00
|
|
|
OpInitMem
|
2015-06-06 16:03:33 -07:00
|
|
|
OpArg
|
2015-06-19 21:02:28 -07:00
|
|
|
OpAddr
|
2015-06-06 16:03:33 -07:00
|
|
|
OpSP
|
2015-06-19 21:02:28 -07:00
|
|
|
OpSB
|
2015-06-06 16:03:33 -07:00
|
|
|
OpFunc
|
|
|
|
|
OpLoad
|
|
|
|
|
OpStore
|
|
|
|
|
OpMove
|
2015-06-27 15:45:20 +01:00
|
|
|
OpZero
|
2015-06-10 15:03:06 -07:00
|
|
|
OpClosureCall
|
2015-06-06 16:03:33 -07:00
|
|
|
OpStaticCall
|
2015-08-28 22:51:01 -07:00
|
|
|
OpDeferCall
|
|
|
|
|
OpGoCall
|
2015-09-09 23:56:59 -07:00
|
|
|
OpInterCall
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
OpSignExt8to16
|
|
|
|
|
OpSignExt8to32
|
|
|
|
|
OpSignExt8to64
|
|
|
|
|
OpSignExt16to32
|
|
|
|
|
OpSignExt16to64
|
|
|
|
|
OpSignExt32to64
|
|
|
|
|
OpZeroExt8to16
|
|
|
|
|
OpZeroExt8to32
|
|
|
|
|
OpZeroExt8to64
|
|
|
|
|
OpZeroExt16to32
|
|
|
|
|
OpZeroExt16to64
|
|
|
|
|
OpZeroExt32to64
|
|
|
|
|
OpTrunc16to8
|
|
|
|
|
OpTrunc32to8
|
|
|
|
|
OpTrunc32to16
|
|
|
|
|
OpTrunc64to8
|
|
|
|
|
OpTrunc64to16
|
|
|
|
|
OpTrunc64to32
|
2015-08-20 15:14:20 -04:00
|
|
|
OpCvt32to32F
|
|
|
|
|
OpCvt32to64F
|
|
|
|
|
OpCvt64to32F
|
|
|
|
|
OpCvt64to64F
|
|
|
|
|
OpCvt32Fto32
|
|
|
|
|
OpCvt32Fto64
|
|
|
|
|
OpCvt64Fto32
|
|
|
|
|
OpCvt64Fto64
|
|
|
|
|
OpCvt32Fto64F
|
|
|
|
|
OpCvt64Fto32F
|
2015-06-06 16:03:33 -07:00
|
|
|
OpIsNonNil
|
|
|
|
|
OpIsInBounds
|
2015-08-24 23:52:03 -07:00
|
|
|
OpIsSliceInBounds
|
2015-10-23 19:12:49 -07:00
|
|
|
OpNilCheck
|
2015-08-12 11:22:16 -07:00
|
|
|
OpGetG
|
2015-09-11 16:40:05 -04:00
|
|
|
OpGetClosurePtr
|
2015-06-06 16:03:33 -07:00
|
|
|
OpArrayIndex
|
|
|
|
|
OpPtrIndex
|
|
|
|
|
OpOffPtr
|
|
|
|
|
OpSliceMake
|
|
|
|
|
OpSlicePtr
|
|
|
|
|
OpSliceLen
|
|
|
|
|
OpSliceCap
|
2015-08-28 14:24:10 -04:00
|
|
|
OpComplexMake
|
|
|
|
|
OpComplexReal
|
|
|
|
|
OpComplexImag
|
2015-06-06 16:03:33 -07:00
|
|
|
OpStringMake
|
|
|
|
|
OpStringPtr
|
|
|
|
|
OpStringLen
|
2015-08-18 10:26:28 -07:00
|
|
|
OpIMake
|
2015-08-04 15:47:22 -07:00
|
|
|
OpITab
|
2015-08-18 10:26:28 -07:00
|
|
|
OpIData
|
2016-01-11 21:05:33 -08:00
|
|
|
OpStructMake0
|
|
|
|
|
OpStructMake1
|
|
|
|
|
OpStructMake2
|
|
|
|
|
OpStructMake3
|
|
|
|
|
OpStructMake4
|
|
|
|
|
OpStructSelect
|
2015-07-24 14:51:51 -07:00
|
|
|
OpStoreReg
|
|
|
|
|
OpLoadReg
|
2015-06-06 16:03:33 -07:00
|
|
|
OpFwdRef
|
2016-01-14 16:02:23 -08:00
|
|
|
OpUnknown
|
2015-08-24 02:16:19 -07:00
|
|
|
OpVarDef
|
|
|
|
|
OpVarKill
|
2016-01-19 09:59:21 -08:00
|
|
|
OpVarLive
|
2016-04-21 19:28:28 -07:00
|
|
|
OpKeepAlive
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
OpInt64Make
|
|
|
|
|
OpInt64Hi
|
|
|
|
|
OpInt64Lo
|
|
|
|
|
OpAdd32carry
|
|
|
|
|
OpAdd32withcarry
|
|
|
|
|
OpSub32carry
|
|
|
|
|
OpSub32withcarry
|
|
|
|
|
OpMul32uhilo
|
|
|
|
|
OpSignmask
|
2016-05-25 23:17:42 -04:00
|
|
|
OpZeromask
|
2016-05-31 11:27:16 -04:00
|
|
|
OpCvt32Uto32F
|
|
|
|
|
OpCvt32Uto64F
|
|
|
|
|
OpCvt32Fto32U
|
|
|
|
|
OpCvt64Fto32U
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
OpSelect0
|
|
|
|
|
OpSelect1
|
2016-06-24 14:37:17 -05:00
|
|
|
|
|
|
|
|
OpPPC64ADD
|
|
|
|
|
OpPPC64ADDconst
|
|
|
|
|
OpPPC64FADD
|
|
|
|
|
OpPPC64FADDS
|
|
|
|
|
OpPPC64SUB
|
|
|
|
|
OpPPC64FSUB
|
|
|
|
|
OpPPC64FSUBS
|
|
|
|
|
OpPPC64MULLD
|
|
|
|
|
OpPPC64MULLW
|
|
|
|
|
OpPPC64FMUL
|
|
|
|
|
OpPPC64FMULS
|
|
|
|
|
OpPPC64FDIV
|
|
|
|
|
OpPPC64FDIVS
|
|
|
|
|
OpPPC64AND
|
|
|
|
|
OpPPC64ANDconst
|
|
|
|
|
OpPPC64OR
|
|
|
|
|
OpPPC64ORconst
|
|
|
|
|
OpPPC64XOR
|
|
|
|
|
OpPPC64XORconst
|
|
|
|
|
OpPPC64NEG
|
|
|
|
|
OpPPC64MOVBreg
|
|
|
|
|
OpPPC64MOVBZreg
|
|
|
|
|
OpPPC64MOVHreg
|
|
|
|
|
OpPPC64MOVHZreg
|
|
|
|
|
OpPPC64MOVWreg
|
|
|
|
|
OpPPC64MOVWZreg
|
|
|
|
|
OpPPC64MOVBload
|
|
|
|
|
OpPPC64MOVBZload
|
|
|
|
|
OpPPC64MOVHload
|
|
|
|
|
OpPPC64MOVHZload
|
|
|
|
|
OpPPC64MOVWload
|
|
|
|
|
OpPPC64MOVWZload
|
|
|
|
|
OpPPC64MOVDload
|
|
|
|
|
OpPPC64FMOVDload
|
|
|
|
|
OpPPC64FMOVSload
|
|
|
|
|
OpPPC64MOVBstore
|
|
|
|
|
OpPPC64MOVHstore
|
|
|
|
|
OpPPC64MOVWstore
|
|
|
|
|
OpPPC64MOVDstore
|
|
|
|
|
OpPPC64FMOVDstore
|
|
|
|
|
OpPPC64FMOVSstore
|
|
|
|
|
OpPPC64MOVBstoreconst
|
|
|
|
|
OpPPC64MOVHstoreconst
|
|
|
|
|
OpPPC64MOVWstoreconst
|
|
|
|
|
OpPPC64MOVDstoreconst
|
|
|
|
|
OpPPC64MOVDconst
|
|
|
|
|
OpPPC64MOVWconst
|
|
|
|
|
OpPPC64MOVHconst
|
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OpPPC64MOVBconst
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OpPPC64FMOVDconst
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OpPPC64FMOVSconst
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OpPPC64FCMPU
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OpPPC64CMP
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OpPPC64CMPU
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OpPPC64CMPW
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OpPPC64CMPWU
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OpPPC64CMPconst
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OpPPC64CALLstatic
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OpPPC64Equal
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OpPPC64NotEqual
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OpPPC64LessThan
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OpPPC64LessEqual
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OpPPC64GreaterThan
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OpPPC64GreaterEqual
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2015-06-06 16:03:33 -07:00
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)
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var opcodeTable = [...]opInfo{
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{name: "OpInvalid"},
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2015-08-12 16:38:11 -04:00
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{
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2016-03-10 13:05:56 -08:00
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name: "ADDSS",
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argLen: 2,
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commutative: true,
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resultInArg0: true,
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asm: x86.AADDSS,
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2015-08-12 16:38:11 -04:00
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reg: regInfo{
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2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
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2016-03-22 09:43:28 -07:00
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{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
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{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
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2015-08-12 16:38:11 -04:00
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},
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outputs: []regMask{
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2016-03-22 09:43:28 -07:00
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4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
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2015-08-12 16:38:11 -04:00
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},
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},
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},
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{
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2016-03-10 13:05:56 -08:00
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name: "ADDSD",
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argLen: 2,
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commutative: true,
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resultInArg0: true,
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asm: x86.AADDSD,
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2015-08-12 16:38:11 -04:00
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reg: regInfo{
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2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
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2016-03-22 09:43:28 -07:00
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{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
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{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
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2015-08-12 16:38:11 -04:00
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},
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outputs: []regMask{
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2016-03-22 09:43:28 -07:00
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4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
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2015-08-12 16:38:11 -04:00
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},
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},
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},
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{
|
2016-03-10 13:05:56 -08:00
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name: "SUBSS",
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argLen: 2,
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resultInArg0: true,
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asm: x86.ASUBSS,
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2015-08-12 16:38:11 -04:00
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reg: regInfo{
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2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
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2016-03-22 09:43:28 -07:00
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{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
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{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
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2015-08-12 16:38:11 -04:00
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},
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2016-03-22 09:43:28 -07:00
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clobbers: 2147483648, // X15
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2015-08-12 16:38:11 -04:00
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outputs: []regMask{
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2016-03-22 09:43:28 -07:00
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2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
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2015-08-12 16:38:11 -04:00
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},
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},
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},
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{
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2016-03-10 13:05:56 -08:00
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name: "SUBSD",
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argLen: 2,
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resultInArg0: true,
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asm: x86.ASUBSD,
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2015-08-12 16:38:11 -04:00
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reg: regInfo{
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2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
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{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
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{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
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2015-08-12 16:38:11 -04:00
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},
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2016-03-22 09:43:28 -07:00
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clobbers: 2147483648, // X15
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2015-08-12 16:38:11 -04:00
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outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
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2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
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2015-08-12 16:38:11 -04:00
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},
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},
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},
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{
|
2016-03-10 13:05:56 -08:00
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name: "MULSS",
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argLen: 2,
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commutative: true,
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resultInArg0: true,
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asm: x86.AMULSS,
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2015-08-12 16:38:11 -04:00
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reg: regInfo{
|
2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
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{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
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{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
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},
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outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
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4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
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2015-08-12 16:38:11 -04:00
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},
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},
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},
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{
|
2016-03-10 13:05:56 -08:00
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name: "MULSD",
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argLen: 2,
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commutative: true,
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resultInArg0: true,
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asm: x86.AMULSD,
|
2015-08-12 16:38:11 -04:00
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reg: regInfo{
|
2015-08-11 12:51:33 -07:00
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inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
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{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
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|
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{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
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},
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outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
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},
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|
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},
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},
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{
|
2016-03-10 13:05:56 -08:00
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|
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name: "DIVSS",
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argLen: 2,
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resultInArg0: true,
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|
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asm: x86.ADIVSS,
|
2015-08-12 16:38:11 -04:00
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reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
|
|
|
|
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 2147483648, // X15
|
2015-08-12 16:38:11 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
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},
|
|
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|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "DIVSD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ADIVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
|
|
|
|
{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 2147483648, // X15
|
2015-08-12 16:38:11 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSconst",
|
2016-03-11 19:36:54 -06:00
|
|
|
auxType: auxFloat32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDconst",
|
2016-03-11 19:36:54 -06:00
|
|
|
auxType: auxFloat64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-03-31 09:34:35 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVSSloadidx1",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: x86.AMOVSS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSloadidx4",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-03-31 09:34:35 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVSDloadidx1",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: x86.AMOVSD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDloadidx8",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-03-31 09:34:35 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVSSstoreidx1",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 4,
|
|
|
|
|
asm: x86.AMOVSS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSSstoreidx4",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSS,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-03-31 09:34:35 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVSDstoreidx1",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 4,
|
|
|
|
|
asm: x86.AMOVSD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVSDstoreidx8",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVSD,
|
2015-08-12 16:38:11 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-08-12 16:38:11 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-04-10 08:26:43 -07:00
|
|
|
name: "ADDQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: x86.AADDQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-04-10 08:26:43 -07:00
|
|
|
name: "ADDL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: x86.AADDL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
2016-04-10 08:26:43 -07:00
|
|
|
name: "ADDQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AADDQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-04-10 08:26:43 -07:00
|
|
|
name: "ADDLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AADDL,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-10 11:25:48 -06:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBQ,
|
2015-07-10 11:25:48 -06:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-10 11:25:48 -06:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-10 11:25:48 -06:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-10 11:25:48 -06:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 18:06:15 +02:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBQ,
|
2015-07-21 18:06:15 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-21 18:06:15 +02:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SUBLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASUBL,
|
2015-07-21 18:06:15 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-21 18:06:15 +02:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 18:06:15 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AIMULQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AIMULL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AIMULQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-24 17:48:22 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "MULLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AIMULL,
|
2015-06-24 17:48:22 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-24 17:48:22 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-24 17:48:22 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-24 17:48:22 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-05 20:26:18 -08:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULQ,
|
2016-02-05 20:26:18 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-05 20:26:18 -08:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2016-02-05 20:26:18 -08:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2016-02-05 20:26:18 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 19:14:47 -05:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULL,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:14:47 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULW,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:14:47 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIMULB,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:14:47 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-05 20:26:18 -08:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULQU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULQ,
|
2016-02-05 20:26:18 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-05 20:26:18 -08:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2016-02-05 20:26:18 -08:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2016-02-05 20:26:18 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 19:14:47 -05:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULLU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULL,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:14:47 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULWU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULW,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:14:47 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "HMULBU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMULB,
|
2015-08-18 19:14:47 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:14:47 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:14:47 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-05 20:26:18 -08:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "AVGQU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
2016-02-05 20:26:18 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-05 20:26:18 -08:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2016-02-05 20:26:18 -08:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-05 20:26:18 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-17 17:46:06 -05:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVQ,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934596, // DX FLAGS
|
2015-08-17 17:46:06 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
1, // AX
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVL,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934596, // DX FLAGS
|
2015-08-17 17:46:06 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
1, // AX
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVW,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934596, // DX FLAGS
|
2015-08-17 17:46:06 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
1, // AX
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVQU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVQ,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934596, // DX FLAGS
|
2015-08-17 17:46:06 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
1, // AX
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVLU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVL,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934596, // DX FLAGS
|
2015-08-17 17:46:06 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
1, // AX
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "DIVWU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVW,
|
2015-08-17 17:46:06 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934596, // DX FLAGS
|
2015-08-17 17:46:06 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
1, // AX
|
2015-08-17 17:46:06 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 19:51:44 -05:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVQ,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:51:44 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVL,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:51:44 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AIDIVW,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:51:44 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODQU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVQ,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:51:44 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODLU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVL,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:51:44 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MODWU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ADIVW,
|
2015-08-18 19:51:44 -05:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 1}, // AX
|
|
|
|
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 19:51:44 -05:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-08-18 19:51:44 -05:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ANDQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AANDQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ANDL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AANDL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-24 12:47:00 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ANDQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AANDQ,
|
2015-07-24 12:47:00 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-24 12:47:00 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-24 12:47:00 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ANDLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AANDL,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-14 11:38:46 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ORQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AORQ,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-14 11:38:46 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ORL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AORL,
|
2015-07-22 13:46:15 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-22 13:46:15 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 14:19:20 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ORQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AORQ,
|
2015-07-28 14:19:20 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ORLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "XORQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AXORQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "XORL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "XORQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AXORQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "XORLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AXORL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CMPQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ACMPQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CMPL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ACMPL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CMPW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ACMPW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CMPB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ACMPB,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CMPQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ACMPQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CMPLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ACMPL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CMPWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ACMPW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CMPBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ACMPB,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "UCOMISS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AUCOMISS,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "UCOMISD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AUCOMISD,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "TESTQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ATESTQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "TESTL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ATESTL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "TESTW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ATESTW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "TESTB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.ATESTB,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "TESTQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ATESTQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "TESTLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ATESTL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "TESTWconst",
|
|
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ATESTW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "TESTBconst",
|
|
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.ATESTB,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHLQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHLQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-04-10 08:26:43 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHLL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-04-10 08:26:43 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHLQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHLQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHLLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHLL,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-04-10 08:26:43 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:19:20 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRL,
|
2015-07-28 14:19:20 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 14:19:20 -07:00
|
|
|
outputs: []regMask{
|
2016-04-10 08:26:43 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:19:20 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRW,
|
2015-07-28 14:19:20 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 14:19:20 -07:00
|
|
|
outputs: []regMask{
|
2016-04-10 08:26:43 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:19:20 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-04-10 08:26:43 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRWconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRW,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SHRBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASHRB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-19 21:02:28 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-04-10 08:26:43 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-04-10 08:26:43 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARW,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-04-10 08:26:43 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 2}, // CX
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-04-10 08:26:43 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-14 11:38:46 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARQ,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-14 11:38:46 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARL,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-14 11:38:46 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARWconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARW,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "SARBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ASARB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-05 22:11:14 -04:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ROLQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AROLQ,
|
2015-08-05 22:11:14 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-08-05 22:11:14 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ROLLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AROLL,
|
2015-08-05 22:11:14 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-08-05 22:11:14 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ROLWconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AROLW,
|
2015-08-05 22:11:14 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-08-05 22:11:14 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "ROLBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.AROLB,
|
2015-08-05 22:11:14 -04:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-08-05 22:11:14 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-05 22:11:14 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "NEGQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ANEGQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-14 11:38:46 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "NEGL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ANEGL,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:07:09 -07:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "NOTQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ANOTQ,
|
2015-07-29 17:07:09 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-29 17:07:09 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "NOTL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ANOTL,
|
2015-07-29 17:07:09 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-07-29 17:07:09 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-03-11 00:10:52 -05:00
|
|
|
{
|
|
|
|
|
name: "BSFQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ABSFQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSFL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ABSFL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSFW",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ABSFW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSRQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ABSRQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSRL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ABSRL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSRW",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ABSRW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMOVQEQconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ACMOVQEQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 8589934592}, // FLAGS
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // AX FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMOVLEQconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ACMOVLEQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 8589934592}, // FLAGS
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // AX FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMOVWEQconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ACMOVLEQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 8589934592}, // FLAGS
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // AX FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMOVQNEconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ACMOVQNE,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 8589934592}, // FLAGS
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // AX FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMOVLNEconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ACMOVLNE,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 8589934592}, // FLAGS
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // AX FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMOVWNEconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ACMOVLNE,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 8589934592}, // FLAGS
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65518}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934593, // AX FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSWAPQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ABSWAPQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BSWAPL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.ABSWAPL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-04-10 08:26:43 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-03-11 00:10:52 -05:00
|
|
|
},
|
|
|
|
|
clobbers: 8589934592, // FLAGS
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-09-12 13:26:57 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SQRTSD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASQRTSD,
|
2015-09-12 13:26:57 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-09-12 13:26:57 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-09-12 13:26:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SBBQcarrymask",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASBBQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:07:09 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SBBLcarrymask",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASBBL,
|
2015-07-29 17:07:09 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:07:09 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-27 15:45:20 +01:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETEQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETEQ,
|
2015-06-27 15:45:20 +01:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-27 15:45:20 +01:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETNE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETNE,
|
2015-06-27 15:45:20 +01:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-27 15:45:20 +01:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETLT,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETLE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETLE,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-06-10 15:03:06 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETG",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETGT,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 15:03:06 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETGE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETGE,
|
2015-06-10 15:03:06 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-10 15:03:06 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETB",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETCS,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETBE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETLS,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETA",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETHI,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETAE",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETCC,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETEQF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETEQ,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETNEF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETNE,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934593, // AX FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65518, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETORD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETPC,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETNAN",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETPS,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETGF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETHI,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "SETGEF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ASETCC,
|
2015-08-18 14:39:26 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 8589934592}, // FLAGS
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-18 14:39:26 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVBQSX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVBQSX,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVBQZX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVBQZX,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVWQSX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVWQSX,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVWQZX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVWQZX,
|
2015-06-14 11:38:46 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVLQSX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVLQSX,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVLQZX",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.AMOVLQZX,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLconst",
|
|
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVL,
|
2015-07-19 15:48:20 -07:00
|
|
|
reg: regInfo{
|
2015-07-28 16:04:50 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVQconst",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: x86.AMOVQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-07-19 15:48:20 -07:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-20 15:14:20 -04:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTTSD2SL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTTSD2SL,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTTSD2SQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTTSD2SQ,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTTSS2SL",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTTSS2SL,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTTSS2SQ",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTTSS2SQ,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSL2SS",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSL2SS,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSL2SD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSL2SD,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSQ2SS",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSQ2SS,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSQ2SD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSQ2SD,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSD2SS",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSD2SS,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "CVTSS2SD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: x86.ACVTSS2SD,
|
2015-08-20 15:14:20 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-20 15:14:20 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-08-28 14:24:10 -04:00
|
|
|
{
|
2016-03-10 13:05:56 -08:00
|
|
|
name: "PXOR",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
asm: x86.APXOR,
|
2015-08-28 14:24:10 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-28 14:24:10 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-08-28 14:24:10 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ1",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ2",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ4",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-21 16:58:18 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-21 16:58:18 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-22 13:46:15 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "LEAQ8",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-22 13:46:15 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AMOVBLZX,
|
2015-07-22 13:46:15 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBQSXload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVBQSX,
|
2015-07-28 14:58:49 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AMOVWLZX,
|
2015-07-28 14:58:49 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWQSXload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVWQSX,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVL,
|
2015-07-28 14:58:49 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLQSXload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVLQSX,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVQload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVQ,
|
2015-07-28 14:58:49 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:52:25 +02:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVB,
|
2015-07-29 17:52:25 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVW,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVL,
|
2015-07-29 17:52:25 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVQstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVQ,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVOload",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVUPS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVOstore",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVUPS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBloadidx1",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AMOVBLZX,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
2016-02-02 11:13:50 -08:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
},
|
cmd/compile: fix plan9-amd64 build
The previous rules to combine indexed loads produced addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_CX,
Name: NAME_AUTO,
Offset: 121,
...
}
which are erroneous because NAME_AUTO implies a base register of
REG_SP, and cmd/internal/obj/x86 makes many assumptions to this
effect. Note that previously we were also producing an extra "ADDQ
SP, CX" instruction, so indexing off of SP was already handled.
The approach taken by this CL to address the problem is to instead
produce addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_SP,
Name: NAME_AUTO,
Offset: 121,
Index: REG_CX,
Scale: 1,
}
and to omit the "ADDQ SP, CX" instruction.
Downside to this approach is it requires adding a lot of new
MOV[WLQ]loadidx1 instructions that nearly duplicate functionality of
the existing MOV[WLQ]loadidx[248] instructions, but with a different
Scale.
Fixes #15001.
Change-Id: Iad9a1a41e5e2552f8d22e3ba975e4ea0862dffd2
Reviewed-on: https://go-review.googlesource.com/21245
Run-TryBot: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
2016-03-28 19:10:13 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVWloadidx1",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: x86.AMOVWLZX,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVWloadidx2",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-15 17:01:26 +03:00
|
|
|
asm: x86.AMOVWLZX,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
2016-02-02 11:13:50 -08:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
},
|
cmd/compile: fix plan9-amd64 build
The previous rules to combine indexed loads produced addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_CX,
Name: NAME_AUTO,
Offset: 121,
...
}
which are erroneous because NAME_AUTO implies a base register of
REG_SP, and cmd/internal/obj/x86 makes many assumptions to this
effect. Note that previously we were also producing an extra "ADDQ
SP, CX" instruction, so indexing off of SP was already handled.
The approach taken by this CL to address the problem is to instead
produce addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_SP,
Name: NAME_AUTO,
Offset: 121,
Index: REG_CX,
Scale: 1,
}
and to omit the "ADDQ SP, CX" instruction.
Downside to this approach is it requires adding a lot of new
MOV[WLQ]loadidx1 instructions that nearly duplicate functionality of
the existing MOV[WLQ]loadidx[248] instructions, but with a different
Scale.
Fixes #15001.
Change-Id: Iad9a1a41e5e2552f8d22e3ba975e4ea0862dffd2
Reviewed-on: https://go-review.googlesource.com/21245
Run-TryBot: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
2016-03-28 19:10:13 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVLloadidx1",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: x86.AMOVL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVLloadidx4",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVL,
|
2016-01-30 11:25:38 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
cmd/compile: fix plan9-amd64 build
The previous rules to combine indexed loads produced addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_CX,
Name: NAME_AUTO,
Offset: 121,
...
}
which are erroneous because NAME_AUTO implies a base register of
REG_SP, and cmd/internal/obj/x86 makes many assumptions to this
effect. Note that previously we were also producing an extra "ADDQ
SP, CX" instruction, so indexing off of SP was already handled.
The approach taken by this CL to address the problem is to instead
produce addresses like:
From: obj.Addr{
Type: TYPE_MEM,
Reg: REG_SP,
Name: NAME_AUTO,
Offset: 121,
Index: REG_CX,
Scale: 1,
}
and to omit the "ADDQ SP, CX" instruction.
Downside to this approach is it requires adding a lot of new
MOV[WLQ]loadidx1 instructions that nearly duplicate functionality of
the existing MOV[WLQ]loadidx[248] instructions, but with a different
Scale.
Fixes #15001.
Change-Id: Iad9a1a41e5e2552f8d22e3ba975e4ea0862dffd2
Reviewed-on: https://go-review.googlesource.com/21245
Run-TryBot: Matthew Dempsky <mdempsky@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@golang.org>
2016-03-28 19:10:13 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVQloadidx1",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: x86.AMOVQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
2016-02-02 11:13:50 -08:00
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
2016-01-30 11:25:38 -08:00
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:52:25 +02:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVQloadidx8",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVQ,
|
2016-02-02 11:13:50 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBstoreidx1",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVB,
|
2015-07-29 17:52:25 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
2016-03-31 09:34:35 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVWstoreidx1",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 4,
|
|
|
|
|
asm: x86.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-10-21 17:18:07 -07:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVWstoreidx2",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVW,
|
2015-10-21 17:18:07 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 17:18:07 -07:00
|
|
|
},
|
2016-02-02 11:13:50 -08:00
|
|
|
},
|
|
|
|
|
},
|
2016-03-31 09:34:35 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVLstoreidx1",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 4,
|
|
|
|
|
asm: x86.AMOVL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-02 11:13:50 -08:00
|
|
|
{
|
|
|
|
|
name: "MOVLstoreidx4",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 17:18:07 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-03-31 09:34:35 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVQstoreidx1",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 4,
|
|
|
|
|
asm: x86.AMOVQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-10-21 17:18:07 -07:00
|
|
|
{
|
2016-02-02 11:13:50 -08:00
|
|
|
name: "MOVQstoreidx8",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-02-02 11:13:50 -08:00
|
|
|
asm: x86.AMOVQ,
|
2015-10-21 17:18:07 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{2, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 17:18:07 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-10-21 13:13:56 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVBstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVB,
|
2015-10-21 13:13:56 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 13:13:56 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVWstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVW,
|
2015-10-21 13:13:56 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 13:13:56 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVLstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVL,
|
2015-10-21 13:13:56 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 13:13:56 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVQstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-31 11:39:39 -08:00
|
|
|
asm: x86.AMOVQ,
|
2015-10-21 13:13:56 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2015-10-21 13:13:56 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-04 15:53:33 -08:00
|
|
|
{
|
|
|
|
|
name: "MOVBstoreconstidx1",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-04 15:53:33 -08:00
|
|
|
asm: x86.AMOVB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-04 15:53:33 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-03-31 09:34:35 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVWstoreconstidx1",
|
|
|
|
|
auxType: auxSymValAndOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: x86.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-04 15:53:33 -08:00
|
|
|
{
|
|
|
|
|
name: "MOVWstoreconstidx2",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-04 15:53:33 -08:00
|
|
|
asm: x86.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-04 15:53:33 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-03-31 09:34:35 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVLstoreconstidx1",
|
|
|
|
|
auxType: auxSymValAndOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: x86.AMOVL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-04 15:53:33 -08:00
|
|
|
{
|
|
|
|
|
name: "MOVLstoreconstidx4",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-04 15:53:33 -08:00
|
|
|
asm: x86.AMOVL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-04 15:53:33 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-03-31 09:34:35 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVQstoreconstidx1",
|
|
|
|
|
auxType: auxSymValAndOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: x86.AMOVQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-02-04 15:53:33 -08:00
|
|
|
{
|
|
|
|
|
name: "MOVQstoreconstidx8",
|
|
|
|
|
auxType: auxSymValAndOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-02-04 15:53:33 -08:00
|
|
|
asm: x86.AMOVQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
|
|
|
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
|
2016-02-04 15:53:33 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "DUFFZERO",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 128}, // DI
|
|
|
|
|
{1, 65536}, // X0
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934720, // DI FLAGS
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
},
|
2015-10-19 13:56:55 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "MOVOconst",
|
2016-04-20 11:17:41 -07:00
|
|
|
auxType: auxInt128,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-31 11:39:39 -08:00
|
|
|
rematerializeable: true,
|
2015-10-19 13:56:55 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4294901760, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
|
2015-10-19 13:56:55 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-07-29 17:52:25 +02:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "REPSTOSQ",
|
|
|
|
|
argLen: 4,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 128}, // DI
|
|
|
|
|
{1, 2}, // CX
|
|
|
|
|
{2, 1}, // AX
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 130, // CX DI
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLstatic",
|
|
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-11 12:51:33 -07:00
|
|
|
reg: regInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
|
2015-08-11 12:51:33 -07:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLclosure",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-07-29 17:52:25 +02:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{1, 4}, // DX
|
|
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-08-28 22:51:01 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLdefer",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 22:51:01 -07:00
|
|
|
reg: regInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
|
2015-08-28 22:51:01 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLgo",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 22:51:01 -07:00
|
|
|
reg: regInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
|
2015-08-28 22:51:01 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-09-09 23:56:59 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "CALLinter",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-09-09 23:56:59 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65519}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-09-09 23:56:59 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 12884901871, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 FLAGS
|
2015-09-09 23:56:59 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
{
|
2016-01-31 11:39:39 -08:00
|
|
|
name: "DUFFCOPY",
|
|
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-10-21 17:18:07 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 128}, // DI
|
|
|
|
|
{1, 64}, // SI
|
2015-10-21 17:18:07 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8590000320, // SI DI X0 FLAGS
|
2015-10-21 17:18:07 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "REPMOVSQ",
|
|
|
|
|
argLen: 4,
|
2015-07-28 16:04:50 -07:00
|
|
|
reg: regInfo{
|
2015-08-11 12:51:33 -07:00
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 128}, // DI
|
|
|
|
|
{1, 64}, // SI
|
|
|
|
|
{2, 2}, // CX
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 194, // CX SI DI
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "InvertFlags",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{},
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
2015-08-12 11:22:16 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "LoweredGetG",
|
|
|
|
|
argLen: 1,
|
2015-08-13 13:12:17 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-08-13 13:12:17 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-08-12 11:22:16 -07:00
|
|
|
},
|
2015-09-11 16:40:05 -04:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "LoweredGetClosurePtr",
|
|
|
|
|
argLen: 0,
|
2015-09-11 16:40:05 -04:00
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
4, // DX
|
2015-09-11 16:40:05 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-10-23 19:12:49 -07:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "LoweredNilCheck",
|
|
|
|
|
argLen: 2,
|
2015-10-23 19:12:49 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-10-23 19:12:49 -07:00
|
|
|
},
|
2016-03-22 09:43:28 -07:00
|
|
|
clobbers: 8589934592, // FLAGS
|
2015-10-23 19:12:49 -07:00
|
|
|
},
|
|
|
|
|
},
|
2015-11-10 15:35:36 -08:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "MOVQconvert",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: x86.AMOVQ,
|
2015-11-10 15:35:36 -08:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-03-22 09:43:28 -07:00
|
|
|
{0, 65535}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-11-10 15:35:36 -08:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-03-22 09:43:28 -07:00
|
|
|
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
2015-11-10 15:35:36 -08:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-01-05 14:56:26 -08:00
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagEQ",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagLT_ULT",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagLT_UGT",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagGT_UGT",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-27 08:04:48 -06:00
|
|
|
name: "FlagGT_ULT",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{},
|
2016-01-05 14:56:26 -08:00
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
|
2016-03-21 22:57:26 -07:00
|
|
|
{
|
|
|
|
|
name: "ADD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AADD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-03-21 22:57:26 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-05-06 10:13:31 -07:00
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
2016-03-21 22:57:26 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ADDconst",
|
2016-06-06 22:36:45 -04:00
|
|
|
auxType: auxInt32,
|
2016-03-21 22:57:26 -07:00
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AADD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 14335}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SUB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ASUB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-03-21 22:57:26 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-05-06 10:13:31 -07:00
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SUBconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.ASUB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "RSB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ARSB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "RSBconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.ARSB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-13 15:22:56 -04:00
|
|
|
{
|
|
|
|
|
name: "MUL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AMUL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-13 15:22:56 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "HMUL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AMULL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-13 15:22:56 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "HMULU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AMULLU,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-13 15:22:56 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-25 09:49:28 -04:00
|
|
|
{
|
|
|
|
|
name: "DIV",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ADIV,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-25 09:49:28 -04:00
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
clobbers: 4294967296, // FLAGS
|
2016-05-25 09:49:28 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "DIVU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ADIVU,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-25 09:49:28 -04:00
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
clobbers: 4294967296, // FLAGS
|
2016-05-25 09:49:28 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.AMOD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-25 09:49:28 -04:00
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
clobbers: 4294967296, // FLAGS
|
2016-05-25 09:49:28 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MODU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.AMODU,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-25 09:49:28 -04:00
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
clobbers: 4294967296, // FLAGS
|
2016-05-25 09:49:28 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
{
|
|
|
|
|
name: "ADDS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AADD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
clobbers: 4294967296, // FLAGS
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ADC",
|
|
|
|
|
argLen: 3,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AADC,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 11:27:16 -04:00
|
|
|
{2, 4294967296}, // FLAGS
|
|
|
|
|
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SUBS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ASUB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
clobbers: 4294967296, // FLAGS
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SBC",
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: arm.ASBC,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 11:27:16 -04:00
|
|
|
{2, 4294967296}, // FLAGS
|
|
|
|
|
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MULLU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AMULLU,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
clobbers: 1, // R0
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5118, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MULA",
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: arm.AMULA,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
{
|
|
|
|
|
name: "ADDF",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AADDF,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ADDD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AADDD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SUBF",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ASUBF,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SUBD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ASUBD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MULF",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AMULF,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MULD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AMULD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "DIVF",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ADIVF,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "DIVD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ADIVD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-06 10:13:31 -07:00
|
|
|
{
|
|
|
|
|
name: "AND",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AAND,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ANDconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AAND,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "OR",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AORR,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ORconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AORR,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "XOR",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.AEOR,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "XORconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AEOR,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BIC",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ABIC,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "BICconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.ABIC,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-13 11:25:07 -04:00
|
|
|
{
|
|
|
|
|
name: "MVN",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMVN,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-13 11:25:07 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
{
|
|
|
|
|
name: "SQRTD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.ASQRTD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-13 15:22:56 -04:00
|
|
|
{
|
|
|
|
|
name: "SLL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ASLL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-13 15:22:56 -04:00
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
clobbers: 4294967296, // FLAGS
|
2016-05-13 15:22:56 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SLLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.ASLL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-13 15:22:56 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SRL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ASRL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-13 15:22:56 -04:00
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
clobbers: 4294967296, // FLAGS
|
2016-05-13 15:22:56 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SRLconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.ASRL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-13 15:22:56 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SRA",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ASRA,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-13 15:22:56 -04:00
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
clobbers: 4294967296, // FLAGS
|
2016-05-13 15:22:56 -04:00
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SRAconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.ASRA,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-13 15:22:56 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-25 23:17:42 -04:00
|
|
|
{
|
|
|
|
|
name: "SRRconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-25 23:17:42 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-06 10:13:31 -07:00
|
|
|
{
|
|
|
|
|
name: "CMP",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ACMP,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-05-31 11:27:16 -04:00
|
|
|
4294967296, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMPconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.ACMP,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-05-31 11:27:16 -04:00
|
|
|
4294967296, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMN",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ACMN,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-05-31 11:27:16 -04:00
|
|
|
4294967296, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMNconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.ACMN,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-05-31 11:27:16 -04:00
|
|
|
4294967296, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "TST",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.ATST,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-05-31 11:27:16 -04:00
|
|
|
4294967296, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "TSTconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.ATST,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-05-31 11:27:16 -04:00
|
|
|
4294967296, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "TEQ",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: arm.ATEQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-05-31 11:27:16 -04:00
|
|
|
4294967296, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "TEQconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.ATEQ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-05-31 11:27:16 -04:00
|
|
|
4294967296, // FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMPF",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ACMPF,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294967296, // FLAGS
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMPD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.ACMPD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294967296, // FLAGS
|
2016-03-21 22:57:26 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 0,
|
|
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: arm.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-05-06 10:13:31 -07:00
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
2016-03-21 22:57:26 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
{
|
|
|
|
|
name: "MOVFconst",
|
|
|
|
|
auxType: auxFloat64,
|
|
|
|
|
argLen: 0,
|
|
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: arm.AMOVF,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVDconst",
|
|
|
|
|
auxType: auxFloat64,
|
|
|
|
|
argLen: 0,
|
|
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: arm.AMOVD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-06-06 22:36:45 -04:00
|
|
|
{
|
|
|
|
|
name: "MOVWaddr",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: arm.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 8589942784}, // SP SB
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-03-21 22:57:26 -07:00
|
|
|
{
|
2016-05-06 10:13:31 -07:00
|
|
|
name: "MOVBload",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.AMOVB,
|
2016-03-21 22:57:26 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
|
2016-03-21 22:57:26 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-05-06 10:13:31 -07:00
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBUload",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.AMOVBU,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVHload",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.AMOVH,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVHUload",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.AMOVHU,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
2016-03-21 22:57:26 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-04-20 11:17:41 -07:00
|
|
|
name: "MOVWload",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.AMOVW,
|
2016-03-21 22:57:26 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
|
2016-03-21 22:57:26 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-05-06 10:13:31 -07:00
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
{
|
|
|
|
|
name: "MOVFload",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.AMOVF,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
|
2016-05-31 11:27:16 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVDload",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.AMOVD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
|
2016-05-31 11:27:16 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-06 10:13:31 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVBstore",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: arm.AMOVB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVHstore",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: arm.AMOVH,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
|
2016-03-21 22:57:26 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2016-04-20 11:17:41 -07:00
|
|
|
name: "MOVWstore",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: arm.AMOVW,
|
2016-03-21 22:57:26 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{1, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
|
|
|
|
{0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
|
2016-05-31 11:27:16 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVFstore",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: arm.AMOVF,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
|
2016-05-31 11:27:16 -04:00
|
|
|
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVDstore",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: arm.AMOVD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 8589948927}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP SB
|
2016-05-31 11:27:16 -04:00
|
|
|
{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBreg",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVBS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBUreg",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVBU,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVHreg",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVHS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVHUreg",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVHU,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
2016-03-21 22:57:26 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
{
|
|
|
|
|
name: "MOVWF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVWF,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVWD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWUF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVWF,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWUD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVWD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVFW",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVFW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVDW",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVDW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVFWU",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVFW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVDWU",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVDW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVFD",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVFD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVDF",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: arm.AMOVDF,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
4294901760, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-03-21 22:57:26 -07:00
|
|
|
{
|
|
|
|
|
name: "CALLstatic",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CALLclosure",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{1, 128}, // R7
|
|
|
|
|
{0, 13311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP
|
|
|
|
|
},
|
2016-05-31 14:01:34 -04:00
|
|
|
clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CALLdefer",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CALLgo",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CALLinter",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
2016-05-31 14:01:34 -04:00
|
|
|
clobbers: 8589875199, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "LoweredNilCheck",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Equal",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 11:27:16 -04:00
|
|
|
{0, 4294967296}, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "NotEqual",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 11:27:16 -04:00
|
|
|
{0, 4294967296}, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
2016-03-21 22:57:26 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "LessThan",
|
2016-04-20 11:17:41 -07:00
|
|
|
argLen: 1,
|
2016-03-21 22:57:26 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 11:27:16 -04:00
|
|
|
{0, 4294967296}, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "LessEqual",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 11:27:16 -04:00
|
|
|
{0, 4294967296}, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "GreaterThan",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 11:27:16 -04:00
|
|
|
{0, 4294967296}, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "GreaterEqual",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 11:27:16 -04:00
|
|
|
{0, 4294967296}, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "LessThanU",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 11:27:16 -04:00
|
|
|
{0, 4294967296}, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "LessEqualU",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 11:27:16 -04:00
|
|
|
{0, 4294967296}, // FLAGS
|
2016-03-21 22:57:26 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
2016-05-06 10:13:31 -07:00
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "GreaterThanU",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 11:27:16 -04:00
|
|
|
{0, 4294967296}, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "GreaterEqualU",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 11:27:16 -04:00
|
|
|
{0, 4294967296}, // FLAGS
|
2016-05-06 10:13:31 -07:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
2016-03-21 22:57:26 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
{
|
|
|
|
|
name: "Carry",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
2016-05-31 11:27:16 -04:00
|
|
|
4294967296, // FLAGS
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "LoweredSelect0",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1, // R0
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "LoweredSelect1",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
resultInArg0: true,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-25 23:17:42 -04:00
|
|
|
{
|
|
|
|
|
name: "LoweredZeromask",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-25 23:17:42 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-05-13 15:31:14 -04:00
|
|
|
{
|
|
|
|
|
name: "DUFFZERO",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 2}, // R1
|
|
|
|
|
{1, 1}, // R0
|
|
|
|
|
},
|
|
|
|
|
clobbers: 2, // R1
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "DUFFCOPY",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4}, // R2
|
|
|
|
|
{1, 2}, // R1
|
|
|
|
|
},
|
|
|
|
|
clobbers: 7, // R0 R1 R2
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "LoweredZero",
|
|
|
|
|
argLen: 4,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 2}, // R1
|
|
|
|
|
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
clobbers: 4294967298, // R1 FLAGS
|
2016-05-13 15:31:14 -04:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "LoweredMove",
|
|
|
|
|
argLen: 4,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 4}, // R2
|
|
|
|
|
{1, 2}, // R1
|
|
|
|
|
{2, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
clobbers: 4294967302, // R1 R2 FLAGS
|
2016-05-13 15:31:14 -04:00
|
|
|
},
|
|
|
|
|
},
|
2016-05-25 09:49:28 -04:00
|
|
|
{
|
|
|
|
|
name: "LoweredGetClosurePtr",
|
|
|
|
|
argLen: 0,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
128, // R7
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWconvert",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: arm.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
2016-05-31 14:01:34 -04:00
|
|
|
{0, 6143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12
|
2016-05-25 09:49:28 -04:00
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2016-03-21 22:57:26 -07:00
|
|
|
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Add8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Add16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Add32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Add64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "AddPtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
|
|
|
|
name: "Add32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Add64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Sub64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-24 23:52:03 -07:00
|
|
|
{
|
|
|
|
|
name: "SubPtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-24 23:52:03 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
|
|
|
|
name: "Sub32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Sub64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Mul8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Mul16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Mul32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Mul64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-22 13:46:15 -07:00
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
|
|
|
|
name: "Mul32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mul64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 19:14:47 -05:00
|
|
|
{
|
|
|
|
|
name: "Hmul8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul8u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul16u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul32u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:14:47 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-02-05 20:26:18 -08:00
|
|
|
{
|
|
|
|
|
name: "Hmul64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-05 20:26:18 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Hmul64u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-05 20:26:18 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Avg64u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-05 20:26:18 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-17 17:46:06 -05:00
|
|
|
{
|
|
|
|
|
name: "Div8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div8u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div16u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div32u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Div64u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-17 17:46:06 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 19:51:44 -05:00
|
|
|
{
|
|
|
|
|
name: "Mod8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod8u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod16u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod32u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mod64u",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 19:51:44 -05:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-28 14:58:49 +02:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "And8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "And16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "And32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "And64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 14:58:49 +02:00
|
|
|
},
|
2015-07-29 17:52:25 +02:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Or8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Or16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Or32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Or64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-29 17:52:25 +02:00
|
|
|
},
|
2015-07-28 16:04:50 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Xor8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Xor16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Xor32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Xor64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-28 16:04:50 -07:00
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh8x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh8x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh8x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh8x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh16x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh16x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh16x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh16x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh32x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh32x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh32x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh32x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh64x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh64x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh64x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Lsh64x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh8x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh8x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh8x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh8x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh16x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-29 17:07:09 -07:00
|
|
|
name: "Rsh16x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64x8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64x16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64x32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64x64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh8Ux8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh8Ux16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh8Ux32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh8Ux64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16Ux8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16Ux16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16Ux32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh16Ux64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32Ux8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32Ux16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32Ux32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh32Ux64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64Ux8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64Ux16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64Ux32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh64Ux64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-05 22:11:14 -04:00
|
|
|
{
|
|
|
|
|
name: "Lrot8",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-05 22:11:14 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lrot16",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-05 22:11:14 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lrot32",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-05 22:11:14 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lrot64",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-05 22:11:14 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Eq8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Eq16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Eq32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Eq64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
2015-07-27 13:17:45 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "EqPtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-27 13:17:45 -07:00
|
|
|
},
|
|
|
|
|
{
|
2015-09-10 13:53:27 -07:00
|
|
|
name: "EqInter",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-09-10 13:53:27 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "EqSlice",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-27 13:17:45 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
|
|
|
|
name: "Eq32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Eq64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Neq8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Neq16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Neq32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
|
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "Neq64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-19 15:48:20 -07:00
|
|
|
},
|
2015-07-27 13:17:45 -07:00
|
|
|
{
|
2016-02-22 11:19:15 +01:00
|
|
|
name: "NeqPtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-02-22 11:19:15 +01:00
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
2015-07-27 13:17:45 -07:00
|
|
|
},
|
|
|
|
|
{
|
2015-09-10 13:53:27 -07:00
|
|
|
name: "NeqInter",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-09-10 13:53:27 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "NeqSlice",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-27 13:17:45 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
|
|
|
|
name: "Neq32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neq64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less8U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less16U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less32U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Less64U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
|
|
|
|
name: "Less32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Less64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq8U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq16U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq32U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Leq64U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
|
|
|
|
name: "Leq32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Leq64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater8U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater16U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater32U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Greater64U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-07-19 15:48:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
|
|
|
|
name: "Greater32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Greater64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-19 15:48:20 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq8U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-24 17:48:22 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq16U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq32U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-24 17:48:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Geq64U",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 14:39:26 -04:00
|
|
|
{
|
|
|
|
|
name: "Geq32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Geq64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 14:39:26 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-04-24 21:21:07 +02:00
|
|
|
{
|
|
|
|
|
name: "AndB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "OrB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "EqB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "NeqB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-10 11:25:48 -06:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Not",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-10 11:25:48 -06:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-21 16:58:18 +02:00
|
|
|
{
|
|
|
|
|
name: "Neg8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-21 16:58:18 +02:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-21 16:58:18 +02:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-21 16:58:18 +02:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-21 16:58:18 +02:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-28 14:24:10 -04:00
|
|
|
{
|
|
|
|
|
name: "Neg32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Neg64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-07-29 17:07:09 -07:00
|
|
|
{
|
|
|
|
|
name: "Com8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Com16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Com32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Com64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-07-29 17:07:09 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-03-11 00:10:52 -05:00
|
|
|
{
|
|
|
|
|
name: "Ctz16",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Ctz32",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Ctz64",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Clz16",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Clz32",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Clz64",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Bswap32",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Bswap64",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-09-12 13:26:57 -07:00
|
|
|
{
|
|
|
|
|
name: "Sqrt",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-09-12 13:26:57 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Phi",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: -1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Copy",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-10-19 11:36:07 -04:00
|
|
|
{
|
|
|
|
|
name: "Convert",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-10-19 11:36:07 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-28 14:19:20 -07:00
|
|
|
name: "ConstBool",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxBool,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ConstString",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxString,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ConstNil",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const8",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt8,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const16",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt16,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const32",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const64",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-07-28 14:19:20 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-12 16:38:11 -04:00
|
|
|
{
|
|
|
|
|
name: "Const32F",
|
2016-03-11 19:36:54 -06:00
|
|
|
auxType: auxFloat32,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const64F",
|
2016-03-11 19:36:54 -06:00
|
|
|
auxType: auxFloat64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-08-12 16:38:11 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 10:26:28 -07:00
|
|
|
{
|
|
|
|
|
name: "ConstInterface",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-08-18 10:26:28 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ConstSlice",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-08-18 10:26:28 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-11-02 08:10:26 -08:00
|
|
|
{
|
|
|
|
|
name: "InitMem",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-11-02 08:10:26 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Arg",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Addr",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SP",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SB",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Func",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Load",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Store",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Move",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-27 15:45:20 +01:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "Zero",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-27 15:45:20 +01:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "ClosureCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StaticCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSymOff,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-28 22:51:01 -07:00
|
|
|
{
|
|
|
|
|
name: "DeferCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 22:51:01 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "GoCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 22:51:01 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-09-09 23:56:59 -07:00
|
|
|
{
|
|
|
|
|
name: "InterCall",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-09-09 23:56:59 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
name: "SignExt8to16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt8to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt8to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt16to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt16to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SignExt32to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt8to16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt8to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt8to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt16to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt16to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ZeroExt32to64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc16to8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc32to8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc32to16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc64to8",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc64to16",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
[dev.ssa] cmd/compile/internal/ssa: redo how sign extension is handled
For integer types less than a machine register, we have to decide
what the invariants are for the high bits of the register. We used
to set the high bits to the correct extension (sign or zero, as
determined by the type) of the low bits.
This CL makes the compiler ignore the high bits of the register
altogether (they are junk).
On this plus side, this means ops that generate subword results don't
have to worry about correctly extending them. On the minus side,
ops that consume subword arguments have to deal with the input
registers not being correctly extended.
For x86, this tradeoff is probably worth it. Almost all opcodes
have versions that use only the correct subword piece of their
inputs. (The one big exception is array indexing.) Not many opcodes
can correctly sign extend on output.
For other architectures, the tradeoff is probably not so clear, as
they don't have many subword-safe opcodes (e.g. 16-bit compare,
ignoring the high 16/48 bits). Fortunately we can decide whether
we do this per-architecture.
For the machine-independent opcodes, we pretend that the "register"
size is equal to the type width, so sign extension is immaterial.
Opcodes that care about the signedness of the input (e.g. compare,
right shift) have two different variants.
Change-Id: I465484c5734545ee697afe83bc8bf4b53bd9df8d
Reviewed-on: https://go-review.googlesource.com/12600
Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
2015-07-23 14:35:02 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Trunc64to32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-20 15:14:20 -04:00
|
|
|
{
|
|
|
|
|
name: "Cvt32to32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32to64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64to32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64to64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32Fto32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32Fto64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64Fto32",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64Fto64",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32Fto64F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64Fto32F",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-20 15:14:20 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "IsNonNil",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "IsInBounds",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-24 23:52:03 -07:00
|
|
|
{
|
|
|
|
|
name: "IsSliceInBounds",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-24 23:52:03 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-11 09:47:45 -07:00
|
|
|
{
|
2015-10-23 19:12:49 -07:00
|
|
|
name: "NilCheck",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-11 09:47:45 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-12 11:22:16 -07:00
|
|
|
{
|
|
|
|
|
name: "GetG",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-12 11:22:16 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-09-11 16:40:05 -04:00
|
|
|
{
|
|
|
|
|
name: "GetClosurePtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-09-11 16:40:05 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "ArrayIndex",
|
2016-03-01 15:59:15 -08:00
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "PtrIndex",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "OffPtr",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SliceMake",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SlicePtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SliceLen",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "SliceCap",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-28 14:24:10 -04:00
|
|
|
{
|
|
|
|
|
name: "ComplexMake",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ComplexReal",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ComplexImag",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-28 14:24:10 -04:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StringMake",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StringPtr",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "StringLen",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 10:26:28 -07:00
|
|
|
{
|
|
|
|
|
name: "IMake",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2015-08-18 10:26:28 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-04 15:47:22 -07:00
|
|
|
{
|
|
|
|
|
name: "ITab",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-04 15:47:22 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-18 10:26:28 -07:00
|
|
|
{
|
|
|
|
|
name: "IData",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-18 10:26:28 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-01-11 21:05:33 -08:00
|
|
|
{
|
|
|
|
|
name: "StructMake0",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructMake1",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructMake2",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 2,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructMake3",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 3,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructMake4",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 4,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StructSelect",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxInt64,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-11 21:05:33 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
2015-07-24 14:51:51 -07:00
|
|
|
name: "StoreReg",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-24 14:51:51 -07:00
|
|
|
name: "LoadReg",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-07-21 07:10:56 -07:00
|
|
|
name: "FwdRef",
|
2016-04-21 19:28:28 -07:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2015-06-06 16:03:33 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-01-14 16:02:23 -08:00
|
|
|
{
|
|
|
|
|
name: "Unknown",
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 0,
|
2016-01-14 16:02:23 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-08-24 02:16:19 -07:00
|
|
|
{
|
|
|
|
|
name: "VarDef",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-24 02:16:19 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "VarKill",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2015-08-24 02:16:19 -07:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-01-19 09:59:21 -08:00
|
|
|
{
|
|
|
|
|
name: "VarLive",
|
2016-01-31 11:39:39 -08:00
|
|
|
auxType: auxSym,
|
2016-02-27 08:04:48 -06:00
|
|
|
argLen: 1,
|
2016-01-19 09:59:21 -08:00
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-04-21 19:28:28 -07:00
|
|
|
{
|
|
|
|
|
name: "KeepAlive",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
{
|
|
|
|
|
name: "Int64Make",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Int64Hi",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Int64Lo",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Add32carry",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Add32withcarry",
|
|
|
|
|
argLen: 3,
|
|
|
|
|
commutative: true,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Sub32carry",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Sub32withcarry",
|
|
|
|
|
argLen: 3,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mul32uhilo",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Signmask",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-05-25 23:17:42 -04:00
|
|
|
{
|
|
|
|
|
name: "Zeromask",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
2016-05-31 11:27:16 -04:00
|
|
|
{
|
|
|
|
|
name: "Cvt32Uto32F",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32Uto64F",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt32Fto32U",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Cvt64Fto32U",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
[dev.ssa] cmd/compile: decompose 64-bit integer on ARM
Introduce dec64 rules to (generically) decompose 64-bit integer on
32-bit architectures. 64-bit integer is composed/decomposed with
Int64Make/Hi/Lo ops, as for complex types.
The idea of dealing with Add64 is the following:
(Add64 (Int64Make xh xl) (Int64Make yh yl))
->
(Int64Make
(Add32withcarry xh yh (Select0 (Add32carry xl yl)))
(Select1 (Add32carry xl yl)))
where Add32carry returns a tuple (flags,uint32). Select0 and Select1
read the first and the second component of the tuple, respectively.
The two Add32carry will be CSE'd.
Similarly for multiplication, Mul32uhilo returns a tuple (hi, lo).
Also add support of KeepAlive, to fix build after merge.
Tests addressed_ssa.go, array_ssa.go, break_ssa.go, chan_ssa.go,
cmp_ssa.go, ctl_ssa.go, map_ssa.go, and string_ssa.go in
cmd/compile/internal/gc/testdata passed.
Progress on SSA for ARM. Still not complete.
Updates #15365.
Change-Id: I7867c76785a456312de5d8398a6b3f7ca5a4f7ec
Reviewed-on: https://go-review.googlesource.com/23213
Reviewed-by: Keith Randall <khr@golang.org>
2016-05-18 18:14:36 -04:00
|
|
|
{
|
|
|
|
|
name: "Select0",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Select1",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
|
2016-06-24 14:37:17 -05:00
|
|
|
{
|
|
|
|
|
name: "ADD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: ppc64.AADD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ADDconst",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: ppc64.AADD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FADD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: ppc64.AFADD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FADDS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: ppc64.AFADDS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SUB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.ASUB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FSUB",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AFSUB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FSUBS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AFSUBS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MULLD",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: ppc64.AMULLD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MULLW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: ppc64.AMULLW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FMUL",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: ppc64.AFMUL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FMULS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: ppc64.AFMULS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FDIV",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AFDIV,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FDIVS",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AFDIVS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "AND",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: ppc64.AAND,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ANDconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: ppc64.AAND,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "OR",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: ppc64.AOR,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ORconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: ppc64.AOR,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "XOR",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
commutative: true,
|
|
|
|
|
asm: ppc64.AXOR,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "XORconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: ppc64.AXOR,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "NEG",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: ppc64.ANEG,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBreg",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: ppc64.AMOVB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBZreg",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: ppc64.AMOVBZ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVHreg",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: ppc64.AMOVH,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVHZreg",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: ppc64.AMOVHZ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWreg",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: ppc64.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWZreg",
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: ppc64.AMOVWZ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBload",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AMOVB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBZload",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AMOVBZ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVHload",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AMOVH,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVHZload",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AMOVHZ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWload",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWZload",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AMOVWZ,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVDload",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AMOVD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FMOVDload",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AFMOVD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FMOVSload",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AFMOVS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBstore",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: ppc64.AMOVB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVHstore",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: ppc64.AMOVH,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWstore",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: ppc64.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVDstore",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: ppc64.AMOVD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FMOVDstore",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: ppc64.AFMOVD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FMOVSstore",
|
|
|
|
|
auxType: auxSymOff,
|
|
|
|
|
argLen: 3,
|
|
|
|
|
asm: ppc64.AFMOVS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AMOVB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVHstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AMOVH,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVDstoreconst",
|
|
|
|
|
auxType: auxSymValAndOff,
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AMOVD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVDconst",
|
|
|
|
|
auxType: auxInt64,
|
|
|
|
|
argLen: 0,
|
|
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: ppc64.AMOVD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 0,
|
|
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: ppc64.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVHconst",
|
|
|
|
|
auxType: auxInt16,
|
|
|
|
|
argLen: 0,
|
|
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: ppc64.AMOVH,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBconst",
|
|
|
|
|
auxType: auxInt8,
|
|
|
|
|
argLen: 0,
|
|
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: ppc64.AMOVB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FMOVDconst",
|
|
|
|
|
auxType: auxFloat64,
|
|
|
|
|
argLen: 0,
|
|
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: ppc64.AFMOVD,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FMOVSconst",
|
|
|
|
|
auxType: auxFloat32,
|
|
|
|
|
argLen: 0,
|
|
|
|
|
rematerializeable: true,
|
|
|
|
|
asm: ppc64.AFMOVS,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460743713488896, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FCMPU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.AFCMPU,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460752303423488, // CR
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMP",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.ACMP,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460752303423488, // CR
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMPU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.ACMPU,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460752303423488, // CR
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMPW",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.ACMPW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460752303423488, // CR
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMPWU",
|
|
|
|
|
argLen: 2,
|
|
|
|
|
asm: ppc64.ACMPWU,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []inputInfo{
|
|
|
|
|
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
|
|
|
|
},
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
576460752303423488, // CR
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMPconst",
|
|
|
|
|
auxType: auxInt32,
|
|
|
|
|
argLen: 1,
|
|
|
|
|
asm: ppc64.ACMP,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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outputs: []regMask{
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576460752303423488, // CR
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},
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},
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},
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{
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name: "CALLstatic",
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auxType: auxSymOff,
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argLen: 1,
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reg: regInfo{
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clobbers: 576460744787220472, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
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},
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},
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{
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name: "Equal",
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argLen: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 576460752303423488}, // CR
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},
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outputs: []regMask{
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1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "NotEqual",
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argLen: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 576460752303423488}, // CR
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},
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outputs: []regMask{
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1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "LessThan",
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argLen: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 576460752303423488}, // CR
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},
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outputs: []regMask{
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1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "LessEqual",
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argLen: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 576460752303423488}, // CR
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},
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outputs: []regMask{
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1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "GreaterThan",
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argLen: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 576460752303423488}, // CR
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},
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outputs: []regMask{
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1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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{
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name: "GreaterEqual",
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argLen: 1,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 576460752303423488}, // CR
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},
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outputs: []regMask{
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1073731576, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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},
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},
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}
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func (o Op) Asm() obj.As { return opcodeTable[o].asm }
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func (o Op) String() string { return opcodeTable[o].name }
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var registersAMD64 = [...]Register{
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{0, "AX"},
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{1, "CX"},
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{2, "DX"},
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{3, "BX"},
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{4, "SP"},
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{5, "BP"},
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{6, "SI"},
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{7, "DI"},
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{8, "R8"},
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{9, "R9"},
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{10, "R10"},
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{11, "R11"},
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{12, "R12"},
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{13, "R13"},
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{14, "R14"},
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{15, "R15"},
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{16, "X0"},
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{17, "X1"},
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{18, "X2"},
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{19, "X3"},
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{20, "X4"},
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{21, "X5"},
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{22, "X6"},
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{23, "X7"},
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{24, "X8"},
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{25, "X9"},
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{26, "X10"},
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{27, "X11"},
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{28, "X12"},
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{29, "X13"},
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{30, "X14"},
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{31, "X15"},
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{32, "SB"},
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{33, "FLAGS"},
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}
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var gpRegMaskAMD64 = regMask(65519)
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var fpRegMaskAMD64 = regMask(4294901760)
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var flagRegMaskAMD64 = regMask(8589934592)
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var framepointerRegAMD64 = int8(5)
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var registersARM = [...]Register{
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{0, "R0"},
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{1, "R1"},
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{2, "R2"},
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{3, "R3"},
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{4, "R4"},
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{5, "R5"},
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{6, "R6"},
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{7, "R7"},
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{8, "R8"},
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{9, "R9"},
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{10, "g"},
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{11, "R11"},
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{12, "R12"},
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{13, "SP"},
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{14, "R14"},
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{15, "R15"},
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{16, "F0"},
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{17, "F1"},
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{18, "F2"},
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{19, "F3"},
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{20, "F4"},
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{21, "F5"},
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{22, "F6"},
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{23, "F7"},
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{24, "F8"},
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{25, "F9"},
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{26, "F10"},
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{27, "F11"},
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{28, "F12"},
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{29, "F13"},
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{30, "F14"},
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{31, "F15"},
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{32, "FLAGS"},
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{33, "SB"},
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}
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var gpRegMaskARM = regMask(5119)
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var fpRegMaskARM = regMask(4294901760)
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var flagRegMaskARM = regMask(4294967296)
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var framepointerRegARM = int8(-1)
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var registersPPC64 = [...]Register{
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{0, "R0"},
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{1, "SP"},
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{2, "SB"},
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{3, "R3"},
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{4, "R4"},
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{5, "R5"},
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{6, "R6"},
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{7, "R7"},
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{8, "R8"},
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{9, "R9"},
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{10, "R10"},
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{11, "R11"},
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{12, "R12"},
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{13, "R13"},
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{14, "R14"},
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{15, "R15"},
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{16, "R16"},
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{17, "R17"},
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{18, "R18"},
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{19, "R19"},
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{20, "R20"},
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{21, "R21"},
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{22, "R22"},
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{23, "R23"},
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{24, "R24"},
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{25, "R25"},
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{26, "R26"},
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{27, "R27"},
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{28, "R28"},
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{29, "R29"},
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{30, "R30"},
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{31, "R31"},
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{32, "F0"},
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{33, "F1"},
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{34, "F2"},
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{35, "F3"},
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{36, "F4"},
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{37, "F5"},
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{38, "F6"},
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{39, "F7"},
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{40, "F8"},
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{41, "F9"},
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{42, "F10"},
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{43, "F11"},
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{44, "F12"},
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{45, "F13"},
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{46, "F14"},
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{47, "F15"},
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{48, "F16"},
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{49, "F17"},
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{50, "F18"},
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{51, "F19"},
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{52, "F20"},
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{53, "F21"},
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{54, "F22"},
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{55, "F23"},
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{56, "F24"},
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{57, "F25"},
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{58, "F26"},
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{59, "CR"},
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}
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var gpRegMaskPPC64 = regMask(1073731576)
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var fpRegMaskPPC64 = regMask(576460743713488896)
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var flagRegMaskPPC64 = regMask(0)
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var framepointerRegPPC64 = int8(1)
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